Method for manufacturing self-aligning planar two-gate mos transistor on silicon-0n-insulator substrate

FIELD: integrated-circuit manufacture on silicon-on-insulator substrate; transistor structures of extremely minimized size for ultra-high-speed integrated circuits.

SUBSTANCE: proposed method for manufacturing self-aligning planar two-gate MOS transistor on SOI substrate includes production of work and insulator regions of two-gate transistor on wafer surface, modification of hidden oxide, formation of tunnel in hidden oxide, formation of polysilicon gate and drain-source regions; upon formation of insulator and work regions; supporting mask layer is deposited onto substrate surface and ports are opened to gate regions to conduct ionic doping of hidden oxide with fluorine through them; then doped part of oxide under silicon is removed by selective etching to form tunnel in hidden oxide whereupon silicon surface is oxidized in open regions above tunnel and gate is formed; port in supporting layer and tunnel are filled with conductive material, and gate-source regions are produced upon etching supporting layer using gate as mask. Transistor structure channel length is up to 10 nm.

EFFECT: reduced length of transistor structure channel.

2 cl, 1 dwg

 

The invention relates to the production technology of IP on the substrate type silicon on insulator (SOI), and can be used to create transistory structures with extremely minimum sizes for UBIS.

A known method of manufacturing a planar dvuhstvornyh MOSFETs on SOI-structures described in the patents [1, 2]. The method has the following feature. On the SOI substrate are formed workers and the insulating region. Created in the hidden recesses oxide on both sides from the center of the semiconductor island (shutter), then etched tunnel oxide under the future gate. Creates insulation exposed surfaces of silicon (gate dielectric) and a deposited layer of polysilicon that fills the tunnel under the silicon and above. The main disadvantages of this method is that it is impossible to combine the upper and lower electrode of the gate.

In patents [3, 4, 5, 6] for samoobladanie gate electrodes of the ion doping is used. Thus there is a change of the electrical properties of silicon in the channel, which cannot be recovered through subsequent annealing.

For the prototype we have adopted a patent [7] U.S. No. 6482877, which describes how to create the MOS transistor on the SOI substrate, consisting in the following. On the surface of the substrate is formed an auxiliary oxide layer, p is the power of photolithographic methods are packing area. Is doping nitrogen ions hidden SiO2through the support oxide and working silicon layer, a film of silicon oxide creates a layer of oxinitride, which liquid is removed by etching, is formed in a hidden tunnel oxide under the top layer of silicon. Is the gate oxidation of the upper and lower open surface of the silicon that creates insulation top and bottom gate electrodes. On the surface of the silicon deposited doped polysilicon so that filled the tunnel hidden in the oxide, thus forming the upper and lower electrode of the gate. Lithographic methods are Stoke-ishikawae region and is formed by metallization. The main disadvantage of this method is the change of properties of the top layer of silicon associated with doping by a large dose of nitrogen.

The aim of the invention is to provide a transistor structure with a limit for silicon technology dimensions of the channel length of 10 nm.

Our proposed design eliminates korotkokanal effects that affect traditional MOSFET, since the channel length of less than 1 μm. The advantages of planar dvukhatomnogo transistor is determined mainly by the geometry of its elements. The main feature of the production is available is here precise alignment of the upper and lower gate electrode and the gate relative to the discharge-stokovyh areas.

On the SOI wafer, a top silicon layer thickness of 10-200 nm and a hidden layer of oxide 100-400 nm, are formed in the insulating region (LOCOS or STI) and work mesoblast. Then precipitates reference (sub) layer, which serves as a mask during ion implantation and etching. In the reference layer are opened window to the packing areas, forming a nitride spacer, is ion doping fluorine hidden oxide (drawing a). Selective etching is removed, a modified portion of the oxide under the silicon, is formed in a hidden tunnel oxide (drawing b). Creates a gate insulator by oxidizing the silicon layer on both sides. Then the window in the reference layer and the tunnel filled with a conductive material forming the gate electrode (the drawing). After grazing the support layer using the gate as a mask, ion implantation is carried out Stoke-stokovyh areas (drawing) At the final stage of the deposited insulating layer, the exposed contact window is formed metallization (drawing d).

As the main way of combining the upper and lower electrode of the gate, we propose the use of ion implantation of fluorine oxide hidden through the working layer of silicon. When this boundary is modified by fluorine oxide coincides with the boundary of the support oxide. Upon further select the main the removal of the modified oxide and filling the cavities with the material of the shutter, the above boundary condition, the combination of the lower and upper electrodes of the shutter. During thermal oxidation of the upper and lower surfaces of the silicon fluorine atoms trapped in the working layer of silicon during ion implantation egregious to the boundary of the silicon - gate oxide interface. When performing several sequential processes thermal oxidation and liquid etching of the grown oxide is possible to achieve almost complete removal of fluorine atoms of silicon. At the same time, the presence of a small amount of fluorine in the gate dielectric leads to improved performance transistors [9]. During the filling material of the shutter of the tunnel and the upper part of the sealing region, the main requirement is the conformity of deposition and planarization of the topography (the material of the shutter must complete the tunnel window and the reference layer). In the process of planarization material of the stopper is removed from exposed surfaces and remains only in the Windows of the reference layer. After selective removal of the support layer relative to the material of the gate using the gate as a mask, is the doping of the drain-stokovyh areas, this is achieved by the combination of sinks and sources relative to the bolt.

When forming the tunnel under the working layer of silicon is used, the effect of the selective etching of fluorinated who CSOs layer of oxide relative to the undoped oxide. It was observed that when the doping silicon oxide with a photoresistive mask ions F2+, portions of oxide not protected by the photoresist etched faster. As a result of the research showed that the fluorinated layers of oxide in dilute solutions of hydrofluoric acid etched several times faster films of silicon oxide, fluorine-free. Experimentally were obtained according to the selectivity of the etching of the dose of doping, temperature and time of annealing, as well as on the concentration of the solution of hydrofluoric acid. It was determined the optimal dose of doping, which on the one hand must ensure the selectivity of the etching, on the other hand not to make damage to the working silicon layer.

In the drawing, (a, b, C, d) depicts the stages of forming a transistor on SOI-structures.

On the drawing. On a silicon substrate containing a hidden oxide (1), and the upper silicon layer (2) deposited support layer (3), in which methods of photolithography creates a window (4) of the sealing areas on the walls of which is formed of nitride, the spacer (5). Is ion doping fluorine hidden oxide (6) through the top silicon layer.

In the drawing b. Liquid selective etching of the fluorinated layer (6) relative to the undoped (1). Is formed a cavity under the silicon film (7).

To damn the same century Using thermal oxidation is formed isolation (gate dielectric) (8) of the upper and lower electrode of the gate. Deposited polysilicon (9) is filled in the cavity under the silicon (7) and the window (4) in the support layer. Is planarization polysilicon (selective etching of polysilicon (9) relative to the reference layer (3)) prior to the opening of the supporting oxide, then selective removal of the oxide support (3) with regard to the material of the shutter (9). Ion doping (10) drain-stokovyh areas.

In the drawing, the Deposition of insulating oxide (12). Annealing Stoke-ishikawae areas (11). Then the standard ways are opened contact of the window to the gate and drain-istokov regions and metallization is formed.

An example of manufacturing a MOS transistor (for design rules of 0.5 μm).

The original SOI substrate - thickness of the working layer of silicon amounted to 0.15 μm, the thickness of the oxide hidden 0.4 microns.

1. The formation of isolation.

2. Thermal oxidation of Si in a thickness of 10 nm.

3. Deposition of silicon nitride 100 nm.

4. The deposition of the auxiliary layer consisting of a film of SiO2a thickness of 800 nm.

5. Opening Windows to the packing areas.

6. Forming a nitride spacer thickness is 100 nm.

7. Ion doping fluorine oxide hidden. The energy of the fluorine was 60 Kev, a dose of 20 of the ICC.

8. The etching of the tunnel in the UK is item oxide.

9. Thermal oxidation of silicon to a thickness of 18 nm.

10. Conformal deposition of polysilicon 0.8 μm.

11. Planarization polysilicon prior to the opening of the supporting oxide

12. Removing the support layer.

13. Ion implantation Stoke-stokovyh areas.

14. The deposition of the insulating layer of oxide.

15. The formation of metallization.

The proposed method of forming dvukhatomnogo transistor more simply realized with the reduction of topological dimensions of the elements. When scaling the manufacturing technology is not complicated and is possible to implement the optimal design dvukhatomnogo transistor with limit values channel length (up to a value equal to 10 nm).

Thus, we developed a design and a method of manufacturing samozavestna planar dvuhstvornyh transistors, which provide the opportunity to form long-term nanotransistors patterns with the limit for silicon channel length.

Sources of information

1. H.-S.P.Wong, "Beyond the conventional transistor," IBM J.RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002.

2. U.S. patent No. 5120666.

3. U.S. patent No. 5308999.

4. U.S. patent No. 6074920.

5. U.S. patent No. 5736435.

6. U.S. patent No. 6391752.

7. U.S. patent No. 6346446 (prototype).

8. U.S. patent No. 5482877.

9. Hook T.B, Adler E, "The Effects of Fluorine on Parametrics and Reliability in a 0,18 mk 3,5/6,8 nm Dual gate oxide CMOS Technology" IEEE Transaction on Electron Devices, vol.48, No.7, July 2001.

Cab manufacturing samosoglasovannogo dvukhatomnogo planar MOSFET on SOI substrate, including the creation on the surface of the plate workers and insulating regions dvukhatomnogo transistor, the hidden modification of oxide formation in a hidden tunnel oxide, the formation of the polysilicon gate and the drain-stokovyh areas, characterized in that after forming the insulating and workspaces on the surface of the substrate is deposited a reference mask layer, where the exposed window to the packing areas, through them is ion doping fluorine oxide hidden, then selective etching is removed alloy portion of the oxide under the silicon to form in a hidden tunnel oxide, and thereafter oxidizing the silicon surface in open areas above the tunnel and the formation of the shutter, while the window in the reference layer and the tunnel filled with a conductive material, and after grazing supporting layer, using the gate as a mask, forming a flow-ishikawae area.

2. The method according to claim 1, characterized in that when the doping energy of fluoride ions is selected so that the maximum concentrations were closer to the upper limit of the latent oxide, and the magnitude of the dose was 10-12-10-15cm2.



 

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