Digital correlator of receiver of satellite radio-navigation system signals

FIELD: radio navigation aids, applicable in digital correlators of receivers of satellite radio navigation system (SPNS) signals, in particular, in digital correlators of receivers of the SPNS GLONASS (Russia) and GPS (USA) signals.

SUBSTANCE: the legitimate signal in the digital correlator is detected by the hardware, which makes it possible to relieve the load of the processor and use its released resources for solution of additional problems. The digital correlator has a commutator of the SPNS signals, processor, digital mixers, digital controllable carrier-frequency oscillator, units of digital demodulators, accumulating units, programmed delay line, control register, digital controllable code generator, reference code generator and a signal detector. The signal detector is made in the form of a square-law detector realizing the algorithm of computation of five points of the Fourier sixteen point discrete transformation with additional zeroes in the interval of one period of the, c/a code with a subsequent computation of the modules of the transformation results and their incoherent summation and comparison with a variable threshold, whose value is set up depending on the noise power and the number of the incoherent readout. The signal detector has a controller, multiplexer, complex mixer, coherent summation unit, module computation unit, incoherent summation unit, noise power estimation unit, signal presence estimation unit and a unit for determination of the frequency-time coordinates of the global maximum.

EFFECT: provided acceleration of the search and detection of signals.

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The invention relates to the field of navigation and can be used in a digital correlator receivers of signals from satellite navigation systems (SNS), in particular in digital correlators signal receivers SRNS GLONASS (Russia) and GPS (USA).

Known receivers GPSr running simultaneously on signals SRNS GLONASS and GPS, as described in [1] - Riley S., Howard N., Aardoom E., Daly P., P. Silvestrin "A Combined GPS/GLONASS High Precision Receiver for Spase Applications/Pros. Jf ION GPS-95, Palm Springs, CA, US, Sept. 12-15, 1995, p.835-844, as well as in the patent: [2] - EN No. 2146378 (C1), G01S 5/14, 10.03.2000; [3] - EN No. 2167431 (C2)G01S 5/14, 27.01.2001; [4] - EN No. 2178894 (C1), G01S 5/14, 27.01.2002; [5] - EP No. 1052786 (A1), G01S 1/00, G01S 5/14, NV 7/185, 15.11.2000.

The generalized block diagram of these receivers consists of a block of radio frequency conversion unit multi-correlation processing and a processor (computer). The RF unit conversion performs the amplification of the received signals to the desired level, the filtering signal from noise, converting the carrier frequency signals with decreasing frequency, and then converting the signals into digital form. To perform these functions block radio frequency conversion includes analog filters, amplifiers, frequency converters (analog mixers), analog-to-digital converters (discriminatory), as well as shapers clock and heterodyne the x signals. Operation of the frequency conversion signal and the sampling is carried out in block radio frequency conversion in separate channels GLONASS and GPS that is due to differences between the signals of these systems, namely by placing them in different, although close, frequency bands, by using different pseudo-random modulation codes and the use of different methods of individualization (separation) signals. So, the satellites of the SRNS GPS emit signals modulated individual pseudo-random codes on the same carrier frequency, and the satellites of the SRNS GLONASS emit signals modulated by one and the same pseudo-random code on the individual bearing (lettered) frequencies lying in adjacent frequency domain. The outputs of these channels form the outputs of the block radio-frequency Converter. The signals from these outputs, i.e. the converted signals of GLONASS and GPS, go to corresponding inputs of a block of multi-channel correlation processing. Block multichannel correlation processing in conjunction with the processor performs the search and tracking signals GPSr, measurement radionavigation parameters pseudorange and pseudocerastes of the object relative to the satellites, emitting signals GPSr, the transformation of radio navigation options in the navigation data. Each channel unit m is agoonline correlation processing is a digital correlator, connected via the bus data exchange with common to all the channels of the processor, see [2, 1, 2, block 2, items 31÷3N], [3, 1, 2, block 2, items 31÷3N; [4, 1, block 2, items 31÷3N], [5, 4, block 3, items 41÷4N]. The implementation of digital correlators used in the receivers of GPSr is the subject of consideration in this application.

Digital correlators used in the receivers of GPSr [1]-[5], implemented in the model scheme presented in [2, 4], [3, 3], [4, 3], [5, 6]. A similar scheme digital correlator, differing in detail the digital controlled oscillator carrier, also discussed in [6] - EP No. 1067395 (A1), G01S 1/00, G01S 5/02, NV 7/185, 10.01.2001.

In the generic scheme of the digital correlator of the receiver signals GPSr includes switch signals SRNS GLONASS or GPS), a control register, a digital controlled oscillator carrier, digital mixers in-phase and quadrature channels of the processing blocks connected in series digital demodulators and cumulative blocks in-phase and quadrature channels of processing, serially connected digital controlled code generator, generator reference code and a programmable delay line, and drives the cumulative blocks, the control register, qi is the world controlled oscillator carrier, digital controlled code generator and the generator of the reference code are connected via the bus communication with the processor. Signal inputs the switch signal GPSr form the signal input of the digital correlator. Clock inputs drives the cumulative units, digital controlled code generator, digital controlled generator carrier and programmable delay lines form a clock input of the digital correlator. Signal inputs digital mixer connected to the output switch signals GPSr, the digital outputs of the mixers are connected to the signal inputs of blocks of digital demodulators, and the reference inputs digital mixer connected to the outputs of the digital controlled oscillator carrier. The control inputs of the programmable delay line, generator reference code and the switch signals GPSr connected to the corresponding outputs of the control register. The reference inputs of blocks of digital demodulators connected to the corresponding outputs of the programmable delay line.

Basic procedures implemented by the digital correlator receivers of signals GPSr presented in [1]-[6], is the correlation of a signal from the output of the switch signals GPSr, with a copy of the desired signal and accumulate the correlation results in storage cumulative units within a certain inter the Ala of time. Typically, this interval is one millisecond, which corresponds to the length of the pseudorandom code sequence (SRP) of the reference C/a code SRNS GPS and GLONASS. This correlation is performed by multiplying the digital samples of the input signal generated inside the digital correlator local copy of the desired signal, i.e. a copy of the signal of the selected satellite GPSr. The circuit loops tracking delay of the reference code and the frequency of the signal is performed using a processor. The processor reads information from the storage, processes it using the appropriate software and generates the control signals for the digital generator carrier and code, closing the loop tracking.

The tracking procedure is preceded by at the initial stage of the search procedure and the detection signal. Signal search is carried out by the two parameters : frequency and character of the SRP reference code. The set of all positions of the search frequency and the character of the SRP reference code defines the scope of the search. The position shift of the frequency search is performed through discrete frequency changes of the output signals of the digital controlled oscillator carrier. Changing positions of the search characters SRP reference code is carried out by discrete changes the delay of the reference code in the programmable line sedergreen search signal is a sequential search of all the frequency-time positions of the search and comparison of the accumulated results of the correlation processing with a given detection threshold.

Digital correlators signal receivers GPSr presented in [1]-[6], this threshold is set based on the given probabilities passes and false alarms for low level signals. According to research specific time-frequency position of the decision on the absence or presence of a signal at the given position.

Feature digital correlator receivers of signals GPSr presented in [1]-[6], is that comparing the accumulated results of the correlation processing with a given detection threshold and a decision about the presence or absence of the signal produced by the processor, i.e. using only software. This requires some computing resources, increases the load on the processor and reduces the possibility of its use for additional functions not related to the detection of signals.

Known digital correlator receiver signals GPSr described in [7] - EP No. 1063536 (A1), G01S 5/14, NV 7/185, 27.12.2000 ("Digital correlator for a receptor of signals from satellite radio-navigation systems, which attempt to reduce the load on the CPU due to the use of two-stage procedure of the search signal, the essence of which is that the first step is finding a strong signal using the detector signal, the implemented apparatus is passed by means of, and at the second stage (in the case of a negative result in the first stage) is a standard search programmatically. This digital correlator receiver signals GPSr adopted as a prototype.

The digital correlator of the receiver signals GPSr adopted as a prototype, contains (see figure 1) switch 1 signal GPSr, the processor 2, the first 3 and second 4 digital mixers, related, respectively, to the in-phase and quadrature channels of processing, the digital controlled oscillator 5 by the carrier, the first 6 and second 7 blocks of digital demodulators, related, respectively, to the in-phase and quadrature channels of processing, the first 8 and second 9 cumulative units related, respectively, to the in-phase and quadrature channels of processing, the programmable delay line 10, case 11 management, digital controlled generator 12 code generator 13 reference code and the detector signal 14.

Unit 6 digital demodulator contains a group of two digital demodulators 61and 62block 7 digital demodulator contains a group of two digital demodulators 71and 72cumulative unit 8 contains a group of two drives 81and 82and cumulative block 9 contains a group of two drives 91and 92. Signal inputs digital demodulators 61and 62/sub> are interconnected and form a signal input unit 6, the digital outputs of the demodulators 61and 62form a group of outputs of the block 6 and the reference input of the digital demodulator 61and 62form a group of the support unit 6. Signal inputs digital demodulators 71and 72are interconnected and form a signal input unit 7, the digital outputs of the demodulators 71and 72form a group of outputs of the block 7 and the reference inputs digital demodulators 71and 72. form a group of the support unit 7.

The outputs of the drives 81and 82form a group of outputs of the block 8, the signal inputs of the drives 81and 82form a group signal input unit 8, and connected between a clock input drives 81and 82form a clock input unit 8. The outputs of the accumulators 91and 92form a group of outputs of the block 9, the signal inputs drives 91and 92form a group signal input unit 9, and is connected between a clock input drives 91and 92form a clock input unit 9.

The signal inputs of the switch 1 of the SRNS signals to form a signal input of the digital correlator.

Signal inputs digital mixers 3 and 4 are connected to output switch 1 signal GPSr, and their reference inputs are connected respectively with the first and second outputs of the digital controlled oscillator 5 by the carrier.

Signal inputs digital demodulators 6 and 7 are connected to the outputs of the respective digital mixers 3 and 4, and the outputs associated with inputs corresponding cumulative blocks 8 and 9.

Group outputs cumulative units 8 and 9 are connected with the first and second groups of signal inputs of the detector signals 14, and via the bus data exchange with the CPU 2.

The output of the digital controlled oscillator 12 code associated with the signal generator input 13 of the reference code, the output of which is connected with the signal input of the programmable delay line 10.

A group of two outputs controlled delay line 10 is connected with the groups of the reference inputs of the blocks 6 and 7 digital demodulators. The first release in this group, which is formed by the "exact" ("p") a copy of the reference code, coupled to the reference input of the digital demodulator 61and 71and the second output in this group, which is formed by "biased" (d) a copy of the reference code, coupled to the reference input of the digital demodulator 62and 72. The control input of the programmable delay line 10 is connected with the first output of the register 11 of the control, the second output of which is connected with control inputs of switch 1 signal GPSr and generator 13 reference code.

Digital controlled oscillator 5 by the carrier, the case 11 management, digital controlled generator is the op code 12, the generator 13 reference code and the detector signal 14 are connected via the bus communication with the processor 2.

Clock inputs of the digital controlled oscillator 5 by the carrier, cumulative units 8 and 9, the programmable delay line 10, the digital controlled code generator 12 are connected with a clock input digital correlator.

The detector signal 14 in the prototype implements a simple modular detector, performing a comparison of individually modules of the results of the correlation processing in-phase and quadrature channels with the first threshold and their amounts with the second threshold.

In General the operation of the correlator of the prototype is carried out as follows. The inputs of the switch 1 signal GPSr receive sampling signals SRNS GLONASS and GPS generated by the analog-digital Converter unit of the radio-frequency conversion of the signal receiver GPSr. In accordance with the command of the processor 2, issued in register 11 control switch 1 signal GPSr connects to its output signals of one of the SRNS - GLONASS or GPS. The signals selected GPSr arrive at the signal inputs of the digital mixers 3 and 4, the reference inputs are received quadrature signals ("SIN" and "COS") reference frequency with the respective outputs of the digital controlled oscillator 5 by the carrier. Digital controlled oscillator 5 by the carrier providing the supports forming a quadrature intermediate frequency signals of a given character SRNS GLONASS, binary code which is issued by the processor 2, or intermediate frequency signals SRNS GPS. Digital mixers 3 and 4 provide the selection signals given letters SRNS GLONASS or satellite signals SRNS GPS and transfer spectra of these signals in the baseband frequency to the zero frequency). With the digital outputs of the mixers 3 and 4, the signals on the signal input units 6 and 7 digital demodulators. On the reference inputs of the blocks 6 and 7 digital demodulators with the first and second outputs of the programmable delay line 10 are received, respectively, an "exact" ("p") and "offset" (d) a copy of the reference C/a code SRNS GLONASS or GPS. Blocks 6 and 7 digital demodulators using part of them digital demodulators 61, 62and 71, 72perform a correlation of the received signals with the "exact" ("p") and "offset" (d) copies of the reference C/a code SRNS GLONASS or GPS. The programmable delay line 10 operates on the signals from the output of the generator 13 reference code that generates the reference pseudo-random C/a codes of the satellites SRNS GLONASS or GPS. Required for operation of the generator 13, the clock signal frequency of 1.023 MHz for GPS or 0,511 MHz for GLONASS served on its signal input from the output of the digital controlled oscillator 12 of the code. The choice of the type produced by a pseudorandom code sequence and values of the clock h is the frequency of the reference code is for processor 2, coming through the bus interchange on the generators 12 and 13. The correlation results are accumulated in the cumulative blocks 8 and 9 in the respective drives 81, 82and 91, 92namely, the drive 81accumulates the in-phase component correlation exact copy of the signal (Ip), the drive 82accumulates the in-phase component correlation shifted copies of the signal (Id), the drive 91accumulates quadrature component correlation exact copy of the signal (Qp), and the drive 92accumulates quadrature component correlation shifted copies of the signal (Qd). Accumulation period equal to the period of reference C/a code, i.e. a 1 msec.

Accumulated in the accumulators 81, 82, 91, 92data (Ip, Qp, Id, Qd) periodically read by the CPU 2, in which you implement the necessary algorithms and signal processing is the formation of the necessary control commands and data to locate and track the signal.

At the beginning of the search process, the CPU 2 on the basis of a priori uncertainty of the temporary provisions of the desired signal sets the initial position of the search, i.e. sets the carrier frequency for the digital controlled oscillator 5 by the carrier, the frequency code for the digital controlled oscillator 12 of the code and the position of the "exact" ("p") and "offset" (d) copies of the reference C/a code CF IS WITH GLONASS or GPS with case 10 management and sets the threshold values for the detector signal 14.

Accumulated in the accumulators 81, 82, 91, 92at intervals of 1 MS, the results of the correlation processing Ip, Qp, Id, Qd arrive at the signal inputs of the detector signal 14, which performs detection of a strong signal at the first stage search using their hardware. This is done by comparing modules /Ip/, /Qp/Ad/, /Qd/ and sums of modules /Ip/+/Qp/ and /Id/+/Qd/ with predetermined thresholds. If the comparisons identified the threshold is exceeded, then a decision is made about the detection signal at the given position search. Following is the confirmation procedure, at the end of which the decision on termination or continuation of the procedure search. If after processing all positions of the search signal is not found, the search process proceeds to the second stage of the search signal is implemented by means of software processor 2 without the participation of the hardware of the detector signal 14.

The search signal in the second stage is carried out at the same positions as on the first stage. The CPU 2 generates the starting point of the search, i.e. sets the carrier frequency for the digital controlled oscillator 5 by the carrier, the frequency code for the digital controlled oscillator 12 of the code and the position of the "exact" ("p") and "offset" (d) copies of the reference C/a code With the NA GLONASS or GPS using the control register 10. Then, after 1 MS from the start of accumulation, the CPU 2 reads the information from all drives cumulative blocks 8 and 9. Then it moves on to the second and subsequent positions of the search. After passing through all positions of the search processor 2 processes the results of the savings, using design algorithms, and decides on the presence or absence of the signal at these positions.

Thus in a digital correlator prototype implements a two-stage search procedure signal - the first step is finding a strong signal by using the hardware of the detector signal 14 that implements the function of a simple modular detector, and the second stage (in the case of a negative result in the first stage) is the standard source detection software processor 2.

In ideal conditions when working with strong signals the use of such a digital correlator gives the signal receiver GPSr win, in comparison with analogues [1]-[6], to reduce the detection time of the signal and reduce the load on the processor. In real terms when working with the usual (weak) signals the use of such a digital correlator leads to an increase in time spent on the search of the signal due to the unnecessary loss of time spent on the implementation of b is spolecznego in this case the first stage, without any reduction in the load on the processor.

The task, which is aimed by the invention is the creation of a digital correlator receiver signals GPSr, in which the problem of detecting the signal, regardless of its level is hardware that allows you to actually offload the CPU and use the freed resources for additional tasks.

The invention consists in the following. The digital correlator of the receiver signals GPSr provides switch signals GPSr, signal inputs which form the signal input of the digital correlator, the first and second blocks of digital demodulators, each of which contains a group of digital demodulators, the outputs of which form the group of outputs of the corresponding unit of the digital demodulators reference inputs form the group of the reference inputs of the corresponding unit of the digital demodulator, and connected between a signal input - signal input of the corresponding unit of the digital demodulators, the first and second digital mixers, signal inputs are connected to output switch signals GPSr, and the outputs from the signal inputs of the respective blocks of the digital demodulators, the first and second cumulative blocks, each of which contains a group drives the clock inputs to the which form the clock input of the corresponding cumulative block, the outputs form the group of outputs of the corresponding cumulative block, and the signal inputs - group signal inputs corresponding cumulative unit associated with a group of outputs of the corresponding unit of the digital demodulators, the detector signal, the first and second group of the signal inputs of which are connected with the groups of outputs, respectively, of the first and second cumulative units, digital controlled generator carrier, the first and second outputs of which are connected with the control inputs, respectively, of the first and second digital mixers, programmable delay line, the outputs of which are connected with the groups of the reference inputs of the first and second blocks of digital demodulators generator reference code, the output of which is connected with the signal input of the programmable delay line, a digital controlled code generator, the output of which is connected with the signal generator input reference code, the control register, the outputs of which are connected with control inputs of the programmable delay line, the switch signals GPSr and generator reference code, and a processor, connected via bus communication with digital controlled code generator, the generator of the reference code, a control register, a digital controlled oscillator carrier, cumulative blocks and detector signal. When this clock inputs of NAC is itelnych blocks, programmable delay line, a digital controlled oscillator carrier and digital controlled code generator are connected with a clock input of the digital correlator. Unlike the prototype, the detector signal is made in the form of a quadrature detector that implements the algorithm for calculating five points shestnadtsatietazhnogo discrete Fourier transform with extra zeros on the interval of one era C/a code with the subsequent calculation modules conversion results and their incoherent summation and comparison with a variable threshold value which is set depending on the noise power and the number of incoherent reference, and has associated with the processor through the bus communication controller, the clock input of which is connected with a clock input digital correlator, and a command output from the command generator input reference code, a multiplexer, a control input which is connected with the appropriate control the output of the controller, and the first and second groups of signal inputs, forming a first and a second group of the signal inputs of the detector signal associated with the groups of outputs of the respective cumulative units, integrated mixer, the first and second signal inputs of which are connected with the corresponding outputs of the multiplexer and the reference inputs with the corresponding oporn the mi output controller, the unit of coherent summation of the first and second signal inputs of which are connected with the corresponding outputs of the complex mixer, and control input from the relevant control the output of the controller, the power calculation module, the first and second signal inputs of which are connected with the corresponding outputs of the unit of coherent summation, and control input from the relevant control the output of the controller block incoherent summation signal input of which is connected with the output of the computing unit module, and a control input from the relevant control the output of the controller, the unit estimates the noise power in the signal input of which is connected with the output of the computing unit module, information input is connected with the first output block incoherent summation, the control input associated with the appropriate control the output of the controller, and the output is connected via the bus communication with the processor, the evaluation unit signal, the signal input of which is connected with the second output unit incoherent summation, the output is connected with the signal input of the controller, the control input associated with the appropriate control the output of the controller, and the information inputs are connected via the bus communication with the processor, as well as the definition block of the frequency-time coordinates of the global maximum, first, the information is hydrated input of which is connected with the first output unit incoherent summation, the second information input is connected with the output of the evaluation unit signal, a control input connected with the corresponding control the output of the controller, and the output is connected via the bus communication with the processor.

In an embodiment of practical value, group drives, and digital demodulators in each of the cumulative blocks and blocks of digital demodulators are composed, respectively, of the drives and digital demodulators, where K=16.

The essence of the invention and the possibility of its industrial use are illustrated by the drawings and explanatory material presented on figure 1-6, where

figure 1 shows the generalized block diagram of a digital correlator receiver signals GPSr adopted as a prototype;

figure 2 is a generalized block diagram of the inventive digital correlator receiver signals GPSr;

figure 3 is a generalized block diagram of the evaluation unit sound power;

figure 4 is a generalized block diagram of the evaluation unit of signal presence;

figure 5 - graphical representation of the set of coefficients used in the discrete Fourier transform;

figure 6 - matrix of coefficients used in the discrete Fourier transform.

The inventive digital correlator receiver signals GPSr (hereinafter digital correlator) contains, see figure 2, commutator signals GPSr, the processor 2, the first 3 and second 4 digital mixers, related, respectively, to the in-phase and quadrature channels of processing, the digital controlled oscillator 5 by the carrier, the first 6 and second 7 blocks of digital demodulators, related, respectively, to the in-phase and quadrature channels of processing, the first 8 and second 9 cumulative units related, respectively, to the in-phase and quadrature channels of processing, the programmable delay line 10, case 11 management, digital controlled code generator 12 generator 13 reference code and the detector signal 14.

Unit 6 digital demodulator contains a group of digital demodulators 61÷6Kblock 7 digital demodulator contains a group of digital demodulators 71÷7Kcumulative unit 8 contains a group of drives 81÷8Kand cumulative block 9 contains a group of drives 91÷9Kwhere K=16.

Signal inputs digital demodulators 61÷6Kare interconnected and form a signal input unit 6 digital demodulator, the digital outputs of the demodulators 61÷6Kform a group of outputs of unit 6 digital demodulators and the reference input of the digital demodulator 61÷6Kform a group of the support unit 6 digital demodulators. The signal is further inputs digital demodulators 7 1÷7Kare interconnected and form a signal input unit 7 of the digital demodulator, the digital outputs of the demodulators 71÷7Kform a group of outputs of unit 7 of the digital demodulator and reference inputs digital demodulators 71÷7Kform a group of the support unit 7 digital demodulators.

The outputs of the drives 81÷8Kform a group of outputs cumulative unit 8, the signal inputs of the drives 81÷8Kform a group signal inputs cumulative unit 8, and connected between a clock input drives 81÷8Kform a clock input cumulative unit 8. The outputs of the accumulators 91÷9Kform a group of outputs cumulative unit 9, the signal inputs drives 91÷9Kform a group signal inputs cumulative unit 9, and is connected between a clock input drives 91÷9Kform reference input cumulative unit 9.

The signal inputs of the switch 1 of the SRNS signals to form a signal input of the digital correlator.

Signal inputs digital mixers 3 and 4 are connected to output switch 1 signal GPSr, and their reference inputs connected, respectively, with the first and second outputs of the digital controlled oscillator 5 by the carrier.

Signal input the digital demodulators 6 and 7 are connected, accordingly, with the digital outputs of the mixers 3 and 4, and group their outputs connected, respectively, with groups of inputs cumulative blocks 8 and 9.

Group outputs cumulative units 8 and 9 are connected with the first and second groups of signal inputs of the detector signals 14, and via the bus data exchange with the CPU 2.

The output of the digital controlled oscillator 12 code associated with the signal generator input 13 of the reference code, the output of which is connected with the signal input of the programmable delay line 10.

The outputs of the controllable delay line 10 are connected with support groups of input units 6 and 7 digital demodulators. The control input of the programmable delay line 10 is connected with the first output of the register 11 of the control, the second output of which is connected with control inputs of switch 1 signal GPSr and generator 13 reference code.

Digital controlled oscillator 5 by the carrier, the case 11 management, digital controlled code generator 12 generator 13 reference code and the detector signal 14 are connected via the bus communication with the processor 2.

Clock inputs of the digital controlled oscillator 5 by the carrier, cumulative units 8 and 9, the programmable delay line 10, the digital controlled code generator 12 and the detector signal 14 is connected with a clock input digital correlator.

The detector signal 14 is the form of quadrature detector, implements the algorithm for calculating five points shestnadtsatietazhnogo discrete Fourier transform with extra zeros on the interval of one era C/a code with the subsequent calculation modules conversion results and their incoherent summation and comparison with a variable threshold value which is set depending on the noise power and the number of incoherent reference.

The detector signal 14 contains a controller 15, a multiplexer 16, a complex mixer 17, block 18 coherent summation block 19 calculation module, block 20 non-coherent summation unit 21 estimates the noise power, the unit 22 estimates the signal and the block 23 determine the frequency-time coordinates of the global maximum.

The controller 15 is connected via the bus data exchange with the CPU 2; clock input of the controller 15, which forms the clock input of the detector signal 14, is connected to a clock input of the digital correlator; the command output of the controller 15 is connected with the command generator input 13 of the reference code.

The first and the second group of the signal inputs of the multiplexer 16, forming a first and a second group of the signal inputs of the detector signal associated with the groups of outputs of the cumulative units 8 and 9. The control input of multiplexer 16 is connected with the corresponding control the output controller 15.

The first and second signals is s inputs integrated mixer 17 are connected with the corresponding outputs of the multiplexer 16, and the reference inputs with the corresponding reference output controller 15.

The first and second signal input unit 18 of the coherent summation connected with the corresponding outputs of the complex mixer 17, and the control input with the appropriate control the output controller 15.

The first and second signal inputs of the block 19 calculation module connected with the corresponding outputs of block 18 of the coherent summation, and control input from the relevant control the output controller 15.

Signal input unit 20 incoherent summation connected with the output unit 19 calculation module, and a control input from the relevant control the output controller 15.

Signal input unit 21 estimates the noise power associated with the output unit 19 calculation module, the information input is connected with the first output unit 20 incoherent summation, the control input associated with the appropriate control the output of the controller 15, and the output is connected via the bus communication with the processor 2.

Signal input unit 22 estimates the signal associated with the second output unit 20 incoherent summation, the output is connected with the signal input of the controller 15, the control input associated with the appropriate control the output of the controller 15, and the information inputs are connected via the bus communication with the processor 2.

The first information which include the input unit 23 to determine the frequency-time coordinates of the global maximum is associated with the first output unit 20 incoherent summation, the second information input is connected with the output of block 22 evaluation of the presence signal, the control input associated with the appropriate control the output of the controller 15, and the output is connected via the bus communication with the processor 2.

In this example, the unit 21 estimates the noise power includes (3) unit 24 registers, consisting of registers 241÷24J(J=5), the combined signal inputs of which are connected with the output of the adder 25, and outputs associated with the respective signal inputs of the multiplexer 26 and the corresponding summing inputs of the block 27 subtraction, subtractive inputs of which are connected to the outputs of adders 281÷28J. The inputs of the adders 281÷28Jform information input unit 21 estimates the noise power associated with the first output unit 20 incoherent summation. The first input of the adder 25 forms the signal input unit 21 estimates the noise power associated with the output unit 19 calculation module. The second input of the adder 25 is connected with the output of the multiplexer 26. Control inputs of the multiplexer 26 and registers 241÷24Jform control input unit 21 estimates the noise power associated with the appropriate control the output controller 15. The outputs of block 27 subtracting form the output unit 21 estimates the noise power, which is connected through a bus communication processor 2

In this example, the block 22 evaluation signal contains (figure 4) unit 29 of the comparison, the output register 30, block 31 formation threshold, the block 32 initial threshold value and the unit 33 increments the threshold. The input of the output register 30 is connected with the output unit 29 comparison. The output of the output register 30 forms the output of block 22 evaluation of the presence signal associated with the signal input of the controller 15 and the second information input unit 23 to determine the frequency-time coordinates of the global maximum. Signal input unit 29 comparison forms the signal input unit 22 estimates the presence of a signal associated with a second output unit 20 incoherent summation. The reference input unit 29 comparison connected with the output of block 31 of formation threshold, the first information input of which is connected with the output of block 32 initial threshold value and the second information input is connected with the output unit 33 increments the threshold. The block 31 of the formation of the threshold consists of registers 341÷34j(J=5), the combined signal inputs of which are connected with the output of the adder 35, and the outputs are connected to respective signal inputs of the multiplexer 36, the output of which forms the output of block 31 forming a threshold associated with the first input of the adder 35 and the reference input unit 29 comparison. Inputs set the initial values of the registers 341÷34Jabout atout first information input unit 31 of formation threshold, associated with the output of block 32 initial value of the threshold. The second input of the adder 35 forms a second information input unit 31 forming a threshold associated with the output unit 33 increments the threshold. Block 32 initial value of the threshold consists of registers 371÷37Jcombined signal inputs of which form of information input unit 32 initial threshold value, and outputs associated with the respective signal inputs of multiplexer 38, the output of which is connected with the first information input unit 31 of formation threshold. Unit 33 increments the threshold consists of the registers 391÷39Jcombined signal inputs of which form of information input unit 33 increments the threshold, and outputs associated with the respective signal inputs of the multiplexer 40, the output of which is connected with the second information input unit 31 of formation threshold. An information input unit 32 initial threshold value and unit 33 increments the threshold form information input unit 22 estimates the signal connected via the bus communication with the processor 2. The control inputs of the registers 341÷34J, 371÷37J, 391÷39Jand multiplexers 36, 38, 40 comprise the control unit 22 estimates the signal associated with the appropriate control the output controller 15.

p> Digital correlator has two basic modes of operation - search mode signal and tracking signal. The search mode signal is characterized by two stages, the first of which is the estimation of noise power, and the second is the actual search signal with a variable threshold value which is set depending on the result of the evaluation of noise power, and non incoherent reference (non n millisecond epoch C/a code). The main features of the implementation of both phases of the search mode signal are discussed below in the description of work units 21 evaluation of noise power, and 22 evaluation of signal presence.

In General the digital correlator is described as follows. The inputs of the switch 1 signal GPSr go fetch valid signals SRNS GLONASS and GPS generated by the analog-digital Converter unit of the radio-frequency conversion of the signal receiver GPSr (figures not shown). In accordance with the command of the processor 2, issued in register 11 control switch 1 signal GPSr connects to its output signals of one of the SRNS - GLONASS or GPS. The signals selected GPSr arrive at the signal inputs of the digital mixers 3 and 4, the reference inputs are received quadrature signals ("SIN" and "COS") reference frequency from the corresponding digital control of the renewable generator 5 of the carrier. Digital controlled oscillator 5 carrier provides the formation of a quadrature intermediate frequency signals of a given character SRNS GLONASS, binary code which is issued by the processor 2, or intermediate frequency signals SRNS GPS. Digital mixers 3 and 4 provide the selection signals given letters SRNS GLONASS or satellite signals SRNS GPS and transfer spectra of these signals in the baseband frequency to the zero frequency). With the digital outputs of the mixers 3 and 4, the signals on the signal input units 6 and 7 digital demodulators, i.e. on the signal inputs of the digital demodulator 61÷6Kand 71÷7K. Group reference input units 6 and 7 digital demodulators educated reference inputs digital demodulators 61÷6Kand 71÷7Kwith a group of outputs of the programmable delay line 10 receive copies of the reference code (C/a code SRNS GLONASS or GPS), offset relative to each other by a specified time delay equal to half the duration of the symbol C/a code. Blocks 6 and 7 digital demodulators using part of them digital demodulators 61÷6Kand 71÷7Kare correlated in-phase and quadrature components of the processed signals with the specified copies To the reference code. Copies of the reference code which is sought on the basis of the signals, coming from the output of the generator 13 reference code that generates the reference pseudo-random C/a codes of the satellites SRNS GLONASS or GPS. Required for operation of the generator 13, the clock signal frequency of 1.023 MHz for GPS or 0,511 MHz for GLONASS served on its signal input from the output of the digital controlled oscillator 12 of the code. The choice of the type produced by a pseudorandom code sequence and the values of the clock frequency of the reference code is for processor 2 is supplied via the bus interchange on the generators 12 and 13. The correlation results are accumulated in the cumulative blocks 8 and 9 in the respective drives 81÷8Kand 91÷9Kat intervals of integration equal in the search mode signal 1/8 era C/a code (i.e. 1/8 MS)and in the tracking mode for the signal duration of the epoch of C/a code (i.e. 1 MS).

Accumulated in the accumulators 81÷8Kand 91÷9Kdata (K-phase and K quadrature component correlation) are fed to the first and second group of the signal inputs of the detector signal 14, as well as through the bus interchange in the processor 2, in which you implement the necessary algorithms and signal processing is the formation of the necessary control commands and data used to implement the search (detection) signal and the subsequent tracking of the signal is om.

In the search process of the signal processor 2, based on the a priori uncertainty of time-frequency position of the desired signal, sequentially sets the position of the search for the carrier frequency and the delay code and outputs to the controller 15, the search range for the delay (the number of temporary positions in which to look for the signal) and the interval incoherent processing, defined by a given number N millisecond epochs. The installation positions of the search is carried out by setting the current frequency for the digital controlled oscillator 5 carrier frequency code for the digital controlled oscillator 12 of the code and the provisional regulations of copies of the reference C/a code SRNS GLONASS or GPS with the help of the register 11 of the control generator 13 reference code and the programmable delay line 10. On the installed positions of the search is carried out in the above correlation processing with the formation of the cumulative outputs of blocks 8 and 9 pairs of quadrature signals I(i, k) and Q(i, k), where i is the number of intervals within the era of the C/a code (i=1...8); k is the channel number correlation processing defined by the number of the digital demodulator in groups 61÷6Kand 71÷7K(k=1...16).

Frequency 0,125 MS (8 kHz) of the quadrature signals I(i, k) and Q(i, k) are, respectively, the first and second groups of signal inputs on the of neurites signal 14, i.e. the first and the second group of the signal inputs of the multiplexer 16. Under the action of a control signal from the controller 15, the multiplexer 16 in turn passes on the outputs of the pair of quadrature signals related to the same channel number "k" progressively from the first channel number (k=1) to the last (k=16). On the basis of the total number of channels K=16, the frequency of the output signals of the multiplexer 16 is 128 kHz.

From the outputs of the multiplexer 16 these pair of quadrature signals at the first and second signal inputs of the integrated mixer 17, the reference input of which receives signals Re(V(j, i)) and Im(V(j, i))defined by the matrix [V] of coefficients of the discrete Fourier transform. Integrated mixer 17 converts the I and q signals by multiplying their values by the values of the Fourier coefficients. Each pair of I and q samples from each of the K channels of the correlation processing on the i-th interval is multiplied by a column vector of the matrix [V]corresponding to this interval. The results of this multiplication is then summed in block 18 of the coherent summation, forming the resulting signals implemented the discrete Fourier transform for five frequency bins j ("bin" - element discretization) on the interval one (n-th) age C/a code (1 MS). The operation unit 18 to arentnode summation occurs under the action of control signals, coming from the controller 15.

In order to reduce hardware costs and reduce energy losses it is proposed to use a variant of the discrete Fourier transform, which is the truncation of the standard 16-point algorithm the discrete Fourier transform with leading zeros (see [8] - Labiner, Bgold. Theory and application of digital signal processing. M., Mir, 1978, s, 426), which can be obtained from the original signal I(i, k) and Q(i, k) results for five frequency bins based on 2-bit set of Fourier coefficients. This algorithm differs from the standard 16-point algorithm with leading zeros only used by the set of Fourier coefficients [V0÷V7]shown in figure 5, and the matrix of Fourier coefficients [V], is shown in Fig.6.

The results of the discrete Fourier transform - output signals of block 18 of the coherent summation of I(k, j, n) and Q(k, j, n), where n is the number of millisecond epoch C/a code (n=1...255) - arrive at the inputs of the block 19 calculation module that performs the function module definition ρ(k, j, n) quadrature signals I(k, j, n) and Q(k, j, n).

Unit 19 the calculation module generates at its output the signals ρ(k, j, n), determine the current values of modules for each n-th millisecond epoch C/a code for each of the j-th frequency Bina and each of the k-th channel. In order to reduce and paratory cost unit 19 calculation module invited to perform as a unit, implements approximation algorithm determination module ρ(k, j, n) quadrature signals I(k, j, n) and Q(k, j, n)that do not require operations to extract the square root of the sum of squared terms, and providing the calculation error is not more than 4%: ρ=I-I/16+I/64+I/128+Q/4+Q/8+Q/64+Q/128 (for I>Q) (algorithm Poncelet).

From the output unit 19 calculation module signals ρ(k, j, n) are fed to the signal inputs of the block 20 non-coherent summation unit 21 estimates the noise power.

Work unit 20 incoherent summation and the type of signals generated at the first and second outputs depend on the ongoing phase - evaluation phase power noise or phase search signal.

During the assessment phase of the noise power in the preceding stage of the search signal, at each new frequency position specified by the write of the new value of the carrier frequency in the digital controlled oscillator 5 of the bearing block 20 non-coherent summation generates at its first output signals Ek, j, Nrepresenting the maximum value of modules for each of the k-th channel and each j-th frequency Bina on the time interval defined by a given number N millisecond epochs. These signals when carrying out procedures for the assessment of noise power received at the end of the last (nth) cycle non-coherent accumulation on the information input unit 21 estimates the noise power, the signal is hydrated input of which receives signals ρ (k, j, n) from the output unit 19 in the module definition.

The following by-stage evaluation of noise power stage signal search unit 20 incoherent summation generates at its second output signalsrepresenting a running total of the summation modules ρ(k, j, n) n-m millisecond cycles during non-coherent accumulation, defined by a given number N millisecond epochs. These signals in the implementation procedures of search and detection of the useful signal received at the signal input unit 22 estimates the presence of a signal, to the information input of which receives calculated by the CPU 2 according to the results of the estimation of noise power, the initial values of the thresholds of P0(j) and the values of their increments ΔP(j).

The main features of the evaluation phase of the sound power is determined by the operation unit 21 estimates the noise power (figure 3) and are as follows.

The information input unit 21 estimates the noise power at the stage of estimation of noise power from the first output unit 20 non-coherent summation at the end of the last (nth) cycle non-coherent accumulation of the received signals Ek, j, Nrepresenting, as stated above, the maximum value of modules for each of the k-th channel and each j-th frequency Bina on the time interval defined by a given number N millisecond epochs. These signals are amounts which are in the block 21 evaluation of noise power in the adders 28 1÷28Jfor all k channels for each of the j-th frequency bin. The results of the summationcome on subtractive inputs of block 27 of the subtraction.

On the signal input unit 21 estimates the noise power, i.e. at the first input of the adder 25, signals ρ(k, j, n), representing, as indicated above, the current values of modules for each n-th millisecond epoch C/a code for each of the j-th frequency Bina and the k-th channel. These signals are summed and accumulated in the registers 241÷24Jin accordance with its frequency bins in the interval defined by a given number N millisecond epochs. The summation is carried out through periodic connection of the outputs of the respective registers 241÷24Jthrough the multiplexer 26 to the second input of the adder 25. The accumulated results of summationi.e. the total sum of modules ρ(k, j, n) for a given j-th frequency Bina, for all k=16 channels and all n=N millisecond epochs, at the end of the last (nth) cycle incoherent accumulation arrive at the summing unit 27 subtraction, subtractive inputs of which the outputs of the adders 281÷28Jdo the results discussed above summation maximum values of modules for all k=16 channels

Block 27 subtraction generates for each frequency Bina results of estimation of the noise power Pjin view of the differences of Pj=S(j)-Z(j). The signals that determine the results of the evaluation of noise power, the output unit 21 estimates the noise power via the bus interchange go on processor 2.

Based on the results of the estimation of noise power, the CPU 2 calculates the initial values of the detection thresholds and their increments. These data are in the form of information signals P0(j) and ΔP(j) in the early stage of the search signal received in block 22 evaluation of signal presence.

The main features of the phase of the search and detection of the useful signal is determined by the operation unit 22 estimates the presence of the signal (figure 4). Unit 22 implements a truncated sequential coding detection signal. This procedure lies in the fact that the incoming signal on the input unit 22 signalsrepresenting, as indicated above, increasing the total summation modules ρ(k, j, n) n-m millisecond cycles during non-coherent accumulation, defined by a given number N, for each value of n are compared with increasing thresholdformed in the block 22 based on the input data P0(j) and ΔP(j), and the results of the comparison produces an output signal, attesting to get the angling or absence of the useful signal. If at some value n value E(k, j, n) for all channels k and the frequency bin j is below the threshold, then a decision is made about the absence of the useful signal at a given frequency-time positions. If at least one frequency bin j of one of the channels k value E(k, j, n) is above the threshold, then the process is non-coherent accumulation continues until n=N, when recording the signal in that frequency bin of the channel, in which the value of E(k, j, n)≥P(j, N). This comparison is carried out using a block 29 of the comparison, and storing the signal carrying the information about the detection or absence of a useful signal in each frequency bin of each channel by using the output of the register 30.

The formation of this increasing thresholdis carried out as follows. The initial values of the thresholds of P0(j) for each j-th frequency Bina written to the appropriate registers 371÷37Jblock 32 initial threshold value, and increment value thresholds ΔP0(j) in the corresponding registers 391÷39Junit 33 increments the threshold. The initial threshold value selected by the multiplexer 38 for each of the j-th frequency Bina, alternately served on the first information input unit 31 of the formation of the threshold, where it is written to the appropriate registers 34 1÷34J. Increment value thresholds selected by the multiplexer 40 for each j-th frequency Bina, alternately served on the second information input unit 31 of the formation of the threshold, i.e. to the second input of the adder 35. At the first input of the adder 35 from the output of the multiplexer 36 in turn receives the current values of the thresholds stored in the registers 341÷34J. In the adder 35 is the gain increment to the current threshold value, then a new threshold value is written to the appropriate register 341÷34J. The current values of the increasing threshold, defined asserved on the reference input unit 29 of the summation signal input is received, as indicated above, the signalsCoordinated operation of the blocks 31, 32 and 33 on the formation of increasing thresholds is provided with control signals received from controller 15 to the control input unit 22, i.e. on the control inputs of the registers 341÷34J, 371÷37J, 391÷39Jand multiplexers 36, 38, 40.

If a positive search result is generated at the output of block 22, the detection signal is transmitted to the signal input of the controller 15, which stops the search process. Thus in the output register 30 are fixed non chaston the th and temporary positions, where the detected signal, and to block 20 non-coherent summation for each channel and each frequency positions are saved results incoherent summation modules. This data is supplied to the information input unit 23 to determine the frequency-time coordinates of the global maximum, which produces information signals on time-frequency position of this maximum. This is done by pairwise comparison of the results of the non-coherent accumulation for those frequency bins (j) and channels (k), where the detected signal, and the information which is transmitted to the second information input unit 23 to determine the frequency-time coordinates global maximum output of the unit 22 estimates the presence of the signal (i.e. the output register 30). Information signals generated by the block 23 determine the frequency-time coordinates of the global maximum, together with the error signal generated by the controller 15, is transmitted to the CPU 2 to transfer digital correlator in the tracking mode for the detected signal.

If the useful signal is not detected, then the control unit 22 estimates the signal transmits to the controller 15 a sign of lack of signal at a given k×j frequency-time positions. In this case, the controller 15 sends the generator 13 reference code command on the ass is Riku reference code K temporary positions, reduces per unit specified at the beginning of the search mode, the search range for the delay results in the initial state all the blocks of the detector signal 14 and starts searching for a signal on the same frequency position, installed in the digital controlled oscillator 5 by the carrier (on the same five frequency bins), but on the new K temporary positions. If the signal is not detected in all the specified search range for the delay, the controller 15 outputs to the CPU 2 a sign of lack of signal and stops the operation of the detector signal 14 to receive from the processor 2 of the new task.

Thus considered, it follows that the claimed invention is technically feasible and solves the task of creating a digital correlator receiver signals GPSr, in which the problem of detecting signal (regardless of level) is hardware that allows you to actually offload the CPU and use the freed resources for additional tasks. However through the use of a large number of frequency-time positions, which is the search defined by the product of J×K, where J=5, K=16, and by providing opportunities to assess the noise level, providing data for the calculation of the thresholds in the processor, speed of search and detection signals compared the th prototype and analogues.

1. Digital correlator receiver of signals of satellite navigation systems (SNS), which contains the switch signals GPSr, signal inputs which form the signal input of the digital correlator, the first and second blocks of digital demodulators, each of which contains a group of digital demodulators, the outputs of which form the group of outputs of the corresponding unit of the digital demodulators reference inputs form the group of the reference inputs of the corresponding unit of the digital demodulator, and connected between a signal input - signal input of the corresponding unit of the digital demodulators, the first and second digital mixers, signal inputs are connected to output switch signals GPSr, and the outputs from the signal inputs of the respective blocks of the digital demodulators, the first and second cumulative blocks, each of which contains a group drives the clock inputs of which form the clock input of the corresponding cumulative block, the outputs form the group of outputs of the corresponding cumulative block, and the signal inputs - group signal inputs corresponding cumulative unit associated with a group of outputs of the corresponding unit of the digital demodulators, the detector signal, the first and second group of the signal inputs of which are connected with the groups of outputs relevant to the military first and second cumulative blocks, digital controlled oscillator carrier, the first and second outputs of which are connected with the control inputs respectively of the first and second digital mixers, programmable delay line, the outputs of which are connected with the groups of the reference inputs of the first and second blocks of digital demodulators generator reference code, the output of which is connected with the signal input of the programmable delay line, a digital controlled code generator, the output of which is connected with the signal generator input reference code, the control register, the outputs of which are connected with control inputs of the programmable delay line, the switch signals GPSr and generator reference code, and a processor, connected via bus communication with digital managed code generator, the generator of the reference code, a control register, a digital controlled oscillator carrier, cumulative units and the detector signal, while the clock inputs of cumulative blocks, programmable delay lines, digital controlled generator carrier and digital controlled code generator are connected with a clock input digital correlator, wherein the detector signal is made in the form of a quadrature detector that implements the algorithm for calculating five points shestnadtsatietazhnogo discrete Fourier transform with additional and zeros on the interval of one era C/a code with the subsequent calculation modules conversion results and their incoherent summation and comparison with a variable threshold, the value which is set depending on the noise power and the number of incoherent reference, and has associated with the processor through the bus communication controller, the clock input of which is connected with a clock input digital correlator, and a command output from the command generator input reference code, a multiplexer, a control input which is connected with the corresponding control the output of the controller, and the first and second groups of signal inputs, forming a first and a second group of the signal inputs of the detector signal associated with the groups of outputs of the respective cumulative units, integrated mixer, the first and second signal inputs of which are connected with the corresponding outputs of the multiplexer and reference inputs - with the corresponding reference outputs of the controller, the unit of coherent summation of the first and second signal inputs of which are connected with the corresponding outputs of the complex mixer, and control input from the relevant control the output of the controller, the power calculation module, the first and second signal inputs of which are connected with the corresponding outputs of the unit of coherent summation, and control input from the relevant control the output of the controller block incoherent summation signal input of which is connected with the output of the computing unit module, and rawsome input - with the appropriate control the output of the controller, the unit estimates the noise power in the signal input of which is connected with the output of the computing unit module, information input is connected with the first output unit incoherent summation, the control input associated with the appropriate control the output of the controller, and the output is connected via the bus communication with the processor, the evaluation unit signal, the signal input of which is connected with the second output unit incoherent summation, the output is connected with the signal input of the controller, the control input associated with the appropriate control the output of the controller, and the information inputs are connected via the bus communication with the processor, as well as the definition block of the frequency-time coordinate global maximum, the first information input of which is connected with the first output unit incoherent summation, the second information input is connected with the output of the evaluation unit signal, a control input connected with the corresponding control the output of the controller, and the output is connected via the bus communication with the processor.

2. Digital correlator according to claim 1, characterized in that groups of drives and digital demodulators in each of the cumulative blocks and blocks of digital demodulators are composed To drives and digital demodulators, where K=16.



 

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6 cl, 12 dwg

FIELD: satellite radio navigation, geodesy, communication, applicable for independent instantaneous determination by users of the values of location co-ordinates, velocity vector components of the antenna phase centers of the user equipment, angular orientation in space and bearing.

SUBSTANCE: the method differs from the known one by the fact that the navigational information on the position of the antenna phase centers of ground radio beacons, information for introduction of frequency and time corrections are recorded in storages of the user navigational equipment at its manufacture, that the navigational equipment installed on satellites receives navigational radio signals from two and more ground radio beacons, and the user navigational equipment receives retransmitted signals from two satellites.

EFFECT: high precision of navigational determinations is determined by the use of phase measurements of the range increments according to the carrier frequencies of radio signals retransmitted by satellites.

3 dwg, 1 tbl

FIELD: the invention refers to navigational technique and may be used at designing complex navigational systems.

SUBSTANCE: an integrated satellite inertial-navigational system has a radioset connected through an amplifier with an antenna whose outputs are connected to a computer of the position of navigational satellites and whose inputs are connected with the block of initial installation of the almanac of data about satellites' orbits. The outputs of this computer are connected with the inputs of the block of separation of radio transmitting satellites. The outputs of this block are connected with the first group of inputs of the block of separation of a working constellation of satellites whose outputs are connected with inputs of the block of computation of a user's position. The system has also a meter of projections of absolute angle speed and a meter of projections of the vector of seeming acceleration which are correspondingly connected through a corrector of an angle speed and a corrector of seeming acceleration with the first group of inputs of the computer of navigational parameters whose outputs are connected with the first group of the outputs of the system. The system also includes a computer of initial data which is connected with three groups of inputs correspondingly to the outputs of the meter of projections of absolute angle speed and the meter of projections of a vector of seeming acceleration and to the outputs of a block of integration of information and also to the outputs of the block of computation of a user's position. At that part of the outputs of the computer of initial data are connected to the inputs of the computer of navigational parameters and all outputs are connected to the first group of the inputs of the block of integration of information whose second group of inputs is connected with the outputs of the corrector of an angle speed and the corrector of seeming acceleration, and the third group of inputs is connected to the outputs of the block of computation of a user's position. One group of the outputs of the block of integration of information is connected to the second group of the inputs of the block of selection of a working constellation of satellites, the other group of the outputs are directly connected to the second group of the outputs of the system, the third group of the outputs are connected to the inputs of the corrector of seeming acceleration and the fourth group of the outputs are connected with the inputs of the corrector of an angle speed and the second group of the inputs of the computer of initial data.

EFFECT: increases autonomous of the system, expands composition of forming signals, increases accuracy.

4 dwg

FIELD: railway transport.

SUBSTANCE: proposed repair team warning device contains "n" navigational satellites, dispatcher station consisting of receiving antenna, satellite signals receiver, computing unit to determine corrections to radio navigational parameter for signals from each navigational satellite, modulator, transmitter, transmitting antenna and computer of standard values of radio navigational parameters, movable object installed on locomotive and consisting of satellite signals receiving antenna, satellite signals receiver, computing unit for determining location of movable object, first receiving antenna, first receiver, first demodulator, matching unit, modulator, transmitter, transmitting antenna, second receiving antenna, second receiver and second demodulator, and warming device consisting of receiving antenna, receiver, demodulator, computing unit for determining distance between movable object, warning device, modulator, transmitter, transmitting antenna, satellite signals receiving antenna, satellite signals receiver and control unit.

EFFECT: improved safety of track maintenance and repair teams in wide zone of operation.

6 dwg

FIELD: radio engineering, applicable in receivers of signals of satellite radio navigational systems.

SUBSTANCE: the micromodule has a group of elements of the channel of the first frequency conversion signals, group of elements of the first channel of the second frequency conversion of signals, group of elements of signal condition of clock and heterodyne frequencies and a group of elements of the second channel of the second frequency conversion signals.

EFFECT: produced returned micromodule, providing simultaneous conversion of signals of standard accuracy of two systems within frequency ranges.

4 dwg

FIELD: aeronautical engineering; determination of aircraft-to-aircraft distance.

SUBSTANCE: aircraft-to-aircraft distance is determined by the following formula: where position of first of first aircraft is defined by azimuth α1, slant range d1, altitude h1 and position of second aircraft is determined by azimuth α2, slant range d2 and altitude h2. Proposed device includes aircraft azimuth indicators (1,4), flying altitude indicators (2,5), indicator of slant range to aircraft (3,6), adders (7, 14, 15, 19), multiplication units (8-12, 16, 18), cosine calculation unit 913), square root calculation units (17-20) and indicator (21).

EFFECT: avoidance of collision of aircraft; enhanced safety of flight due to determination of true aircraft-to-aircraft distance with altitude taken into account.

2 dwg

FIELD: the invention refers to radio technique means of determination of a direction, location, measuring of distance and speed with using of spaced antennas and measuring of a phase shift or time lag of taking from them signals.

SUBSTANCE: the proposed mode of determination of coordinates of an unknown transmitter is based on the transmitter's emitting of a tracing signal to the satellite, on receiving of signals of an unknown transmitter and legimite transmitters which coordinates are known, on forming a file of clusters, on selection of the best clusters out of which virtual bases are formed for calculating coordinates of legimite and unknown transmitters according to the coordinates of legimite transmitters and the results of calculation of their coordinates one can calculate mistakes of measuring which are taken into account at calculating the coordinates of the unknown transmitter.

EFFECT: increases accuracy of determination of coordinates of an unknown transmitter in the system of a satellite communication with a relay station on a geostationary satellite.

2 dwg, 1 tbl

The invention relates to receivers, which provide a measure of the information of the location of the satellites and are used in the detection system (GPS)location

FIELD: the invention refers to radio technique means of determination of a direction, location, measuring of distance and speed with using of spaced antennas and measuring of a phase shift or time lag of taking from them signals.

SUBSTANCE: the proposed mode of determination of coordinates of an unknown transmitter is based on the transmitter's emitting of a tracing signal to the satellite, on receiving of signals of an unknown transmitter and legimite transmitters which coordinates are known, on forming a file of clusters, on selection of the best clusters out of which virtual bases are formed for calculating coordinates of legimite and unknown transmitters according to the coordinates of legimite transmitters and the results of calculation of their coordinates one can calculate mistakes of measuring which are taken into account at calculating the coordinates of the unknown transmitter.

EFFECT: increases accuracy of determination of coordinates of an unknown transmitter in the system of a satellite communication with a relay station on a geostationary satellite.

2 dwg, 1 tbl

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