Computing machine and a block for processing oncoming requests

FIELD: computer engineering, in particular, electronic computing machines.

SUBSTANCE: the device contains a processor, local address-data multiplexing bus, memorizing device, modernized system controller consisting of a system controller and a block for processing oncoming requests.

EFFECT: prevented hang-up of processors in case of coincidence of oncoming requests from processors, connected to external PCI bus.

2 cl, 1 dwg

 

The invention relates to the electronics industry, in particular to electronic computing machines.

Known electronic computing device, including a processor, a local multiplex bus address data storage device (memory) and system controller (SC), SC provides communication processor, a memory and an external PCI bus [1].

Exchange standard signal processor and IC ensures execution of write and read data on the local bus address data in the address field of the memory, and in the address field of an external recipient via the PCI bus in accordance with the Protocol specified in [1]. The conversion processor is terminated upon receipt by the processor of the destination signal Ask (and/or formed at the same time signal RdCEn).

When applying an external recipient to the memory via the PCI bus, the system controller generates a request signal to the processor Bus Req, if the processor is busy local bus address data communication Protocol via the PCI bus provides the waiting for the end of the execution of the SC conversion processor local bus and re-survey of an exemption to the processor local bus address data, what processor informs the delivery of the signal Bus Gnt. However, the timeout signal Bus Req is not removed, and performing the conversion processor to an external recipient via the PCI bus is not possible.

In this case, the AE, if you experience signal interrupt request from another processor via the PCI bus IC refers to the processor a signal Bus Req, however, if the processor is put your request on appeal, that is, the active signal Rd or Wr, ALE, A/D, the processor ignores the presence of a signal Bus Req, waiting for a signal processing his conversion - Ack. The Protocol conversion on the PCI bus provides the expectation of resolution conversion on a signal Bus Req in the appearance of the signal Bus Gnt and regular repeat survey of the presence of this signal, without taking with treatment to them. The company may at intervals of repeated surveys Bus Gnt to hold the address of the processor to the memory, then the processor will release the bus and generates the signal Bus Gnt, but when handling the processor to an external recipient IC is not able to interrupt the wait signal Bus Gnt and to process requests from external recipient

There is a situation hangs, insoluble in the exchange of standard signals.

Task patentable invention is to prevent freezing of the processors when the coincidence counter requests from the processors connected to the external PCI bus.

The technical result consists in the generation of additional signals is a sign decode addresses the treatment of external recipient to the memory and the sign of decode address conversion processor to an external destination through the external PCI bus.

the defined task and the technical result is achieved electronic computing machine, including the processor, the local multiplex bus address data storage device (memory) and system controller (SC), while it is equipped with a processing unit of counter-requests (BOWS) with eight inputs and five outputs, forming with the system controller modernized system controller (MSC)that connects the processor with the memory and providing communication between the processor and the memory with the external PCI bus, and the first output-output processor connected to the specified bus address data to the first input-output memory to the first input of the IC, with the first input BOWS, with the first output BOWS, the second output signal of the write address conversion processor (ALE) is connected with the second input of the IC, the third output signal of the read mode of the processor (Rd) connected to the third input of the read mode of the IC and a second input BOWS, the fourth output signal of the recording mode of the processor (Wr) is connected with the third input BOWS, the fifth output of the confirmation signal transmission control local bus from the processor to the system controller (Bus Gnt) is connected with the fourth input BOWS, the first output of the SC signal characteristic decode address conversion processor to an external recipient via the PCI bus connected to the fifth input BOWS, the second output SC signal characteristic decode treatment external recipient via the PCI bus to the memory connected to the sixth input BOWS, the third output IC request signal from the external ADR is Satan to take control of the local Bus Req) is connected to the seventh input BOWS, the fourth output SC of the confirmation signal of the true data on the processor bus (Ack) is connected to the eighth input BOWS, the second output BOWS connected to the fourth input of the confirmation signal transmission control system controller SC (Bus Gnt), the third output BOWS connected to the first input signal confirm the true data on the processor bus (Ack), the fourth output BOWS connected to the fifth input of the signal recording mode SC (Wr), the external PCI bus is connected to the sixth input of the IC, the fifth output BOWS connected with the second input of the processor request signal to the processor to take control of the system Bus Req), the fifth output IC signals address bus is connected to the second input of the address memory, the sixth output IC signal recording mode-read connected with the third input signal mode write-read memory.

The specified task and the technical result is achieved that the processing unit counter requests (BOWS) includes a first circuit And a second circuit And a third circuit And a delay circuit-shaper, the register, the fourth circuit And the switch, the first circuit OR the fifth circuit And the sixth circuit And the inverter, a second circuit OR the third circuit OR the fourth circuit OR the fifth circuit OR, and the fifth input BOWS connected to the first input of the first circuit And the output of the first circuit And connected to the first input of the second circuit And the output the second circuit And connect the n to the first input of the third circuit And to the first input of the sixth circuit And, the output of the third circuit And is connected to the input of delay circuit-shaper, the output of the delay circuit is a driver connected to the first input register signal recording in the register information from the second input register and to the first input of the fifth circuit OR the first input BOWS connected with the second input register, the output data register connected to the first input of the switch, the output signal of the write register connected to the first input of the fourth circuit And the first input of the third circuit OR the output of the fourth circuit And is connected with the second input of the switch and to the first input of the second circuit OR the output data of the switch is connected to the first output BOWS the third input BOWS connected to the first input of the first circuit OR the second input of the third circuit And the second input of the second circuit OR the sixth input BOWS connected to the first input of the fifth circuit And the output of the first circuit OR is connected to a second input of the fifth circuit And the output of the fifth circuit And is connected to a second input of the second circuit And the second input BOWS connected to a second input of the first circuit OR the second input of the sixth circuit And the output of the sixth circuit And connected to the first input of the fourth circuit OR the seventh sign BOWS connected to a second input of the first circuit And, with the input of the inverter and to the second input of the third circuit OR the output of the third circuit OR connected to the fifth output BOWS, the inverter output is connected to a second input of the fourth scheme is s And the output of the fourth circuit OR is connected with the second output BOWS, the eighth input BOWS connected to the third input register and a second input of the fifth circuit OR the output of the fifth circuit OR connected with the third output BOWS, the fourth input BOWS connected to a second input of the fourth circuit OR the output of the second circuit OR connected to the fourth output BOWS.

The processing unit counter query is a functional node MSC and provides the resolution specified the conflicts that arise when the coincidence in time of a collision of requests from a processor connected to the PCI bus.

The drawing shows a block diagram of patentable computer.

Electronic computing machine (computer) includes a processor 1, a local multiplex bus address data 2, a storage device (memory) 3 and modernized system controller (MSC) 4, providing communication between the processor 1, a memory 3 and the external PCI bus 5. Upgraded system controller consists of a system controller (SC) 6 and the processing unit counter requests (BOWS 7 with eight inputs and five outputs.

The first input-output 8 processor 1 is connected to the specified bus address data 2 with the first entrance-exit 9 of the law 3, with the first input 10 SC 6, with the first input 11 BOWS 7 and to the first output 12 BOWS 7. The second output 13 of the recording signal of the address conversion processor 1 (ALE) is connected with the second input 14 of the IC 6. The third output 15 from the drove of read (Rd) processor 1 is connected with the third input 16 of the IC 6 and the second input 17 BOWS 7. The fourth output 18 of the signal recording mode (Wr) processor 1 is connected with the third input 19 BOWS 7. The fifth output 20 of the confirmation signal transmission control local bus 2 from the CPU 1 to the system controller 6 (Bus Gnt) is connected with the fourth input 21 BOWS 7. The first outlet 22 of the IC 6 signal characteristic decode address conversion processor 1 to an external recipient via the PCI bus 5 is connected to the fifth input 23 BOWS 7. The second output 24 SC 6 signal characteristic decode treatment external recipient via the PCI bus 5 to the memory 2 is connected to the sixth input 25 BOWS 7. The third output 26 SA 6 request signal from an external recipient to take control of the local Bus Req) is connected to the seventh input 27 BOWS 7. The fourth output 28 SC 6 confirmation signal of the true data on the processor bus 1 (Ack) is connected to the eighth input 29 BOWS 7. The second output 34 BOWS 7 is connected with the fourth input 35 SC 6 confirmation signal transmission control system controller IC 6 (Bus Gnt). The third exit 32 BOWS 7 connected to the first input 33 of the processor 1 of the confirmation signal of the true data on the processor bus 1 (Ack). The fourth output 30 BOWS 7 is connected to the fifth input 31 SC 6 signal recording mode (Wr) IC 6. External PCI bus 5 is connected to the sixth input 36 of the IC 6. The fifth output 37 BOWS 7 is connected to a second input 38 of the processor 1 request signal to the processor to take control of the system Bus Req). The fifth output 39 of the IC 6 is Ignatov address bus is connected to a second input 40 of the address accessing the memory 3. The sixth output 41 SC 6 signal recording mode-reader is connected to the third input 42 recording mode-read SO.

The processing unit counter query includes in its composition the first scheme And 43, a second circuit And 44, the third circuit 45, a delay circuit-shaper 46, the register 47, the fourth circuit 48, switch 49, the first scheme OR 50, the fifth circuit 51, the sixth circuit 52, an inverter 53, the second scheme OR 54, the third circuit OR 55, the fourth circuit OR 56 and the fifth circuit 57.

The fifth input 23 BOWS 7 connected to the first input 58 of the first circuit And 43, the output 59 of the first circuit And 43 connected to the first input 60 of the second circuit And 44, the output 61 of the second circuit And 44 connected to the first input 62 of the third circuit 45 and to the first input of 63 sixth circuit 52, the output 64 of the third circuit 45 is connected to the input 65 of the delay circuit-shaper 46, the output 66 of the delay circuit of the driver 46 is connected to the first input 67 of the register 47 of the recording signal in the register 47 information from the second input 69 of the register 47 and the first input 68 of the fifth circuit 57, the first input 11 BOWS 7 is connected with the second input 69 of the register 47, the output data register 70 47 connected to the first input 71 of the switch 49, the output of the recording signal 72 of the register 47 is connected to the first input 73 of the fourth circuit And 48 and the first input 74 of the third circuit OR 55, the output 75 of the fourth circuit 48 is connected to a second input 76 of the switch 49 and to the first input 77 of the second circuit OR 54, the output data 78 to the of mutator 49 is connected to the first output 12 BOWS 7, the third entrance 19 BOWS 7 connected to the first input 79 of the first circuit OR 50, with the second input 80 of the third circuit 45 and to the second input 81 of the second circuit OR 54, the sixth input 25 BOWS 7 connected to the first input 82 of the fifth circuit 51, the output 83 of the first circuit 50 is connected to a second input 84 of the fifth circuit 51, the output 85 of the fifth circuit 51 is connected to a second input 86 of the second circuit And 44, the second input 17 BOWS 7 is connected with the second input 87 of the first circuit OR 50 and a second input 88 of the sixth schemes And 52, the output 89 of the sixth circuit And 52 connected to the first input 90 of the fourth circuit OR 56, the seventh input 27 BOWS 7 is connected with the second input 91 of the first circuit And 43, to the input 92 of the inverter 53 and the second input 93 of the third circuit OR 55, the output 94 of the third circuit OR 55 is connected to the fifth output 37 BOWS 7, the output 95 of the inverter 53 is connected to a second input 96 of the fourth circuit 48, the output 97 of the fourth circuit 56 is connected with the second output 34 BOWS 7, the eighth input 29 BOWS 7 is connected with the third input 98 of the register 47 and a second input 99 of the fifth circuit 57, the output 100 of the fifth circuit 57 is connected with the third output 32 BOWS 7, the fourth input 21 BOWS 7 is connected to a second input 101 of the fourth circuit 56, the output 102 of the second circuit OR 54 is connected to the fourth output 30 BOWS.

In the presence of signal Wr or Rd on the inputs 79 or 87, respectively, via a scheme OR 50 from the output 83 of the first circuit OR 50 to the input 84 of the fifth circuit 51 receives a permit passage submit the ka decode addresses the treatment of external recipient to the memory from the second outlet 24 of the IC 6 and the first input 82 of the fifth circuit 51 through the scheme And 51 to the output 85 of the scheme And 51 and to the second input 86 of the second circuit And 44. At the request of the CPU 1 to an external destination on the PCI bus 5 from the first output 22 of the IC 6 to the first input 58 of the first circuit And 43 enters the sign of decode address conversion processor 1 to an external recipient via the PCI bus 5. If available, the request from the external recipient with the third output 26 SA 6 signal Bus Req is supplied to the second input 91 of the first circuit And 43 and gives permission for the passage characteristic decode address conversion processor to an external recipient via the PCI bus 5 from the first output 22 of the IC 6 and the first input 58 of the first circuit And 43 through the first circuit And 43 on the output 59 of the first circuit And 43 and the first input 60 of the second circuit And 44. If the inputs 86 and 60 of the second circuit And 44 simultaneously signals a collision queries on the output 61 of the second circuit 44, a signal is generated in the presence of conflicts of counter-requests. This signal is applied to the first inputs 62 and 63 of the third and sixth circuits And 45 and 52, respectively, the second inputs 80 and 88 which, respectively, receive signals Wr and Rd, respectively. The outputs 64 and 89 of the third and sixth circuits And 45 and 52, respectively, are formed signals the presence of conflict in the write mode and the read processor 1, respectively.

If there is a conflict in the reading mode bus 2 is free, and the output 89 of the sixth circuit And 52 formed signal the presence of conflict, which is supplied to the first input 90 of the fourth circuit OR 56 and through schemes is OR 56 from the output 97 to the input 35 of the IC 6 receives signal simulation Bus Gnt, in the presence of this signal SC 6 performs a standard Protocol for the treatment of external recipient to the law of Ukraine on free bus 2, which ends with the removal of the signal Bus Req output 26 of the IC 6 and the input 91 of the first circuit And 43 and the output 59 of the first circuit And 43 and the input 60 of the second circuit And removes the signal characteristic decode address conversion processor to an external recipient via the PCI bus 5, therefore, the output 61 of the second circuit And 44 and the inlet 63 of the sixth circuit And 52 is removed signal conflict situation, the output 89 of the sixth circuit and 52 And the inlet 90 the fourth circuit OR 56 is removed, the signal of the conflict situation in the reading mode. This leads to the removal of the simulate signal Bus Gnt at the output 97 of the fourth circuit OR 56 and the input 35 of the IC 6. The conflict is solved and SC 6 standard Protocol performs a conversion processor to an external destination. The trip ends with the formation of the signal ASC, which from the output 28 of the IC 6 is supplied to the second input 99 of the fifth circuit 57 and through the scheme And 57 with its output 100 is fed to the input 33 of the CPU 1. The processor after completion of the scan cycle removes the signal Rd. Thus, both counter-request satisfied.

In write mode, the CPU 1 at its second output 13 generates a signal write address conversion at the input 14 of the IC 6 and through the span of time Then set multiplexed mode local bus 2, put the bus 2 information to an external recipient. The output 64 of the third circuit 45, a signal is generated conflict when writing, which is fed to the input 65 of the delay circuit-shaper 46, which over time at the output 66 of the delay circuit-shaper 46 is formed with simulated signal ASC. Input 67 scheme register 47 this signal will write data bus 2 and the entrance of 69 scheme of the register 47 in the register 47 and the output 70 of the register 47 will set the stored information to an external recipient, and the output 72 will be recording signal to an external destination. Output 66 of the delay circuit-shaper 46 simulation signal ACK arrives, also, to the input 68 of the fifth circuit 57 and through the circuit 57 with its output 100 simulated signal ASC is supplied to the first input 33 of the CPU 1, in which the processor has finished recording mode, remove the signal Wr and release the bus 2. The conflict is cleared when saving signal Bus Req output 26 of the IC 6 and the inlet 93 of the third circuit OR 55, through which the scheme OR 55 with its output 94 is supplied to the second input 38 of the signal Bus Req processor 1. Output 26 SA 6 signal Bus Req is supplied also to the input 92 of the inverter 53, and through an inverter 53 to its exit 95 to the input 96 of the fourth circuit 48 receives the prohibition of the passage of the recording signal from the output 72 of the register 47 through the scheme And 48 at its output 75 and to the input 76 of the switch 49, the output of which in this situation is in the third state and hinder the bus 2. Processor after Windows is project record mode after removing the conflict in standard mode on a continuing request signal Bus Req issues at its fifth output 20 response signal Bus Gnt, which goes to the input 101 of the fourth circuit OR 56 and through the scheme, OR 56 with its output 97 is fed to the input 35 of the IC 6, then SC 6 standard Protocol will address external recipient to the memory, which will end with the removal of the signal Bus Req output 26 of the IC 6 and the input 93 of the third circuit OR 55. However, the presence of the recording signal from the output 72 of the register 47 at the input 74 of the third circuit OR 55 holds its output 94 to a second input 38 of the processor 1, the signal Bus Req, which does not allow the processor to remove the signal Bus Gnt and take the bus 2. When removing the signal Bus Req output 26 of the IC 6 and, consequently, with the entrance 92 of the inverter 53 at the output 95 of the inverter 53 and the inlet 96 of the fourth circuit And 48 receive the permission signal signal recording through the scheme And 48 with its output 75 is fed to the input 76 of the switch 49 and opens the switch 49. Previously recorded in the register 47 information processor 1 from the output 70 of the register 47 is fed to the input 71 of the switch 49 and through the open switch 49 with its output 78 to the bus 2, and the output 75 of the fourth circuit And 48 to the input 77 of the second circuit OR 54 and through the scheme, OR 54 with its output 102 to the input 31 of the IC 6 is supplied imitation of the recording signal. The internal address register IC 6 has not received a new signal write address input 14 and stores a previously recorded address of the external recipient via the PCI bus. SC 6 simulated signal recording Wr performs a standard Protocol write data when ihoda switch 49 via the bus 2 through the saved address of the external recipient on the PCI bus. The trip ends with the issuance of the signal ACK from the output 28 of the IC 6, which is fed to the input 98 of the register 47 and resets the register in the initial state, the recording signal is removed from output 72 and 48 and through its exit 75 at the input 76 of the switch 49 turns off the switch 49, converting the output to the third state and freeing the bus 2, and the input 77 of the second circuit OR 54 through the scheme, OR 54 with its output 102 at the input 31 of the IC 6 is removed from the recording signal Wr, the removal of the recording signal from the output 72 of the register 47 leads to the removal of the simulate signal Bus Req from input 74 of the third circuit OR 55, with its output 94 and the second input 38 of the processor 1. The processor then removes the signal Bus Gnt output 20. Both counter-request satisfied.

If there is no conflict of counter-requests no conflict signal at the output 61 of the second circuit And 44, the signals of the conflicts in record mode and read the outputs 64 and 89, respectively, in the initial state is the register 47 is closed the switch, standard protocols exchanges through schemes OR 54, 55, 56 and 57 of the signals Wr, Bus Req, Bus Gnt and ASC, respectively.

Literature

1. Betulin V.B. have been, Bobkov YEAR, Dubrovsky, A.G., Sagebin S.O., Krynicki AV, Novozhilov E.A., Osipenko P.N., Romaniuk YEAR, Cardin O.V. Element base hardware and software platform "Baguette", volume 1, Moscow, niece Russian Academy of Sciences, 2004, ISBN 5-93838-017-0 Volume 1.

1. E will calculate the supplemented flax machine, including the processor, the local multiplex bus address data storage device (memory) and system controller (SC), wherein it is equipped with a processing unit of counter-requests (BOWS) with eight inputs and five outputs, forming together with the system controller modernized system controller (MSC)that connects the processor with the memory and providing communication between the processor and the memory with the external PCI bus, and the first input-output processor connected to the specified bus address data to the first input-output memory to the first input of the IC, with the first input BOWS, with the first output BOWS, the second output signal of the write address conversion processor (ALE) is connected with the second input of the IC, the third output signal of the read (Rd) connected to the third input of the read mode of the IC and a second input BOWS, the fourth signal output mode write (Wr) processor connected to the third input of the signal recording mode BOWS, the fifth output of the confirmation signal transmission control local bus from the processor to the system controller (Bus Gnt) is connected with the fourth input BOWS, the first output of the SC signal characteristic decode address conversion processor to an external recipient via the PCI bus connected to the fifth entrance BOWS, the second output IC signal characteristic decode treatment external recipient via the PCI bus to the memory connected to the sixth input BOWS, the third output SK si is Nala request from the external recipient to take control of the local Bus Req) is connected to the seventh input BOWS, the fourth output SC of the confirmation signal of the true data on the processor bus (Ack) is connected to the eighth input BOWS, the second output BOWS connected with the fourth input ck of the confirmation signal transmission control system controller (Bus Gnt), the third output BOWS connected to the first input of the signal processor confirm the true data on the processor bus (Ack), the fourth output BOWS connected to the fifth input of the SC signal recording mode (Wr), the external PCI bus is connected to the sixth input of the IC, the fifth output BOWS connected with the second input of the processor request signal to the processor to take control of the system Bus Req), the fifth output IC signals address bus is connected with the second input addresses to access the memory, the sixth output IC signals mode write-read memory connected to the third input mode write-read memory.

2. The processing unit counter requests, including in its composition a first circuit And a second circuit And a third circuit And a delay circuit-shaper, the register, the fourth circuit And the switch, the first circuit OR the fifth circuit And the sixth circuit And the inverter, a second circuit OR the third circuit OR the fourth circuit OR the fifth circuit OR, and the fifth input BOWS connected to the first input of the first circuit And the output of the first circuit And connected to the first input of the second circuit And the output of the second circuit And connected to the first input of the third circuit And with the first I is the home of the sixth circuit And, the output of the third circuit And is connected to the input of delay circuit-shaper, the output of the delay circuit is a driver connected to the first input register signal recording in the register information from the second input register and to the first input of the fifth circuit OR the first input BOWS connected with the second input register, the output data register connected to the first input of the switch, the output signal of the write register connected to the first input of the fourth circuit And the first input of the third circuit OR the output of the fourth circuit And is connected with the second input of the switch and to the first input of the second circuit OR the output data of the switch is connected to the first output BOWS the third input BOWS connected to the first input of the first circuit OR the second input of the third circuit And the second input of the second circuit OR the sixth input BOWS connected to the first input of the fifth circuit And the output of the first circuit OR is connected to a second input of the fifth circuit And the output of the fifth circuit And is connected to a second input of the second circuit And the second input BOWS connected to a second input of the first circuit OR the second input of the sixth circuit And the output of the sixth circuit And connected to the first input of the fourth circuit OR the seventh sign BOWS connected to a second input of the first circuit And, with the input of the inverter and to the second input of the third circuit OR the output of the third circuit OR connected to the fifth output BOWS, the inverter output is connected to a second input of the fourth scheme is s And the output of the fourth circuit OR is connected with the second output BOWS, the eighth input BOWS connected to the third input register and a second input of the fifth circuit OR the output of the fifth circuit OR connected with the third output BOWS, the fourth input BOWS connected to a second input of the fourth circuit OR the output of the second circuit OR connected to the fourth output BOWS.



 

Same patents:

FIELD: method for processing applications for usage in computing device, in particular, providing resources of device allocated for one application.

SUBSTANCE: in accordance to the invention, wireless device comprises wireless interface, computer platform, including memory for storage of control software and a set of applications, each one of which contains a list of privileges and a set of device resources. System for permitting access to device resource comprises wireless interface, computer platform, including a set of device resources, processing means, containing device for receiving access request for certain resource from an application, and means for evaluating a list of privileges. Access of application to device resources is provided on basis of privileges, associated with an application. A list of privileges is created by server, which defines resources which may be accessed by the application. During execution of the application, when application requests a resource, control program uses a list of privileges, associated with the application, to determine whether the application may access the resource.

EFFECT: increased flexibility of resource control.

2 cl, 5 dwg

FIELD: system and method for dynamically configuring port of network equipment (20) for communications in broadband network (10).

SUBSTANCE: in accordance to the invention, database (26) of central control data, connected to server (24) of dynamic host configuration protocol, supports templates with records of network equipment parameters for settings of its physical port (21) and provided services. As a result, it is possible to dynamically update port settings by transferring parameter records from server (24) of dynamic host configuration protocol. Parameter settings are updated in intermediate device (20).

EFFECT: identification of user and configuration template, correction of configuration template and application of configuration.

2 cl, 2 tbl, 1 dwg

FIELD: methods for reproducing content information in device for interactive optical disk and for providing content information on the server of information provider.

SUBSTANCE: the reproduction method includes synchronization and reproduction of data read from interactive optical disk, and content information, dispatched and loaded from information provider server, connected via Internet, generation of command for requesting repeated send of content information, if content send from information provider server is stopped or delayed, dispatching of the command and reproduction of content information, repeatedly sent from information provider server together with data read from interactive optical disk, during its repeated synchronization with data read from interactive optical disk.

EFFECT: expanded functional capabilities.

5 cl, 6 dwg

FIELD: specialized computer devices, possible use in digital systems for controlling and processing signals.

SUBSTANCE: device contains measurement result storage block, block for setting number of thresholds, block for creating thresholds, discriminator blocks, penalty value storage blocks, detection interval setting block, blocks for finding non-stationary intervals of penalty values, zeroing blocks, addition block, threshold block, discriminator block, storage block, clock impulse generator.

EFFECT: detection of abnormal measurements under conditions of insufficient a prior information about statistical characteristics of additive noise, with single present realization of process being researched.

2 cl, 1 dwg

FIELD: three-level virtual VPN networks.

SUBSTANCE: VPN includes provider routers and end provider routers in main network P, in user VPN networks a set of sites are included as well as user end routers and hierarchical device (HoPE), which includes low level end router (UPE) and high level end router (SPE). In accordance to method, between UPE and SPE several end routers of medium level are positioned (MPE), which are used for supporting all routes in VPN, for replacing mark connected to default routes (VRF), and for creating an UPE route.

EFFECT: creation of expandable three-level VPN network, satisfying requirements of limitations of required resources and minimized configuration.

2 cl, 5 dwg

FIELD: system and method for realizing private message exchange, pertaining to information about presence of object, presence of which it is required to detect.

SUBSTANCE: in accordance to invention, during realization of communication between presence servers and terminals, connected to presence servers via a network, at least one object is identified, presence of which is determined, relatively to which terminal requested presence services. Presence document is created, while presence document includes presence information, corresponding to object, presence of which is determined. Information about presence is generated as private presence information, containing less than full presence information, available for object, presence of which is detected.

EFFECT: creation of more efficient and comfortable method for submitting presence information.

7 cl, 9 dwg

Personal computer // 2300139

FIELD: computer engineering, possible use for manufacturing personal computers.

SUBSTANCE: device contains first radio-transmitting device, positioned in system block, first radio-receiving device, positioned in the body of digital monitor, second radio-transmitting device, positioned on the body of keyboard, second radio-receiving device, positioned on system block.

EFFECT: increased interference resistance of radio-technical devices - input devices and monitor of personal computer.

15 dwg

FIELD: second level local computing networks.

SUBSTANCE: in accordance to invention, method includes stages, at which commutating device sends message about registration order, including address of identifier of commutating device, control device sends response message about successful registration to commutating device, which after receiving that message sends communication setup message to control device, which after receiving that message sends response message about communication setup to commutating device, which after receiving that message sets up communication with controlling device, which realizes control over commutating device during communication setup, while commutating device determines, whether communication setup process exceeds predetermined time.

EFFECT: provision of integrated control and support of network commutating devices, and also saving of resources of IP-addresses of network.

7 cl, 2 dwg

FIELD: office equipment, in particular, system and method for correction of image during output to printing device.

SUBSTANCE: computer, with printing device connected to it, is equipped with information carrier, containing file with image, agent module, data storage module, at least one application, graphic device interface and printing device interface. Agent module is made with possible finding of new file with image on data carrier, aforementioned file containing additional information, calculations for this file of numeric index based on image data and recording of computed index together with additional file information to data storage module. Printing device driver is made with possible calculation of numeric index on basis of additional information data received in it, appropriate to calculated numeric index, and correction of image data received by it and transfer of corrected image data to printing device.

EFFECT: possible correction of image in accordance to additional information during output to printing device from various applications, installed on computer.

2 cl, 1 dwg

FIELD: cell communication systems.

SUBSTANCE: invention includes system and method for facilitating access via mobile terminal to certain network application, accessible through multiple application servers in the network. Application identifier, corresponding to network application, and connected parameters of application access, including address of server of applications of one of a set of application servers, are inserted into provision information. Provision information is transferred at least to one mobile terminal, connected to provision procedure. Mobile terminal is outfitted to facilitate access to network application through applications server, identified by application server address, provided with provision information.

EFFECT: expanded functional capabilities for mobile terminal access to applications, only accessible through application servers in network.

5 cl, 7 dwg

FIELD: midget phones or electronic secretaries.

SUBSTANCE: proposed system enables user to pack, transfer, or save dynamic or static information such as video, audio, and scribal information from video display for other user through Internet. Upon receiving information package user can browse all pieces of information contained in mentioned package without addressing various application programs.

EFFECT: facilitated data exchange and message compilation, provision for preventing virus infection through e-mail.

27 cl, 8 dwg

FIELD: systems and method for software control of access between one or more nodes and multiple devices connected thereto.

SUBSTANCE: system has system of parallel used memorizing devices and node, programmed for identification of each memorizing device and masking access from node to at least one memorizing device. System for controlling access to multiple memorizing devices in system of memorizing devices has node, programmed for determining, whether for each of multiple memorizing devices masking should be performed relatively to node and interface for selective modification of programmed data structure. Method describes operation of system for controlling access to multiple parallel use memorizing devices by multiple computers.

EFFECT: possible concurrent transfer of frames in both directions at speed, exceeding 1 Gbit per second, for distance over 10 km.

6 cl, 13 dwg

The invention relates to systems for the transmission of data lines shared tire using a variety of interfaces

The invention relates to computing and information exchange in computer network

The invention relates to a circuit for exchanging signals I / o between the devices to operate in one of multiple modes using a single channel and can be used in electronic measuring Coriolis mass flowmeter

The invention relates to methods of information exchange in computer networks

The invention relates to the field of data transmission in multiplex channels of information exchange and can be used for access control stand-alone terminal to the data bus

The invention relates to computing and is designed for interfacing computers over telephone lines

FIELD: computer engineering, in particular, electronic computing machines.

SUBSTANCE: the device contains a processor, local address-data multiplexing bus, memorizing device, modernized system controller consisting of a system controller and a block for processing oncoming requests.

EFFECT: prevented hang-up of processors in case of coincidence of oncoming requests from processors, connected to external PCI bus.

2 cl, 1 dwg

Up!