Method for manufacturing silicon-on-sapphire mis transistor

FIELD: microelectronics; integrated circuits built around silicon-on-sapphire structures.

SUBSTANCE: proposed method for manufacturing silicon-on-sapphire MIS transistor includes arrangement of silicon layer island on sapphire substrate, formation of transistor channel therein by doping silicon island with material corresponding to channel type, followed by production of gate insulator and gate, as well as source and drain regions; prior to doping silicon island with material corresponding to channel type part of silicon island is masked; mask is removed from part of silicon island of inherent polarity of conductivity upon doping its unmasked portion and producing gate insulator; in addition, part of gate is produced above part of silicon island of inherent polarity of conductivity; source region is produced in part of silicon island of inherent polarity of conductivity and drain region is produced in part of silicon island doped with material corresponding to channel type.

EFFECT: improved output characteristics of short-channel transistor at relatively great size of gate.

1 cl, 7 dwg

 

The invention relates to the field of microelectronics and can be used in the manufacture of integrated circuits on the basis of structures of silicon on sapphire (SOS), is widely used to create digital, digital-analog and analog-to-digital CMOS LSIS, as well as CMOS LSI high reliability and resistant to radiation effects.

The most common use of the specified element base received in a special electronic equipment for space research, radar, communications and telecommunications, the elimination of the effects of radiation and other environmental disasters, the disposal of nuclear and chemical waste, and special equipment for civilian use.

Known MOS transistor at the CND of ' induced by the channel, in which is formed an additional inversion region, which divides the channel in the surface region into two parts: one between the source and the inversion region, and the other between the inversion region and drain. Thus, the effective channel length is reduced by the length of the inversion region, which allows to obtain korotkokanal transistors. (V.fyodorov overseas - worse" in the section "Commission". Scientific-technical journal "Technology youth", 1998, No. 2, page 42).

The disadvantage of the described structure MOS transistor at the CND is the complexity of the playback IMEI : the conduct of geometrical parameters of locking areas of the channel and, accordingly, the output characteristics of the transistor when the channel size is less than 1.5 μm, what affects the reliability of the device and limits the possibilities of its application in the realization of submicron transistors with a channel length of less than 1.5 microns.

The closest to the technical nature of the present device is a MOS field-effect transistor (MOS-FET) with the induced channel based on the structure of the CND. (U.S. patent No. 4106045, MKI 2 01L 29/78, epubl year).

MOS field-effect transistor (MOS-FET) with the induced channel based on the structure of the SPS contains planar formed in the island silicon layer area of the source and drain of the n+the conductivity type and located between the region of p-type conductivity, which is induced by the channel. To increase performance of the device in the switching mode, the silicon layer near the border with the sapphire substrate between the n+the area of the source and the p-region, which is induced by the channel is created, R+-area. Additional p+-region supports the potential of the substrate is equal to the potential source, thereby prevents the accumulation of holes in the channel region of and excludes the "kink effect".

The disadvantage of the described structure is to use it only for n-channel transistors. This noticeable increase in performance of forming an additional p+-region does not provide as effective channel length of the transistor is not reduced.

Known SPO is about the formation of the MIS - transistor on the structure of the CND. (V.fyodorov overseas - worse" in the section "Commission". Scientific-technical journal "Technology youth", 1998, No. 2, page 42).

In the known method in the generated lithographically Islands of silicon on a sapphire substrate using the masking and ion implantation to form pockets n-type and p-type conductivity. Next, the surface of the silicon Islands of n-type and p-type conductivity is subjected to thermal oxidation for forming the gate dielectric of silicon dioxide. Then, using photolithography mask gate silicon oxide SiO2leaving unprotected area of the silicon oxide in the Central channel region of a transistor, the amount of unprotected area is not more than 1/3 of the channel length of the transistor. And after etching the unprotected gate oxide silicon remove the mask. On the surface of the gate silicon oxide and the Central channel region of a transistor, available from silicon oxide, is applied to the silicon nitride Si3N4while formation of the "built-in" channel or inversion region at the interface of Si-Si3N4and locking regions in the transistor channel at the interface of Si-SiO2-Si3N4. Next, form the gate polysilicon by ion implantation to form the field of art the Cove and origins, and after applying the interlayer isolation and opening contact Windows sprayed the contacts.

Since the establishment of the proposed inversion region provides for the use of different dielectric coatings as a gate dielectric (SiO2and Si3N4or necessary overcompensation dopant in the surface region of the channel by using ion implantation, the implementation of such a method is very time consuming and expensive, and also requires the use of additional photolithographic equipment with a resolution several times better than the baseline production, which is not realistic in the manufacture of transistors with a channel length of less than 1.5 microns.

The closest in technical essence to the proposed method is a method of manufacturing a structure MOS field-effect transistor (MOS-FET) with the induced channel based on the structure of the CND for U.S. patent No. 41006045. (U.S. patent No. 4106045, MKI 2 01L 29/78, epubl year).

In the known method initially on a sapphire substrate (AL2About3form Islands of silicon (Si). Then, for forming the channel of p-type conductivity of the silicon Islands using masking and ion implantation alloyed impurity of p-type conductivity, are subjected to thermal oxidation to form the gate dielectric is silicon oxide and the gate and the polysilicon. Then make the field of sinks and sources. A feature of the manufacture of n-channel transistors is that they spend the formation of an additional p+-region. Additional p+-region is created in the silicon layer near the border with the sapphire substrate between the n+region of the source and the p-region, which is induced by the channel of the transistor. The formation of the p+-region is carried out by bombarding protons relevant field with subsequent annealing at a temperature of 800°-1000°With, simultaneously with the activation of the impurities in stock and stokovyh areas of the transistors, while in areas subjected to proton bombardment, there has been a rapid diffusion of aluminum from the sapphire in the silicon with the formation of the p+-region. Next, after applying the interlayer isolation and opening contact Windows are made of aluminum contacts.

The known method does not solve the main tasks, namely, improve performance, and only allows you to exclude the "kink effect" n-channel transistor.

The disadvantages of this method are:

- the need for inclusion in the technological cycle of complex additional equipment;

- limited use of the method because the method can be implemented only for n-channel transistors.

The present invention relates to the structure of a MOS-transistor at the SPS and method E. the making.

The technical task to be solved by the invention is the creation of a MOS transistor, a channel structure which allows to significantly reduce its effective length while maintaining the dimensions of the bolt and the thickness of the gate dielectric.

The technical result from the use of the invention is:

- significant improvement of the output characteristics of the transistor current (performance gain), while maintaining its reliability by eliminating the possibility of breakdown in the region locking,

- significant increase device reliability in General,

- expansion of the scope of the proposed transistor.

The technical problem is solved by the fact that in the MOS transistor on the structure of silicon on sapphire, containing the formed planar in the island silicon layer on a sapphire substrate region of the source and drain and located between the channel insulated gate, according to the proposed invention, the edge with the inlet part of the channel is made of silicon own type conductivity.

The technical problem is solved in that in the method of manufacturing a MOS transistor structure of silicon on sapphire, including the creation of a sapphire substrate of the island silicon layer of intrinsic conductivity, formation in n the m channel transistor by doping the silicon island admixture, corresponding to the channel type, followed by the creation of gate dielectric and gate, and then the manufacturing areas of the source and drain, according to the proposed invention, before the doping of the silicon island impurity corresponding to the channel type, masking part of the silicon island, and after doping unmasked (open) part of it and to create a gate dielectric and gate, remove the mask part of the island silicon own type conductivity, in addition, the portion of the bolt creates on the part of the island silicon own type conductivity, while the area of the source is made in part of the island silicon own type conductivity, and the drain is made in part of the silicon island doped impurity corresponding to the channel type.

Forming an edge with the source side of the transistor channel of the silicon own type conductivity, then which for brevity may be called "insert", you change the size of the shutter to reduce the effective channel length due to the increased mobility and speed of carriers in the channel with its own type conductivity silicon, while providing high reliability play a locking part of the channel. In addition, the absence of dopant in the "insert" reduces the number of scattering centers nose the residents of charge. The insert also allows you to lower the threshold voltage of the transistor due to the low concentration of charge carriers in the field "insert" and at the same time to increase mobility, which dramatically increases the output characteristics of the current more than 1.5 times with the same size of the channel length of the transistor on the gate. Execution part of the channel of the silicon own type conductivity in the proposed method of manufacturing is provided by a set of operations: masking part of the island silicon own type conductivity, the doping is not masked part of the island silicon with subsequent formation of part of the shutter on the part of the island silicon own type conductivity. Execution part of the channel's own conduction type as an edge with source region is provided by the creation of areas of the source in parts of the island silicon own type conductivity. High reproducibility of the structure of the transistor of the proposed method ensures the reliability of the devices.

In addition, keeping the size of the gate by performing part of the channel of the Si own type conductivity will provide output characteristics korotkokanal transistor at a greater thickness gate dielectric that will allow you to:

to increase the resistance to breakdown from static electricity.

- n is to reduce the supply voltage and thus increase the noise immunity of the transistor.

The technical result from the use of the proposed invention are implementing and ensuring the output characteristics korotkokanal transistor with a relatively big size of the bolt, which allows you to:

- use bóthe greater the thickness of the gate dielectric,

to increase the resistance to breakdown from static electricity

- to maintain the supply voltage,

to improve the noise immunity of the transistor

- to increase output characteristics (gain, performance) more than 1.5 times with the same size of the channel length of the transistor on the gate by increasing the mobility of charge carriers in the channel region of a transistor made of silicon intrinsic conductivity and reducing the effective channel length of the transistor.

To achieve the above technical results in the standard version of the transistor (without "insert" in the channel) it would be necessary to reduce the channel length of the transistor on the gate not less than 1.3 times.

The invention is illustrated in Fig 1-7, where

figure 1 presents the structure of p(n)-channel MOS transistor into a gutter in the incision;

figure 2 shows the step of forming the border between the locking part of the channel and its part with its own conductivity;

figure 3 and figure 4 show stages in the formation of the I gate dielectric and gate;

figure 5 shows the step of forming signalisierung regions of source and drain;

figure 6 shows the step of forming the low-alloy regions of source and drain, and the boundaries induced channel;

figure 7 shows the output voltage characteristics of the known n-channel MOS transistor into a gutter with a channel length of L=1.5 µm (III) and proposed performance n-channel MOS transistor into a gutter when the size of the masked area, part 1/2L channel (I) and 3/4L channel (II), respectively.

MOS transistor at the SPS (figure 1) contains a substrate 1 of sapphire (AL2About3); the island of semiconductor silicon (Si) 2 formed therein signalground areas 3 and 4, low-alloy regions 5 and 6 of the source and drain, respectively. Between areas 5 and 6 of the source and drain region is induced channel 7, which is divided into alloy (locking) part 8 and part with its own (i) conductivity 9. The device comprises a gate dielectric 10, for example of silicon dioxide (SiO2); the bolt 11, for example of doped polysilicon; pads 12, 13, 14 with the conclusions for areas 3, 4 and the source and drain and the channel 7, respectively; an interlayer insulation 15, for example, of a layer of silicon dioxide SiO2and silicon nitride (Si3N4). The length of the channel 7 is determined by the length L of the shutter 11. The length l is Asti with its own conductivity type 9 channel 7 for p - and n-channel MOS transistors should be selected based on the required characteristics of p - and n-channel MOS transistors, depending on the operation modes. For example, in the CMOS circuit, it is desirable to have the same gain. If you use one type of transistor, it is possible to use design with maximum gain.

In figure 2, 3, 4, 5, 6, illustrating the sequence of formation regions of the source, drain and channel of the proposed design MOS transistor shown position on the intermediate stages of its formation: the border between 16 alloy locking part 8 of the induced channel 7 and part of it with its own conductivity 9; mask is formed from a photoresist 17 (figure 2); a layer of silicon oxide (SiO2) 18 to create a gate dielectric 10; the polysilicon layer 19 and the mask 20 of the photoresist for forming the gate 11 (Fig 3, 4); mask 21 of the photoresist for forming signalisierung regions 3 and 4, respectively, the source and drain (figure 5) and low-alloy regions 5 and 6 of the source and drain (6).

The proposed MOS transistor at the SPS with any type of channel works as follows.

In the absence of supply voltage (1) gate 11 channel 7 length L is locked in the main part 8, as for transistors with any type channel part with sobstvennim conductivity type 9 channel 7 has a low threshold voltage. When applying bias to the gate 11 in part 9 of the channel 7 is already Ave the small values of U I(for example, 1) because of the small threshold voltage due to the low concentration of charge carriers in this area there will be a noticeable inversion charge and there is a large amount of carriers of the appropriate type. With further increase of the input voltage on the gate 11 opens the locking part 8 channel 7 and the value of current Ioreaches almost at reduced power (for example, ≤3B) such values, which is known for transistors with channel without the border with the source part of the intrinsic type conductivity) may not always be achieved when UI=5V (see Fig.7). These results are provided due to the increased mobility of carriers in part 9 of the channel 7 and the small number of scattering centers due to the absence of dopant in part 9 of the channel, as well as a significant decrease in effective channel length 7, since the locking area in the channel 7 is only part 8, which increases the performance of the device, which is confirmed by figure 7 the increase in the slope (see output specifications) current-voltage characteristics of n-channel MOS transistors of the proposed design.

Using the proposed design of the p - and n-channel MOS transistors on the CND achieved the following technical advantages.

1. Increases the performance of the device is and by performing an edge to the inlet part of the channel of the silicon intrinsic conductivity by increasing the mobility and speed of carriers, as well as reducing the effective channel length.

2. Increases the gain due to the reduction of scattering centers and the number of collisions of carriers with defects of its own conductivity type.

3. Increases reliability and noise immunity of the devices due to the possibility of use in submicron transistors gate dielectric with a greater thickness of silicon oxide, since the proposed design provides the ability to save high voltage.

4. Increases the efficiency of the proposed device, because it does not require large expenditures on modernization of production facilities to reduce the design requirements and consumers the opportunity to remain the same power supply devices, as reduced supply voltage requires additional costs.

It is established that the gain (Kus) 1.5 for n-channel transistor with a long shutter L=1.5 μm is achieved when the size of l "insert"made of Si own type conductivity in part 9 of the channel 7, is equal to 1/2 (0,75 µm) of the length L of the shutter. For the p-channel transistor gain factor of 1.5 is achieved when the size l of part 9 of the Si own type conductivity equal to 3/4 of the length L of the shutter (≤1 μm). The increased size of the part 9 of the channel 7 for n-channel Tran who istora more than 1/2 to 3/4 of the length L of the shutter 11 leads to an increase in gain to values of 1.8-2. The use of such n-channel transistors is possible schemes, when they do not work in a pair of p-channel transistors, so as not to disrupt the stability of the scheme, therefore, in the case of CMOS circuits, when both are n - and p-channel transistors, n-channel appropriate value l "insert" 9 to limit the size of 1/2L. Size l part 9 channel 7, is equal to 3/4 of the length L of the shutter 11 to p-channel transistor, does not impair the characteristics of the p-channel transistor on the input current consumption and breakdown voltage of stock transfer. In order to obtain the same gain at the n - and p-channel transistors with the same design rule (shutter) due to the different mobility of carriers (holes and electrons) for n-channel transistors masked areas "insert" l should be, for example, 1/2 of the field L and p-channel transistors masked areas "insert" l should be 3/4 of the field L.

A method of manufacturing a MOS transistor structure of silicon on sapphire is shown in specific examples of implementation of the n - and p-channel transistors with a channel length L (proektnym standards shutter) is equal to 1.5 mm.

Example 1. An example implementation of a n-channel transistor.

In the process of forming the channel 7 of the transistor located on the substrate 1 of the Al2O3the island sloa own Si conduction type (i-type) with a thickness of 0.3 μm before the doping of the channel 7 photoresist mask 17 thus, to the exposed part of the island 2 was palagiovani an impurity of p-type conductivity (boron). When this pre-defined inner boundary 16 (2) locking part 8 channel 7. Doping with boron (B) is conducted by ion implantation in 2 modes:

mode 1 - boron implanted at the interface of Al2O3- Si with energy E=150 Kev and a dose of D=0,5 mkcol/cm2;

mode 2 - boron are implanted in the surface region with energy E=40 Kev and a dose of D=0,3 mkcol/cm2.

After removal of the layer 17 of photoresist spend gate oxidation to form a layer of silicon oxide 18 in the thickness 350 Åand for the formation of the shutter 11 are increasing the polysilicon layer 19 with a thickness of 0.4 μm (figure 3) and alloyed its diffusion. Then carried out using photolithography fabrication of the mask 20 (3), so part of her was placed over part of the island silicon own conductivity type for forming a shutter 11, which is located over part of the island Si own type conductivity, and the alloy part of the island. The operation of the alignment pattern after application of the photoresist is carried out, making the binding to the edge of the island 2 or to the border 16. In this example, workmanship, under size mask 1.5 μm was placed above the border 16 overlapping a side of the alloy part of the p-type 0.75 μm (i.e. 1/2 L).

After etching the polysilicon 19 and the Alenia photoresist 20 (Fig,4) create a mask 21 (figure 5) and form signalground region 3 and 4, respectively, the source and drain of the transistor. Region 3 is formed in part of the Si own type conductivity island 2, and area 4 in the alloy part of the Si island 2. To do this, carry out ion implantation of phosphorus (P) with energy E=40 Kev and a dose of D=700 mkcol/cm2(figure 5). Then remove the mask 21 and the re ion implantation of P with energy E=40 Kev and a dose of D=100 mkcol/cm2to create low-alloy regions 5 and 6, respectively, the source and drain with the simultaneous formation of the external borders of the channel 7 (6). Activate the dopant at a temperature T=850°÷900°manufactured interlayer insulation 15 of SiO2and Si3N4thickness of 0.35 μm, and after opening contact Windows in the interlayer insulation 15 is formed of aluminum contacts 12, 13 and 14 to the source, drain and channel 7, respectively.

Example 2. An example implementation of a p-channel transistor.

All the stages of forming a semiconductor structure of the transistor is similar to the steps described in example 1 in the manufacture of n-channel transistor. But at the stage of forming the locking part 8 channel 7 unprotected by the mask 17 part of the island 2 Si alloyed impurity of n-type (phosphorus) using ion implantation which is performed by double-phosphorus. As alloying impurity phosphorus has a large ionic radius, palagiovani the entire thickness of 0.3 μm film 2 Si can t is like with higher energy ions 200÷ 250 Kev. If there is an installation Lada-30" that is provided by double-phosphorus ions with an energy of E=150 Kev and a dose of D=0,1 mkcol/cm2.

The difference in the formation of the mask 20 of length L=1.5 µm in the process of creating the shutter 11 is equal to L - l the amount of overlap of the mask 20 from the border 16 in the part of the island 2, the alloy impurity of n-type conductivity (phosphorus), for p-channel transistor may be at least 1/3L, that is, when L=1.5 μm is not less than 0.5 μm.

For the formation of signalisierung regions 3 and 4 of the source and drain, respectively, as a dopant using boron, and carry out ion implantation with an energy of E=40 Kev and a dose of D=500 mkcol/cm2

Re-implantation of boron to create low-alloy regions 5 and 6, respectively, the source and drain with the simultaneous formation of the external borders of the channel 7 is carried out with energy E=40 Kev and a dose of D=30 mkcol/cm2.

To create p - and n-channel transistors with the same gain is equal to, For example, ausor =1.5, it is necessary for the p-channel transistor size With part 9 of the channel 7 to perform increased.

The above method can be used to create p - and n-channel MOS transistors on the CND short channel and ensures the reproducibility of the proposed structures and does not require special equipment.

A method of manufacturing a MOS transistor structure of silicon on sapphire, including the creation of a sapphire substrate of the island silicon layer of intrinsic conductivity, the formation in it of the channel of the transistor by doping the silicon island impurity corresponding to the channel type, followed by the creation of gate dielectric and gate, and then the manufacturing areas of the source and drain, wherein before the doping of the silicon island impurity corresponding to the channel type, masking part of the silicon island, and after doping unmasked portion, and to create a gate dielectric and gate, remove the mask part of the island silicon own type conductivity, in addition, part shutter creates on the part of the island silicon own type conductivity, while the area of the source is made in part of the island silicon own type conductivity, and the drain is made in part of the silicon island, alloy impurity corresponding to the channel type.



 

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