Device for parallel search and substitution of entrances in processed words

FIELD: informatics; computer technology.

SUBSTANCE: device can be used for soling tasks of composing dictionaries, manual as well as for creation of new databases. Device has entrance memory unit, processed words memory unit, unit for analyzing search, substitution memory unit, substitution unit, result storage unit, control unit.

EFFECT: widened functional abilities; improved reliability of operation; simplified algorithm of operation.

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The invention relates to means for Informatics and computer technology and can be used to create high-speed, specialized and high-performance digital processors, performs the search and replace function in the processing of words.

Known "Information retrieval system" (h-ka RU patent No. 2199778 from 27.02.2003 g)performing a search operation of occurrences of words [9].

Known "Device search random occurrences" (h-ka RU patent No. 2202823 from 20.04.2003 g)defining any entries in the processed words [10].

Known (h-ka RU, "Search device random occurrences" (patent No. 2209465 from 27.07.2003 g)performing a search of random occurrences in the processed words.

As the prototype is set to "Device search and replace arbitrary occurrences in the words of the text" (C-ka RU patent No. 2250493 20.04.2005,) that performs search and replace arbitrary occurrences in the words of the text.

The task consisted of the following:

1) to extend the functionality of the device

2) to improve the performance of search operations,

3) to increase the reliability of the device that performs the search and replace in the processed words.

In the present device the parallel search and replace occurrences in the treated with the peninsulas search operations are performed in parallel using Comparators.

The proposed device will allow you to extend the functionality, to improve the performance of search operations, simplify the algorithm operation.

The solution of the problem is that the device parallel search and replace occurrences in the processing of words that contains a block of memory occurrences, the control unit, characterized in that additionally introduced: the memory block is processed words, the unit of analysis of the search, the memory block replacement block replacement block of storage of the result, and the first to third information output control unit which respectively generates control signals memory device, the addresses of rows and columns of random access memory and data stored in random access memory, connected respectively with the first through third information input of the memory block listings, information the output of which is connected to the first information input unit of analysis of the search, the second information input of which is connected with the information output memory block of the processed words, from the first to the third information input of which is connected respectively with the fourth to sixth information output control unit which respectively generates control signals memory device is istom memory block of the processed words, addresses of rows and columns of random access memory and data stored in the memory device, from the third to the fifth control inputs which are connected respectively with the first through third control outputs of the unit of analysis of search, which are formed signals characterizing respectively the result of the comparison of characters entering and processed words, the mode of the device search occurrences in the processed word without the common parts and the terminator symbols are processed words, from the third to the fifth information unit of analysis search connected respectively with the seventh to ninth informational outputs of the control unit, which generates signals installed in the zero state of the binary counters that control the signal shaping modes register block registers occurrences and processed words, respectively, the first and second control outputs of the control unit, are respectively formed signals characteristic of the operation of the device with the parts and unlocking impulse connected respectively with the first and second control inputs of the unit of analysis of the search, the second information, the output of which is connected to the first information input unit replacement, third and fourth information, the inputs of which are connected respectively desatin and eleventh informational outputs of the control unit, on which are formed the signal control block registers replacement and the unit register of the replacement part replacement unit, the third control output of the control unit is connected with the control input of the replacement unit, the second information input of which is connected to the information output of the memory block replacement, from the first to the third information input of which is connected respectively with the twelfth through fourteenth informational outputs of the control unit, which generates control signals memory device, the addresses of rows and columns of random access memory and data stored in the random access memory of the memory block replacement, from the fourth to the ninth control outputs of the memory block are connected respectively with the first to sixth control inputs of the storage unit of the second information input of which is connected to the first information output unit of analysis for search, data output replacement unit connected with the first information input of the storage unit of the first and second control inputs RESET" and "START" control unit are external inputs to the device.

BPVH - block of memory occurrences is used for recording, storing and issuing of occurrences of the chain of characters that must be detected in the processed word./p>

APPU are - memory block of the processed word is used for recording, storage and distribution of processed words with which you want to conduct search operations.

BAP - block search Analytics is used to analyze the search operation, determine how search occurrences in the processed word, and determining the address of the entry.

BPSM - memory block replacement is used for recording, storing and issuing replacement in the registers of the register unit of the replacement.

BSAM - replacement unit serves to perform operations: 1) write the symbol of the processed words in case of a negative comparison, 2) recording the substitution in the registers of the register unit of the replacement, if there is a positive comparison in block comparator.

BHR - block of storage of the results can be used to record and store the addresses of entries in the processed words and results of operations replacement.

BOO - control unit is used for generating control signals for the device.

The processes of search occurrences in the processed word, you can perform both serial and parallel modes of symbolic processing. To form a new word possible with the help of replacement operations, as well as left or right concatenation [1].

When performing search operations occurrences in the processed word is to reach a high speed of search and replace.

P is the claim of occurrences in the processed word can be carried out in two working modes: 1) identifying occurrences, having common parts, 2) determination of the occurrence of the non-shared parts [7]. Such a search procedure which meets the requirements set, is called to be correct.

The device used random access memory in which is stored information [2]. The occurrence of the processed word and replacing rewritten from memory in the shift registers. The processes of recording and reading of information in the registers can be the following: parallel input - parallel output, is used in the register for storing occurrences, the serial input - serial output is used to register for storing replacement, as well as the serial input-parallel output, is used to store in the register of processed words [3], [5]. The device used a neural elements and threshold logic [4].

When performing search functions occurrences can be represented by various combinations of letters in a word processed [7, 8].

1) there is no repetition of the same letters (iteration) in the processed word;

2) repeat the same letters in the middle of the processed words, it is assumed the designation W{A}P;

3) iteration exists at the end of a word, symbol N {};

4) iteration in the processed word exists in the beginning of the word, the symbol {A}R;

5) iteration in the processed word is available the t and at the beginning of words and at the end, the symbol {A}S{A}.

6) the processed word consists entirely of iterations, the notation {}.

Depending on the type iteration algorithm, performing a search operation occurrence in processed word [7, 8].

In the proposed device the search entry in the processed word is running in parallel. All occurrences of symbols in parallel arrive at the first inputs of the comparator. On the second input, also in parallel, the node comparing the received symbols are processed words. In the device parallel search and replace occurrences in the processed words used three register - register entry, the register of the processed words and register replacement. The length of registers, which store the entry and word processed, and the number of Comparators that compare the characters are the same. If there is a positive comparison, the output of the comparator is formed by a single value. In this case, in the processing of word occurrence. In the case of a device operating in the search mode is determined by the address entry. If the device is in the mode of search and replace, in case replacement is written to the string of characters to replace. The processed word is not changed in the process of replacing. If there was a negative comparison, it is necessary to move the processed word on the od of the n discharge to the left and to compare the following series of characters equal to the number of the occurrences of symbols. The process of shifting the processed word in the register is to determine the sign of the end of the processed words. The symbol in the result of the left shift is recorded in the register of replacement. In case of replacement of written symbols processed words in the result of the operation of the left shift register or letter substitutions in the mode of the device search and replace. In the device operations of the left and right concatenation.

1 shows a block diagram of the device parallel search and replace occurrences in the processed words.

Figure 2 presents different technical implementations of memory blocks: occurrences, the processed words and replace.

Figure 3 shows a functional block circuit analysis of search operations and block comparator.

Figure 4 shows a functional block circuit analysis, search, and combinational circuits: address generation and method of conducting search operations.

Figure 5 shows a functional block circuit registers occurrences.

Figure 6 shows the functional block circuit registers the processed words.

7 shows a functional diagram of the replacement unit.

On Fig depicts a block diagram of the register unit replacement.

Figure 9 depicts the functional diagram of the unit registers of the replacement./p>

Figure 10 shows the block diagram of the storage unit of the result.

On figa, 11b, 11b - content GAW operation.

On figa, 12B, 12B - tagged GAW operation.

The device parallel search and replace occurrences in the processed words (figure 1) contains the block 1 of memory occurrences, the memory unit 2 is processed words, block 3 analysis search unit 4 memory replacement, unit 5 replacement, unit 6, the storage of the block 7 of the control.

To describe the algorithm unit 7 controls the following identifiers are used.

1. The water economy Department of - control signals for the memory device of the memory block occurrences: reset, chip select, read/write.

2. ADH address column and row of RAM memory block occurrences.

3. DWR data recorded in the random access memory of the memory block occurrences.

4. The I - output of the random access memory of the memory block occurrences.

5. CSS - control signals for the memory device of the memory block of the processed words: reset, chip select, read/write.

6. ADOs address column and row of RAM memory block of the processed words.

7. DOS data written in the memory device blueplate processed words.

8. OS - the output of the random access memory of the memory block of the processed words.

9. USM - control signals for the memory device of the memory block replacement: reset, chip select, read/write.

10. Adsm address row and column random access memory devices of the memory block replacement.

11. MBT - data stored in the random access memory of the memory block replacement.

12. ZM - output data from the random access memory of the memory block replacement.

13. WPRV - control signals: reset, clock, signal shaping modes of registers of the register unit of occurrences of the block analysis of the search.

14. UPRS - control signals: reset, clock, signal shaping modes of registers of the register unit of the processed words of the block analysis of the search.

15. SV - signal of a left shift by one bit information block registers occurrences of the unit of analysis of the search.

16. WITH a signal of a left shift by one bit information unit registers the processed words of the block analysis of the search.

17. PCP - output binary signal from the block analysis of the search, which determines the result of the comparison of characters entering and processed the words.

18. GTO - unlocking the pulse - control signal from the control unit, appearing at the inputs of the logic is of such schemes And unit of analysis the search for counting the signals of the shift when determining addresses of occurrences in the processed word.

19. SOIL characteristic operation of the device with the common parts, the binary signal analysis block search that determines the mode of the device: 1) the search with the common parts, 2) the search without the common parts in the processed word.

20. UAN - an information signal received from the control unit to the inputs of R1, R2, R3 installation in the zero state of the binary counter unit of analysis of the search.

21. RTH - output information signal analysis block search, specifying address occurrences in the processed word.

22. BOC - binary signal analysis block search that determines the mode of the device search occurrences in the processed word without the common parts.

23. CMi - input information signal symbol block reference registers occurrences.

24. SIM - output information signal of the unit register listings.

25. NUMBER 1 - the symbol of the processed words of the first register WG1 unit registers the processed words.

26. OCi - output information signal symbols processed words of register unit processed the words.

27. PEC - terminator symbols processed words, no information 00...0.

28. UKL - control signal of the control unit is received at the control inputs of circuits And block replacement.

29. BONDS - information signal: reset, clock, write enable and data output received at control inputs of the registers unit replacement.

30. ORSM - information signal: reset, clock, write enable and data output received at control inputs of the register unit of the replacement.

31. OSSM information signal symbols processed words or replacement, coming to the information input of the register unit of the replacement.

32. RZ - output information signal is the result of replacing coming from the output of the register unit of the replacement.

33. BONDS - information signal of the control unit: reset, clock, write enable and data output, appearing on the control inputs of the registers of the register unit replacement.

34. REZ - information signal, the result of the replacement or the address of the entry in the processed word, coming to the information input of the random access memory unit store the result.

35. HELL STL - address column random access memory devices for recording the replacement or address entry in the storage unit of the result.

36. HELL PAGE addresses of rows of random access memory for recording the replacement or address entry in the storage unit of the result.

37. GI is the generator of impulses from the control unit to a summing input (+) of the binary counter SC block store the result.

38. T - heartbeats coming from backupsonline on summing input (+) of the binary counter SC block store the result.

39. ABOUT command reset binary counter SC block store the result.

40. The CONDITION "0" - command reset binary counter SC block store the result.

41. VK - command chip select random access memory RAM of the storage unit of the result.

42. SC/St command read/write random access memory RAM of the storage unit of the result.

43. REPS - output random access memory unit storing the results of substitutions or address listings in the processed word.

44. The RESET signal reset - reset elements of the memory device perform a parallel search and replace.

45. The START signal the beginning of the operation.

The work of the unit parallel search and replace occurrences in the processed words.

Meaningful GSA control shown in figa, figb, 11b, and reflects the operation of the control unit (figure 1).

In unit 2 of the algorithm on the signal "RESET" is setting to zero all elements of the device (figure 1).

In block 3 of the algorithm on the command "RESET:=1" is being installed in one state of the signal RESET.

In unit 4 of the algorithm analyzes the characteristic operation of the device START. The output of the block unit starts the operation of the device parallel search and replace occurrences in the processed word is.

In block 5 of the algorithm at the command of PVC:=water economy Department is filing the information signal to the input of the memory block occurrences. Information signal, the water economy Department consists of control signals: chip select signals enable writing and reading data from the RAM block. Team POS:=CSS supplied a similar information signal CSS from the control unit to the input of the memory block of the processed words. Team TZM:=USM on the control inputs of the operational storage device replacement receives control signals: chip select signals enable writing and reading data from the RAM block (1, 2).

In block 6 of the algorithm at the command of PVC:=Advh to the input of random access memory block of memory occurrences are served addresses of rows and columns for recording occurrences in RAM. Team POS:=Ados input RAM memory block of the processed words are given addresses of rows and columns for recording in the memory the processed words. Team TZM:=Adsm to the input of random access memory of the memory block replacement serves the addresses of rows and columns for recording replacement in RAM (1, 2).

In block 7 of the algorithm at the command of PVC:=WRD on the information input RAM memory block occurrences do data - entry, representing a chain of characters that must be detected in the developing word. After this operation ends, the operation of loading the data in the random access memory of the occurrences. Team POS:=DOS in random access memory-data - processed words. Team TZM:=MBT online storage device writes the data replacement. Blocks 5, 6, 7 this is the download operation occurrences, the processed words and substitutions in the random access memory blocks: memory occurrences, the memory of the processed words and memory replacement (figure 1, 2).

In block 8 of algorithm analyzes the characteristic operation of the device search and replace occurrences in the processed words - EBL. At the exit THERE is a transition to the 51 end of the block algorithm operation. Output YES, you move on block 9 of the algorithm.

In block 9 of the algorithm analyzes the sign of the left-concatenation - LEK, i.e. the accession of entry to the treated word to the left. This operation has the form {S}P, where S is the occurrence, and the P - processed word. On the output THERE is transition to a block 14 of the algorithm. Output YES, you go to the block 10 of the algorithm.

Blocks 9, 10, 11, 12, and 13 are organizing a cycle in which the operation is performed left concatenation. The loop will allow you to get one or multiple connection entry to the treated word to the left, it can be written as {{S1}...{Sn}}R.

In block 10 were elaborated to the and command UKL:=1 at the control input unit replacement - BSAM from the control unit control signal UKL equal to the unit (Fig.7). In this operation, the data block register replacement through open electronic keys with direct control inputs and diagrams OR fed to the input of the unit register of the replacement. When this operation is carried out left concatenation.

In block 11 of the algorithm on the team PGSM:=BONDS to the inputs of register unit replacement receives control signals from the control unit. It signals: authorizing the issuance of data, clock (Fig.7). Team Blrz:=ORSM from the control unit serves the control signals that result in the recording of outputs schematic OR block of registers of the replacement. It signals: recording resolution data and clock (Fig.7).

In block 12 of the algorithm on the team OSM:=ZM to the input data register unit of the replacement data is received from the register unit replacement.

In block 13 of the algorithm on the team Blrz:=ZM in the register unit of the replacement recorded occurrence of registers unit replacement (Fig.7).

In block 14 of algorithm analyzes the sign of the right-concatenation - DAG, i.e. the accession of entry to the treated word to the right. This operation has the form P{S}, where R is the processed word, a S - entry. On the output THERE is transition to a block 20 of the algorithm. Output YES, you move on th the 15 of the algorithm.

Blocks 14, 15, 16, 17, and 18 can arrange cycle, the result of which operation is in progress right concatenation. The loop will allow you to get one or multiple attaching the workpiece to the word entry on the right, it can be written as P{{S1}...{Sm}}.

In block 15 of the algorithm at the command of the UKL:=0 on the control input of the electronic keys replacement unit - BSAM from the control unit control signal UKL equal to zero (Fig.7). In this operation, the data block registers the processed words through open electronic keys with inverted control inputs and diagrams OR fed to the input of the unit register of the replacement. If this is a write operation symbols processed words in the block of registers of the replacement.

In block 16 of the algorithm at the command of Burgos:=OPRS to the inputs of register unit processed words are received control signals from the control unit. It signals: resolution of data output, the clock (6, 7). Team Blrz:=ORSM from the control unit serves the control signals that result in the recording of outputs schematic OR block of registers of the replacement. It signals: recording resolution data and the clock (7, 9).

In block 17 of the algorithm on the team OSM:=OS input data register unit of the replacement data is received from a block of registers obrabatyvaemogo the word (6, 7, 9).

In block 18 of the algorithm on the team Blrz:=OSSM in the register unit of the replacement of the written word processed from a block of registers processed words (6, 7).

In block 19 of the algorithm is analyzed characteristic connected concatenation CON left or right. Exit YES of block transitions to block 9 of the algorithm, in this case, the process of accessions continues or goes to the block 20 of the algorithm. On the output THERE is transition to a block 43 of the algorithm to write the result of the concatenation in the random access memory unit storing the results.

As a result of performing these cycles the following composition occurrences and processed words: {S}P - one left concatenation, {{S1}...{Sn}}P - n left concatenation, and P{S} - right concatenation and R{{S1}...{Sm}} - m right concatenation.

In block 20 of the algorithm on the team Blwh:=UPRV on the control inputs of the registers of the register unit of occurrences of the control unit serves the control signals: recording resolution information, a clock, set to the zero state registers (1, 5). Control signals are fed simultaneously to all inputs of the registers of the block. The team Bros:=OPRS on the control inputs of the registers of the register unit processed the words from the control unit serves the control signals: recording resolution slo is a, the clock, reset registers (1, 6). At the command of the GTO:=1 to control inputs of the electronic keys from the control unit served unlocking signal is equal to a single value. Through an open electronic key, the scheme And the direct Manager of the entrance, the number of shift pulses fed to the input circuit OR (figure 4). Command NAV:=ST to a summing input of a binary counter NAV signals of ST. shift from a block of registers occurrences. The number of pulses of the shift of the ST defines the number of characters in the entry (3, 4).

In block 21 of the algorithm on the team Blwh:=I for informational inputs of the registers of the register unit occurrences in parallel from a block of memory occurrences are occurrences of symbols I (2, 5). The team Bros:=OS for informational inputs of the registers of the register unit processed the words in sequential mode character by character from a memory block of the processed words are symbols processed words for search operations (2, 6).

In block 22 of the algorithm is analyzed terminator processed words PEC. In the case of the control signal PEC equal to zero - there is NO way out of the block, this means that all characters are processed words viewed and register the processed word is empty (Fig.6). In this case, the transition is performed in block 43 of the algorithm. If a PC signal is equal to the single value - exit YES block search in the processed word continues (6). In this case, the transition is performed in block 23 of the algorithm.

23 algorithm command COM:=I to the first input of the comparator receives the symbols occurrences of REF. Command COM:=OS on the second input of the comparator receives the symbols of the processed words of the OS. The comparator performs the comparison operation symbol occurrences and processed words. The comparison operation unit analyzing search is performed in parallel character (figure 3).

In block 24 of algorithm analyzes the characteristic of the comparison for equality symbol occurrences and processed word - PCP. If the comparison has been positive, the signal at this PCP is equal to a single value output unit "unit", then transitions to the block 31 of the algorithm. In case of a negative comparison for equality of input values output "zero" block, the PCP signal is equal to zero, this takes you to the block 25 of the algorithm.

In blocks 25, 26, 27, 28 executes the write operation of the symbol being processed words in the register of the register unit of the replacement, if there was a negative comparison of the characters of the processed words and occurrences (figure 3, 7, 9).

In block 25 of the algorithm at the command of the UKL:=0 control signal from the control unit is fed to the inputs of the electronic keys with INVERS the YMI control inputs, thus, Otera electronic keys. As a result, the inputs of the circuits OR enters the symbol being processed words, which will be recorded in the register of the register unit of the replacement. This is characterized by a negative comparison of characters entering and processed words (Fig.7).

In block 26 of the algorithm on the team OSM:=OS for informational inputs of the register of the register unit of the replacement arrives symbol processed words OS for further recording it in the register unit (Fig.7).

In block 27 of the algorithm on the team Blrz:=ORSM on the control inputs of the registers of the register unit of the replacement receives an information signal from the control unit ORSM. The result of this operation registers of the block are set to the zero state at the inputs of the registers receives the clock pulses and the recording resolution information in the registers unit (Fig.9).

In block 28 of the algorithm on the team Blrz:=NUMBER 1 to the inputs of the register of the register unit of the replacement arrives symbol processed word NUMBER 1. This operation is carried out in case of a negative comparison in block comparator characters processed words and occurrences (7, 9).

In block 29 of the algorithm at the command of Burgos:=WITH the control input of the register unit registers the processed speech signal shift. The result of this operation is processed with the PSBs is shifted by one digit to the left to perform the search operation (6).

In block 30 of the algorithm at the command of the GTO:=0 from the control unit receives the control signal GTO equal to zero. The signal is sent to an inverse input circuit And an electronic key. As a result of this electronic key to be opened, and through him, and the circuit OR the signal left shift will arrive at the summing input of the binary adder NAV (Fig 3, 4). Command NAV:=CO summarizing the counter input signal left shift WITH to count the number of left-shift signals processed words to form the address of the entry in the processed word (figure 4).

The output of block 30 of the algorithm goes to block 22 of the algorithm for the comparison of characters entering and shifted to the left by one digit of the processed word. The result is a cycle in which you will view all the characters of the processed words. Cyclic operation will continue until the terminator is encountered processed words PEC.

In block 31 algorithm analyzes the characteristic operations: 1) search, 2) search and replace - PZ. If the device works only mode search - there is NO escape, then transitions to block 43 of the algorithm. In the case of operation search and replace - output DA algorithm then proceeds to block 36 algorithm.

In blocks of algorithm 32, 33, 34, and 35 is determined by the method of processing the TCI information: 1) search, 2) search and replace. There are two types of combinations of occurrences in the processed word: 1) with the common parts symbol occurrences, 2) without common parts symbol occurrences. The first is when the previous entry in the processed word and the next is a common side - characters. In this case, the search entry in the processed word is immediately on the next shift of the processed words, after a positive comparison of characters entering and processing words. The second type is when comparing symbols to the n signals of the left-shift of the processed words, where n is the number of occurrences of symbols.

Unit 32 analyzes the characteristic operation of the device with the parts of output and without common parts - NO exit - signal GROUND. In the case of selecting the mode of operation of the device with the common parts are moving to a block 22 of the algorithm. If the device is in the search mode without the common parts, then jumps to the block 33 of the algorithm.

The blocks 33, 34 and 35 form a cycle, which is the left-shift of the processed words of one category as long as the signal BOC - characteristic operation of the device without the common parts will not be equal to zero.

In block 33 of the algorithm is analyzed binary signal indication without the common parts BOC (figure 4). If the signal is already equal to zero output block zero, then it moves on to the block 22 of the algorithm. In case of equality single value of the signal output unit" block, then jumps to the block 34 algorithm.

In block 34 of the algorithm at the command of Burgos:=WITH on the control inputs of the registers of the register unit of the processed speech signals of a left shift by one bit to perform shift of data to be processed words to the left (6).

In block 35 of the algorithm on a command by command SCV:=CO subtractive input of a binary counter SCU receives signals of the left shift register unit registers the processed words. In the counter SCV operation is performed subtraction. The number of occurrences of symbols is subtracted admitted to the subtractive input of the number of signals of a left shift by one digit of the processed words. Previously when loading characters entry in the registers of the register unit entry in summing binary counter ESS will be recorded information in binary code corresponding to the number of symbol occurrences. Will pre-install subtractive counter SCV. If the result at the output of the counter is equal to zero, it means the processed word is shifted by a certain number of digits to the left equal to the number of occurrences of symbols (1, 4).

Blocks 36-42 algorithm performs a write operation of replacing the registers BC the AC registers of the replacement. If the device works as a search and replace and it found the entry in the processed word, in the registers of the register unit of the replacement store the character string replace (2, 7, 9).

In block 36 of the algorithm on the team PGSM:=BONDS to the inputs of register unit replacement receives control signals from the control unit. It signals: authorizing the issuance of data, clock (figure 1, 7).

In block 37 of the algorithm on the team PGSM:=ZM registers unit replacement is written to the replacement of the memory block replacement (2, 7).

In block 38 on the team UKL:=1 at the control input unit replacement - BSAM from the control unit control signal UKL equal to one. By performing this operation, the data block register replacement through open electronic keys with direct control inputs and diagrams OR fed to the input of the register unit of the replacement (Fig.7).

In block 39 of the algorithm on the team PGSM:=BONDS from the control unit to the inputs of register unit replacement receives control signals: authorizing the issuance of data, clock (figure 1, 7).

In block 40 the team Blrz:=ORSM from the control unit serves the control signals that result in the recording of outputs schematic OR block of registers of the replacement. It signals: recording resolution data and clock (1, 7).

In block 41 of the algorithm on the team OSM:=ZM n the information input unit data registers of the replacement data is received from the register unit replacement (Fig.7).

In block 42 of the algorithm on the team Blrz:=OSSM you rewrite entry in the registers of the register unit of the replacement (7, 9). The output from this block jumps to the block 49 algorithm.

In block 43 of the algorithm is analyzed performing device operations: 1) search 2) search and replace, 3) the concatenation of the left or right (R) or (PZ) or (CON). The result of the execution of the function is defined using a logical OR operation. If you have not run any of these operations the device output is NO block, then transitions to block 8 figa. In the case of performing at least one of these operations - exit YES block, then goes to block 44 of the algorithm.

In block 44 of the algorithm on the team RTH:=NAV is determined by the address of the entry in the processed word, which is a binary counter NAV unit analysis search. Address entry is formed by the number of left-shift signals received at the summing input of the counter NAV, first occurrence, then the processed words (figure 4).

In block 45 of the algorithm on the team REZ:=(ADV)or(RA) is determined by the result of the CUT using a logical OR operation. Search result address entry, or search and replace or after repeated substitutions received a new word from a block of registers of the replacement arrives on the information input from the operator the main storage device of the storage unit of the (7, 10).

In block 46 algorithm command VK:=0, MF/3P:=0 signals: chip select and write/read from unit 7 of the control, set the recording mode information in the RAM of the storage unit of the result. On control inputs received zero values, which corresponds to the recording mode in the RAM device input information (figure 10).

In block 47 algorithm command RAM:=ADSL and RAM:=Adstr to the address inputs of the random access memory unit storing the received address column ADSL and row - Adstr. Address columns and rows define a binary counters SC and SC block. At these locations, the data is written in RAM block (figure 10).

In block 48 of the algorithm at the command RAM:=REZ on the input information input of the operational storage device of the storage unit of the receiving the RESULTS of the operations: search or search and replace or concatenation (figure 10).

In block 49 of the algorithm at the command of Burgos:=WITH the control input of the register unit registers the processed words of the block control signal shift. The processed word when it is shifted by one digit to the left for further search operations (6).

In block 50 of the algorithm at the command of the GTO:=0 from the control unit receives the control signal GTO zero. The signal at the inverted input of the CX is we - an electronic key, which opens, through him, and the circuit OR the signal left shift will arrive at the summing input of the binary adder NAV (Fig 3, 4). Command NAV:=CO summarizing the counter input signal left shift WITH to count the number of left-shift signals processed words to form the address of the entry in the processed word (figure 4).

The output of block 50 of the algorithm goes to block 32 figb algorithm for analyzing how search occurrences in the processed word search with the common parts or without common parts.

The block 51 of the algorithm is finite.

The operation of the device parallel search and replace occurrences in the processing of words is as follows.

External control signals "RESET" and "START" are received in the control block 7. In the memory block of the processed words in random access memory block will be written to the processed words. In these words it is necessary to detect occurrence. In the block of memory occurrences in the operating data storage unit recorded occurrences of characters that you want to find in the processed word. Symbols occurrences and processed words are received at the comparator input in parallel. During operations the left or right of concatenations to the processed word attached to the left or right entry. If the device is operating in the mode of search occurrences in the processed words, the detected symbols, a positive comparison of the comparator calculates the address is the location of the occurrences in the processed words. These addresses is recorded in the storage unit of the result. In the case of the device in the mode of search and replace, upon detection of occurrences in the processing of words is the replacement operation. The write operation of the replacement is performed in the third register - register replacement. If an entry is not found, the characters of the processed speech is under control of the signals of the left shift the data by one digit is written in the third register replacement. In the third shift register will be written to the replacement characters in case of detection of occurrences in the processed words or symbols processed words, if the output of the comparator established a negative result.

Block 1 of memory occurrences BPVH contains random access memory RAM DD8, in which the recorded chain of characters - occurrences. The input information input unit water economy Department consists of control signals: chip select chip and the recording mode is reading data from the RAM block. The address inputs of RAM - signal ADH are the addresses of rows and columns for which data is being written into the memory block. Information data of DWR data are occurrences that come to the information inputs of the operational zapominayusche the device memory block. The signals chip select and write-enable the water economy Department, and address inputs ADH, these occurrences are recorded in the random access memory of the memory block. The output information signal of the block is the signal I - occurrences, which is fed to the input of the block of memory analysis (figure 1, 2).

The memory unit 2 is processed words APPU are contains random access memory RAM DD9. In the RAM block is recorded, processed words with which you want to conduct search operations. The input information input unit CSS consists of control signals: chip select chip and the recording mode is reading data from the RAM block. The input information signals Ados are the address inputs of RAM. Signal Ados consists of the addresses of rows and columns for which data is being written into the memory block. Information DOS data are processed words that come to the information inputs of the random access memory of the memory block. The signals chip select and write-enable CSS, and address inputs Ados, the data is processed words are written in the random access memory of the memory block. The output information signal of the block being processed words OS are sent to the input unit of analysis of the search (figure 1, 2).

Unit 3 analysis of search BAP contains: block, bear in mind that the listings DD11, the unit registers the processed words DD12, binary n - bit comparator DD13, DD14, DD15 performed on the neurons, logic And executed on the threshold element DD16, Raman scheme address generation entry - Xhf, combinational circuit that determines the mode of the device without the common parts BOC - Choc (3, 4). Unit function analysis of the search are in the recording, storage and issuance of characters in the binary equivalent of occurrences and the processed words, in a bitwise comparison of symbol occurrences and processed words in the comparator, the formation of addresses occurrences in the processing of words, but also the determination of the mode of the device without the common parts BOC (3, 4). The input information signal forming operation registers occurrences of the device is to signal OPRV. This signal is applied to control inputs of the registers unit occurrences of unit 7 of the control (Fig 1, 3). This signal includes control signals that determine the operation mode of the unit: resolution recording, storing and issuing of binary digits occurrences, the signal reset registers, signal left shift information, the sync pulses. For informational inputs register unit receives the data - entry I of the memory block occurrences (figure 2, 3). The output information signal of the unit register of occurrences is supplied to the first who moves schemes comparisons - comparator (figure 3). The input data signal block registers the processed speech signal is UPRS, which is supplied to control inputs of the register unit registers the processed words from unit 7 controls. This signal consists of signals forming modes registers: resolution recording, storing and retrieving information from the register unit, the signal left shift the data by one digit, the clock signals reset registers (figure 3). For informational inputs of the registers of the register unit of the processed words supplied information signal OS - processed words of the memory block of the processed words (2, 3). The output information signal of the registers of the register unit of the processed words is supplied to the second inputs of the circuits comparisons - Comparators performed on the neural elements DD13, DD14, DD15 (figure 3). The inputs of the comparator circuits comparisons do bitwise characters occurrences and processed words in binary equivalent. The output signals of the comparator receives the inputs of the circuit And threshold elements DD16. The Comparators operate in the equality of input values. Schema comparisons performed by adders modulo two. The output signal of the comparison - PCP block analysis of search will be equal to a single value only if the input variable character entry and clicks nativeimage words will be equal. This means the equality symbol occurrences with a slice of processed words. A single value of the signal PCP means that the entry was found in the processed word. In this case, the address is formed occurrence in processed word in the search mode of operation of the device or written to replace in the registers of the block of the replacement mode search and replace operation. If the output of the circuit And the signal PCP is equal to zero, the equality of input values to the comparator input has not occurred, in this case it is necessary to move the processed word by one digit to the left, then analyze the result of the comparison of the characters of the entry and the next segment is processed words (3, 6). The output control signal of the block is the signal terminator characters processed word - PEC, which is supplied to the control input of the control block 7. If the terminator processed words PEC is equal to a single value, it means that not all characters are processed words seen in the registers of the register unit processed the words still have the binary information. In case of equality of this signal is zero, this means that all characters are processed words viewed. In the registers of the register unit of the processed speech information is not available registers "empty" (3, 6). The output information is Onen signal block is the symbol of the processed words coming from the output of the first register WG1 unit registers the processed word - NUMBER 1, which is fed to the input of the replacement unit (3, 6, 7). This symbol will be recorded in the register of the register unit replacement in case of a negative comparison of the input values in the comparator unit. The unit of analysis of search logs Raman diagram of the address generation entry - Xhf. The output of this combinational circuit is defined by an information signal address entry in the processed word - ADV, which is fed to the input of the storage unit of the result. Control signal at the input of combinational circuits, the address generation unit of analysis search unit 7 of the control signal is GTO - enabling pulse. This signal is applied to the control inputs of circuits And executed on the threshold elements DD17 and DD18. The schema And element DD17 has inverted control input, the circuit And the element DD18 has direct control input. On the information input circuit And DD element 17 receives the signal FROM the shift to the left by one digit from the input registers of the register unit processed the words. On the information input schema And element DD18 signal SV - shift to the left by one digit from the input register block registers occurrences (figure 4). The output signals of the circuits AND DD17 and DD18 arrive at the inputs of the circuit OR element DD1. The output signal of the circuit OR DD19 is fed to a summing input of a binary address counter NAV DD20. At the output of the counter NAV will be determined by the address of the entry in the processed word. The address formed from the sum signal of the left shift, first in the boot in case of occurrence, then when you search, register of processed words. Pre-binary address counter NAV DD20 will be reset by setting signal in the zero - EAC coming from unit 7 control input R1 - install in the zero state of the binary counter (figure 4). First signal OTI - unlocking pulse width equal to a single value. In this case the scheme AND DD17 will be locked - signal at the inverted control input, and the circuit AND DD18 will be open, as the signal at the direct control input. The number of signals of the left shift register entry through an open circuit AND DD18, scheme OR DD19 arrive at the summing input of a binary counter NAV DD20. The number of signals of ST. shift will correspond to the number of symbol occurrences. After unlocking pulse GTO set to the zero state. As a result of this scheme AND DD17 will be open, the signal is fed to an inverse input schema, and the schema AND DD18 is locked, the signal is applied to the direct entry scheme. In this case, the signals of the left shift register processed words through the open circuit AND DD17, the scheme AND THE AND DD19 arrive at the summing input of a binary counter NAV DD20. In the counter is counting the number of signals of the left shift register processed words. As a result of these procedures at the output of the binary counter will generate an address entry in the processed word, i.e. the location of a particular fragment in the full chain of characters processed words (figure 4). Combinational circuit that determines the mode of the device without the common parts of Choc contains: schema AND DD21, summing the binary counter ESS DD22, subtractive counter SCV DD23, scheme OR DD24. The mode of the device without the common parts searches in the processed words that do not share common characters between the previous and subsequent occurrences [7]. To generate this mode in case of detection of occurrence in the processed word you need to move the processed words to the left by m bits, where m is the number of occurrences of letters. Pre-binary counters ESS DD22 and SCV DD23 will be reset to zero by signal H supplied from the control block 7. The inputs reset R2 and R3 counters respectively receives signals installed in the zero state elements. If the device is in the search mode occurrences without the common parts, the signal from block 7 to control SOIL characteristic work with the common parts takes the unit value. The control signal AL is supplied to a direct control input e is ljuca schemes AND DD21, opening her. Through an open circuit And the signals of the left-shift of ST. occurrences arrive at the summing input of a binary counter ESS DD22. Counter in the ESS will be the counted number of occurrences of symbols. The outputs of the sum counter ESS arrive at the inputs D1-Dx subtractive counter SCV. The result of this operation is preset subtractive counter SCV into a binary value equal to the number of symbol occurrences. On the subtractive input of the counter SCU receives signals shift to the left WITH the processed words. The output of subtractive counter SCV calculates a difference between the number of occurrences of symbols and the received signals of the shift of the processed words. Logic OR DD24 defines a zero value signal BOC - characteristic operation of the device without the common parts. If the signal BOC equal to zero, it means that the input word is shifted by m bits to the left, where m is the number of symbol occurrences. The result of this operation it is necessary to continue the operation of comparing characters entering and processing words. The output control signal BOC sign work without the common parts of the block search Analytics is supplied to the control input of the control block 7 (Fig 1, 4).

Unit 4 memory replacement BPSM contains random access memory RAM DD10. In block RAM recorded chain symb is fishing, which is recorded in a replacement unit if the unit is operating in the search mode, and replacement. In the case of a positive comparison of characters entering and processing the word string of characters that replacement will be recorded in the register of unit replacement. The input information signal USM consists of control signals: chip select chip and the recording mode is reading data from the RAM block. The input information signals of Adsm are the address inputs of RAM. The signal was Adsm consists of the addresses of rows and columns, on which information is recorded in the memory unit. Information MBT data are replacement characters, which are sent to the information inputs of the random access memory of the memory block. The signals chip select and write-enable USM, and the address inputs of AZM, data replacement is recorded in the random access memory of the memory block. The output information signal of the block - replace ZM is fed to the input of the replacement unit (1, 2).

Unit 5 replacement BSAM contains unit 10 registers the replacement PGSM DD31, electronic keys scheme And direct control inputs made at the threshold elements DD32, DD33, DD34, electronic keys scheme And inverse control inputs made at the threshold elements DD35, DD36, DD37, system elements OR executed on the threshold element is x DD38, DD39, DD40, perform a collective function unit 11 registers the replacement Blrz DD41 (Fig.7). The function of this unit parallel search and replace occurrences in the processing of words is to control the write operation to the register unit of the replacement symbol processed words, if the output of the comparison circuit is set to zero or letters of replacement, in case of a positive comparison of the input values in the comparator device mode of operation search and replace. Unit 10 registers the replacement PGSM DD31 is designed for recording, storing and issuing of replacement characters. Replacement is carried out in case of detection of symbol occurrences in the processed word and in the mode of the device search and replace. The input information signal AFFECTIONS is supplied to the control inputs of the registers of the register unit replacement and consists of control signals: left shift the data by one digit, clock, formative modes of recording, storing and retrieving binary code. The input information of the replacement signal SM is supplied to the information input registers block. The parish governing permissive signals from the control block 7 is replacement characters in the registers of the register unit replacement. The output information signal of the register unit replacement bitwise supplied to the information input system e is ectronic keys DD32, DD33, DD34 with direct control inputs. The input information signal of the register unit replacement is the signal NUMBER 1. This signal comes from the output of the first register WG1 DD27 unit registers the processed words Burgos (6). Information signal NUMBER 1 is supplied to the information input system of electronic keys DD35, DD36, DD37 with inverted control inputs. Information outputs of electronic keys DD32, DD33, DD34, DD35, DD36, DD37 arrive at the inputs of the system elements OR DD38, DD39, DD40. Output information signals OR OSM act on the information inputs of the registers of the register unit of the replacement (Fig.7). Information signal OSM is the result of a logical function OR input values: NUMBER 1 - character processed words or symbols replace OSM=(NUMBER 1) or (SM). The input control signal replacement unit is the signal UKL - control coming from unit 7 control direct control inputs of the electronic keys DD32, DD33, DD34, and inverted control inputs of the electronic keys DD35, DD36, DD37 (Fig.7). If the control signal UKL equal to zero, the system of electronic keys with premimu control inputs DD32, DD33, DD34 will be locked and electronic keys with inverted control inputs DD35, DD36, DD37 will be opened. In this case, the symbol being processed word NUMBER 1 through the open electricity the major keys DD35, DD36, DD37 and system logic elements OR DD38, DD39, DD40 will arrive on the input information input registers of the register unit of the replacement (Fig.7). On the arrival of the information signal ORSM on the control inputs of the registers of the register unit of the replacement of the unit 7 controls the input information OSM will be recorded in the registers of the register unit of the replacement. The control signals of the registers block: C, P/S, A/S form modes: left-shift the data by one digit, synchronization, recording, storage and distribution of the in registers of the block. In case of equality of control signal UKL single value system electronic keys with direct control inputs DD32, DD33, DD34 will be opened, and the electronic keys with inverted control inputs DD35, DD36, DD37 will be closed. In this case, the replacement characters ZM through open electronic keys DD32, DD33, DD34 and system logic elements OR DD38, DD39, DD40 is fed to the input information of the input registers of the register unit of the replacement, where on arrival control signals ORSM will be recorded and stored in the unit (Fig.7). The output information signal of the unit register of the replacement signal RZ represents information from the results of the replacement or symbols processed words. This signal is applied to the input of the storage unit of the (1, 7).

Unit 8 registers whodini Blwh contains n eight-bit universal shift registers WT1,..., RSE performed on the elements of the DD25, DD26 (figure 5). Registers block operate in the following modes: parallel input, parallel output, storage, installation zero (reset). Modes of operation registers are set by signals on the control inputs. Control signals are fed in parallel to all registers. From unit 7 controls on the control inputs of the registers receives the information signal WPRV - mode control unit operation registers occurrences (figure 1). The inputs of DR and DL provide modes of shift information to the right and left respectively. The ST. entrance is a clock control inputs S1 and S0 form the modes of registers, R is used to set the registers to the zero state. The input information signals of the block of registers of occurrences of an information signal I - occurrences. This signal comes from the output of the memory block occurrences of (1, 2). Information signals in parallel do for informational inputs of the registers. In each case the block will be written one character that has an eight-bit binary code. At the output of the register will also be eight-bit binary equivalent. The registers have eight informational inputs CMi and eight outputs CMi. For parallel input information in the registers of the block on the two control inputs must be S1=S2=1. Information from inputs CMi will be recorded in the registers and singing is seeking outputs CMi drop of 0.1 clock pulse SV. When the control inputs will be S1=S2=0, the registers operate in the mode information storage. Setting to zero state is performed by applying to the input R, zero [3]. Before you begin all the registers of the register unit occurrences will be reset to zero by filing a " zero " level to the reset inputs R. Upon arrival of the input information signal I, which is fed in parallel to the inputs of registers and consists of information signals CMi, ..., CMn, installation at the inputs of all the registers of the block when S1=S2=1 writes the information in the registers of the register unit occurrences. Storing binary in registers block occurs when S1=S2=0 (figure 5). The input control signal SV clock pulse arrives at the inputs of elements And combinational circuits unit of analysis of the search (figure 4, 5). The output information signal I, consisting of information signals CM1,..., CMn, unit is the character string of occurrences that must be detected in the processed word.

Unit 9 registers the processed words Burgos contains n eight-bit universal shift registers WT1, Wt2,..., RSE, performed on the elements of the DD27, DD28, DD29, logic OR executed on the threshold element DD30 (6). Registers block operate in the following modes: serial input-parallel output, storage, installation zeros (the Bros). Modes of operation registers are set by signals on the control inputs. Control signals are fed in parallel to all registers. From unit 7 controls on the control inputs of the registers receives the information signal UPRS - mode control unit operation registers the processed words. Control signals, P/S and A/S are received at all of the registers in parallel. The signal WITH the synchronizing clock pulse, the combination of signals, P/S and A/S determine the operating modes registers block. The signal P/S forms the input method information signal A/S - asynchronous/synchronous [3]. The input information signal OS - processed word is transferred to the input register RSE DD29 of the memory block of the processed words. When signals of the shift information from the right register RSE element DD29 is shifted to the left register WG1 item DD27. In parallel mode, the characters are processed words NUMBER 1, NUMBER 2, neo,..., OCf received at the second inputs of the Comparators. The first inputs of the Comparators receives symbols occurrences (figure 3). The result of the comparison can be zero or a single value output from the comparator signal. If the output of the comparator is established unit, the search operation has been positive, then there is an occurrence is detected. In the case of obtaining a zero value at the output of the comparator, a signal is generated shift to the left on tinytrak characters processed words. The output signal from outputs of the first register WG1 arrives at the inputs of logic circuit OR element DD30 (6). The output control signal is a sign of the end of the processed words of the PEC with the output of the circuit defines zero OR a combination of the input schema. Zero binary code 0 ... 00 is a terminator characters processed words. In this case, all characters are processed words in registers block is seen. If the terminator processed word is equal to a single value, then registers the block has a binary information. The search process in this case is ongoing. The clock signal WITH an output control signal of the register unit processed the words, which arrives at the inputs of elements And combinational circuits unit of analysis of the search (figure 4, 6).

Unit 10 registers the replacement PGSM s contains eight-bit universal shift registers WT1, Wt2,..., s performed on the elements of the DD42, DD43, DD44 (Fig). Registers block operate in the following modes: serial input, serial output, storage, installation zero (reset). Modes of operation registers are set by signals on the control inputs. The registers are connected in series. On the control inputs of the registers of the control block 7 receives an information signal AFFECTIONS - management modes the operation of the register unit replacement. Opravlyaushi the signals, P/S and A/S are received at all of the registers in parallel. The signal With the synchronizing clock pulse, the combination of signals P/S and A/S determine the operating modes registers block. The signal P/S forms the input method information signal A/S - asynchronous/synchronous [3]. The input information signal SM is the replacement character is received at the input of the right register s DD44 of the memory block replacement. When generating signals of a left shift by one digit information from the right register s element DD44 output of the left register WG1 item DD42 (Fig). Initially, the device is not working all the registers of the block will be zeroed. In the search mode and replace the left or right of the concatenation, in the parish of control signals from unit 7 controls the replacement characters are written from the memory block replacement in the registers of the register unit replacement (2, 8). The output information signal of the register unit replacement is a binary code symbols replace - SM. The unit is in recording mode, storage and distribution of information. Information delivery is the mode of search and replace operation. If the processed word is detected occurrence, it is necessary in the registers of the register unit of the replacement record replacement - the string of symbols. In this case, the registers of the block is operating in the mode of delivery of information (Fig.7, 8).

Unit 11 registers the replacement Blrz contains m University for the real eight-bit shift registers WG1, Wt2,..., DDM, performed on the elements of the DD45, DD46, DD47 (Fig.9). Registers block operate in the following modes: serial input, serial output, storage, installation zero (reset). Modes of operation registers are set by signals on the control inputs. The registers are connected in series, the previous output is the input of the following. On the control inputs of the registers of the control block 7 receives an information signal ORSM - management modes the operation of the unit registers of the replacement. The control signals C, P/S and A/S are received at all of the registers in parallel. The signal With the synchronizing clock pulse, the combination of signals P/S and A/S determine the operating modes registers block. The signal P/S forms the input method information signal A/S - asynchronous/synchronous [3]. The input information signal OSM symbols processed words or replacement is fed to the input of the right register DDM element DD47 outputs of logic circuits OR replacement unit (Fig.7). When generating signals of a left shift by one digit information from the right register DDM element DD47 output of the left register WG1 item DD45 (Fig.9). Initially, the device is not working all the registers of the block will be zeroed. In the search mode and replace characters, replace recorded in the registers of the register unit of the replacement. In the case of operations left reproval concatenation in the registers of the register unit of the replacement symbols are written replacement and processed words (Fig.9). In the search mode in the registers of the register unit of the replacement symbols are written the processed words. The output information signal of the unit register of the replacement is a binary code symbol of the replacement - RH. The unit is in recording mode, storage and distribution of information. The result is handed in case of detection of signs of the end of the processed speech signal PEC equal to zero. The output information signal of the result of the replacement - RZ block registers of the replacement to the input of the storage unit of the (Fig.9, 10).

Unit 6 storage of BHR contains the logic OR executed on the threshold element DD48, the binary counter generates the addresses of the columns of RAM - SC DD49, the binary counter generates the addresses of the rows of RAM - SC DD50, random access memory RAM DD51. Binary counters at the beginning of the operation of the device reset control signals, the CONDITION "0", coming from the control block 7. The inputs of the counters arrive rectangular pulses KI-TI from the control block 7. Counters form the addresses of rows and columns, which will be recorded the results of the search or replacement, at the input of operational storage device RAM DD51. The input information signals of the block are information signal ADV - address entry and information is ignal RZ - the results of the replacement. Information signals arrive at the inputs of the circuit OR DD48. The output information signal RES is the result of the operation OR enters the information input random access memory RAM DD51. If the device is in the search mode occurrences will be recorded address of occurrences. If the device is in the mode of search and replace, in the random access memory will be written to the results of the replacement, in case of a positive comparison of the comparator. The control signals random access memory RAM DD51 the chip select and read/write, respectively, when recording take values VK=0, MF/3P=0 (figure 10).

The control block 7 is synthesized on the basis of GSA control algorithm (figa, 11b, 11C) in a known manner [6]. Tagged GSA unit 7 of the control shown in figa, 12B, 12B, where indicated:

The logical conditions are true:
X1:"RESET"X7:"PEC"
X2:START"X8:"PCP"
X3:"EBL"X9:"PZ"
X4:"LEK"X10:"MAIL"
X5:"DAG"X11:BACH"
X6:"KON"X12:"(P) or (PZ) or (CON)"
Operators:
N1:RESET:=1" U:"Blwh:=UPRV"
U2:"PVC:=water economy Department"U:"GTO:=1"
U3:"POS:=CSS"U:"NAV:=SV
A4:"TZM:=WSM"U:"Blwh:=I"
U:"PVC:=ADH"U:"Burgos:=OS
U:"POS:=Ados"U:"COM:=I"
U:"TZM:=AZM"U:"COM:=OS
U:"PVC:=WRD"U:"Brgr:=NUMBER 1"
U:"POS:=DOSU:"Burgos:="
U:"TZM:=MBT"U:"GTO:=0"
U:"UKL:=1"U:"NAV:="
U:"PGSM:=AFFECTIONS"U:"RTH:=NAV"
U:"Blrz:=URSM"U:"REZ:=(ADV) or (RA)"
U:"OSM:=SM"U33:VK:=0"
- Y15:"Blrz:=SM"U:"MF/3P:=0"
U: "UKL:=0"U:RAM:=ADSL"
U:"Burgos:=OPRS"U:RAM:=Idstr"
U:"OSM:=OSU:RAM:=REZ"
U:"Brgr:=OSM"U:"SCV:="

Sources of information

1. Kudryavtsev V.B. have been, Podkolzin A.S., accomlish W. introduction to theory of abstract machines. M.: Moscow University press, 1985. 174 C.

2. POM A., Agrawal O. high-speed memory systems. - M.: Mir, 1987. - 264 FF., Il.

3. Zeldin E.A. Digital integrated mikros the volumes in the information measuring apparatus. - L.: Energoatomizdat., Leningrad. separa-tion, 1986. - 280 S.: ill.

4. Mkrtchyan S.O. design of the logical devices of the computers on the neural elements. - M.: Energy, 1977

5. Alexenko A.G., Sagarin I.I. Microcircuitry: Textbook. manual for schools. - 2nd ed., revised and enlarged extra - M.: Radio and communication, 1990. - 496 S.: ill.

6. Baranov, S. Synthesis of microprogrammed machines. Energy, Leningrad branch. 1974 - 184 C.

7. Patent No. 2250493 (prototype).

8. Patent No. 2209465 (similar).

9. Patent No. 2199778 (similar).

10. Patent No. 2202823 (similar).

The device parallel search and replace occurrences in the processing of words that contains a block of memory occurrences, the control unit, characterized in that the added memory block of the processed words, the unit of analysis of the search, the memory block replacement block replacement block of storage of the result, and the first to third information output control unit which respectively generates control signals memory device, the addresses of rows and columns of random access memory and data stored in random access memory, connected respectively with the first through third information input of the memory block occurrences, the information output of which is connected to the first information input unit of analysis the search, the second information input of which is outinen information output memory block of the processed words, from the first to the third information input of which is connected respectively with the fourth to sixth information output control unit which respectively generates control signals memory device of the memory block of the processed words, the addresses of rows and columns of random access memory and data stored in the memory device, from the third to the fifth control inputs which are connected respectively with the first through third control outputs of the unit of analysis of search, which are formed signals characterizing respectively the result of the comparison of characters entering and processed words, the mode of the device search occurrences in the processed word without the common parts and the terminator symbols are processed words, from the third to the fifth information unit of analysis search connected respectively with the seventh to ninth informational outputs of the control unit, which generates signals installed in the zero state of the binary counter, the control signals, forming modes register block registers occurrences and processed words, respectively, the first and second control outputs of the control unit, are respectively formed signals characteristic of the operation of the device with the parts and from irusi impulse connected respectively with the first and second control inputs of the unit of analysis search the second information output of which is connected to the first information input unit replacement, third and fourth information, the inputs of which are connected respectively with the tenth and eleventh informational outputs of the control unit, which generates control signals register unit replacement and the unit register of the replacement part replacement unit, the third control output of the control unit is connected with the control input of the replacement unit, the second information input of which is connected to the information output of the memory block replacement, from the first to the third information input of which is connected respectively with the twelfth through fourteenth informational outputs of the control unit, which generates control signals memory device, addresses of rows and columns of random access memory and data stored in the random access memory of the memory block replacement, from the fourth to the ninth control outputs of the memory block are connected respectively with the first through sixth control inputs of the storage unit of the second information input of which is connected to the first information output unit of analysis for search, data output replacement unit connected with the first information input of the storage unit of the first and second administration is allowing the input "RESET" and "START" control unit are external inputs to the device.



 

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FIELD: computer engineering, automated system for collecting and processing electronic polls data.

SUBSTANCE: system consists of input messages receiving unit, data from server database receiving unit, election committee identification unit, first and second units for candidates base addresses identification, polls results disclosure time cycles selection unit, polls results recording time cycles selection unit, input messages receiving time cycles selection unit, database read and write signals forming unit, final polls results data forming unit.

EFFECT: increased system performance due to database entries address localization using receiving messages identifiers and forming of progressive total of polls results in real-time.

9 dwg

FIELD: computer engineering, systems for supporting informational identity of geographically distributed databases of airline companies.

SUBSTANCE: systems consists of address identifiers unit, memory area identification unit, input message target selection unit, database entries base address selection unit, adder, read signal forming unit, six registers, database entries identification unit, entries quantity identification unit, counter, control signal forming unit, OR elements.

EFFECT: increased system performance due to database entries addresses localization using data sources and flights identifiers.

9 dwg

FIELD: computer engineering; system for data distribution control in information analytical center network of air company commerce unit.

SUBSTANCE: system contains three registers, renewed data entries address identification device, client query data address identification device, decoder, data read control signal forming unit, and data output channels commutation unit.

EFFECT: simplified system, increased performance by excluding memory buffer blocks and time interval selector, and asynchronous mode of server-client interaction implementation.

5 dwg

FIELD: computer engineering; structure-statistical analysis of informational arrays.

SUBSTANCE: device contains current evaluation signal former, evaluation zones discriminator, pulse distributor, time intervals counter, commutator, search variable former, adding counters, storage units, division units, classifier, search strategy register, reset signals former, data representation and write unit, threshold signals change unit, current day timer, cutoff threshold former unit, structural analyzer.

EFFECT: increased informativity of traffic values, which define informational arrays structure due to structural analysis of determinate combinations.

2 cl, 3 dwg, 1 apl

FIELD: digital data processing using electrical devices; informational search means and database structures; foreign language learning.

SUBSTANCE: electronic documents data is entered into the computer. Electronic documents objects to be searched in informational system are discovered. Electronic documents objects to be searched in informational system are compared to informational system database objects. Electronic documents data is transformed by marking objects of electronic documents. Electronic documents with marked electronic documents data objects are visualized. Before entering electronic documents data into the computer data objects to be searched in informational system are entered, data objects to be searched in informational system are compared to informational system database data objects and buffer database of data objects is formed. Comparison of electronic documents objects to be searched in informational system is done with data objects in buffer database of data objects.

EFFECT: creation of effective method for searching and marking of information data, that is to implement the learning function "learned repetition", which is based on individual approach to learning.

18 cl

FIELD: technology for recognizing text information from graphic file.

SUBSTANCE: in accordance to method, set in advance is order of access to additional information, assigned also is estimate of quality for each type of additional information, different variants of division of image of selected rows on fragments are constructed, for each fragment of row linear division graph is built, images of graphic elements are recognized, using a classifier, and an estimate is assigned to each recognition variant, transition from variants of recognition of graphic elements to variants of alphabet symbols is performed, for each chain, connecting starting and ending vertexes, chains are built, appropriate for all variants of recognition of graphical elements and variants of transitions from recognized graphical elements to alphabet symbols, produced variants are ranked in order of decrease of recognition quality estimate, produced variants are processed with usage of information about position of uppercase and lowercase letters, if more than one variant of symbol is available based on results of recognition of graphic element, variants are processed with successive usage of additional information, and/or when necessary simultaneous usage of all types of additional information, quality estimate is assigned to each produced variant, variants of symbols with estimate below predetermined value are discarded, produced variants are sorted using pair-wise comparison, and additional correction of recognition of spaces, erroneously recognized at previous stages, is performed.

EFFECT: increased precision of recognition of text and increased interference resistance of text recognition.

9 cl, 2 dwg

FIELD: computer science, technology for mutual transformation of document (for example, XML document) and program object (for example, Java language object).

SUBSTANCE: in such structure, interpreter is used, masking method for producing transformation properties. Due to that, transformation code is generated, having general type for transformation in both directions. Transformer transforms XML document to program object by means of analyzer 104. To execute reverse transformation (from Java language to XML) it is required, that elements of XML document are positioned in certain order to provide for validity of produced XML document 118. For this purpose, in accordance to invention, template XML document is generated using, for example, JSP technology. Template, created using JSP, allows recording tags of documents in JSP with possible reverse call for values of elements and attributes. Content may be sent to buffer or directly to the output stream of servlet.

EFFECT: it is possible to efficiently realize creation of structure for such transformation by means of standard tools.

4 dwg, 8 tbl, 2 ex

FIELD: computer science.

SUBSTANCE: method includes text messages from data channel, linguistic words processing is performed, thesaurus of each text message is formed, statistical processing of words in thesaurus is performed, text message and thesaurus are stored in storage. Membership of text message in one of categories from the list is determined, starting data value of text message is determined, stored in storage with text message, data value values are periodically updated with consideration of time passed since their appearance and text messages with data value below preset threshold are erased, during processing of each message values of categories classification signs are updated.

EFFECT: higher efficiency.

1 dwg

The invention relates to the publishing industry and can be used for the preparation and issue of reference books
The invention relates to the field of electronics and is designed, for example, to use auxiliary data arrays in the conversion process and/or verification of computer codes in the form of symbols, and the corresponding portions of the image
The invention relates to the field of electronics and can be used, for example, in the way of interrelated activation computer code in the form of symbols and corresponding portions of the image

FIELD: computer science.

SUBSTANCE: method includes text messages from data channel, linguistic words processing is performed, thesaurus of each text message is formed, statistical processing of words in thesaurus is performed, text message and thesaurus are stored in storage. Membership of text message in one of categories from the list is determined, starting data value of text message is determined, stored in storage with text message, data value values are periodically updated with consideration of time passed since their appearance and text messages with data value below preset threshold are erased, during processing of each message values of categories classification signs are updated.

EFFECT: higher efficiency.

1 dwg

FIELD: computer science, technology for mutual transformation of document (for example, XML document) and program object (for example, Java language object).

SUBSTANCE: in such structure, interpreter is used, masking method for producing transformation properties. Due to that, transformation code is generated, having general type for transformation in both directions. Transformer transforms XML document to program object by means of analyzer 104. To execute reverse transformation (from Java language to XML) it is required, that elements of XML document are positioned in certain order to provide for validity of produced XML document 118. For this purpose, in accordance to invention, template XML document is generated using, for example, JSP technology. Template, created using JSP, allows recording tags of documents in JSP with possible reverse call for values of elements and attributes. Content may be sent to buffer or directly to the output stream of servlet.

EFFECT: it is possible to efficiently realize creation of structure for such transformation by means of standard tools.

4 dwg, 8 tbl, 2 ex

FIELD: technology for recognizing text information from graphic file.

SUBSTANCE: in accordance to method, set in advance is order of access to additional information, assigned also is estimate of quality for each type of additional information, different variants of division of image of selected rows on fragments are constructed, for each fragment of row linear division graph is built, images of graphic elements are recognized, using a classifier, and an estimate is assigned to each recognition variant, transition from variants of recognition of graphic elements to variants of alphabet symbols is performed, for each chain, connecting starting and ending vertexes, chains are built, appropriate for all variants of recognition of graphical elements and variants of transitions from recognized graphical elements to alphabet symbols, produced variants are ranked in order of decrease of recognition quality estimate, produced variants are processed with usage of information about position of uppercase and lowercase letters, if more than one variant of symbol is available based on results of recognition of graphic element, variants are processed with successive usage of additional information, and/or when necessary simultaneous usage of all types of additional information, quality estimate is assigned to each produced variant, variants of symbols with estimate below predetermined value are discarded, produced variants are sorted using pair-wise comparison, and additional correction of recognition of spaces, erroneously recognized at previous stages, is performed.

EFFECT: increased precision of recognition of text and increased interference resistance of text recognition.

9 cl, 2 dwg

FIELD: informatics; computer technology.

SUBSTANCE: device can be used for soling tasks of composing dictionaries, manual as well as for creation of new databases. Device has entrance memory unit, processed words memory unit, unit for analyzing search, substitution memory unit, substitution unit, result storage unit, control unit.

EFFECT: widened functional abilities; improved reliability of operation; simplified algorithm of operation.

16 dwg

FIELD: engineering of computer components for ordering graphic elements, shown through graphic user interface.

SUBSTANCE: a system of presenting means provides base class of presenting means and a set of interface methods, realized by presentation mechanism, for creation and integration of expandable set of classes of presenting means for processing data of graphical elements of various types during composition operation in given visible image. System of presenting means allows realization of complex image composition operations through calls of presentation mechanism. Aforementioned complex image composition operations include: breaking into pages, partial computation, stepwise computation, a set of samples, alteration of capabilities/operations of composition.

EFFECT: expanded functional capabilities, due to support of compositions of visible images of application, to which a set of graphic elements is assigned.

4 cl, 15 dwg

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