Information finding device

FIELD: electric communications, possible use for finding and quickly identifying information in multi-service digital data transfer networks with commutation of packets.

SUBSTANCE: device contains N generators of time intervals, N selection blocks, frequency divider, N temporary storage registers, N two-input AND elements, solving three-input element AND, N-input OR-NOT element, electronic key, mask storage register, n-input AND-NOT element, control block.

EFFECT: expanded area of possible use of device, increased speed of operation.

5 cl, 6 dwg

 

The claimed technical solution relates to the field of telecommunication and can be applied to search and quickly identify information in a multi-service digital network data packet.

The known device information search - see, for example, Awsw of the USSR №1621049 "Device information", IPC G 06 F 15/40 declared 09.01.89, Awsw of the USSR №1711185 "Device information", IPC G 06 F 15/40 declared 05.04.89.

Known analogues registers borders, summarizing and subtractive counters, the comparison circuit, the memory blocks, blocks, calculating a number of other elements, allowing people to search for information. During reception of digital messages and search specific digital sequence it is necessary to define its parameters, and the line transfer sequence communication rules defined for this Protocol. Known analogues do not fully comply with these requirements.

In the first analogue of the definition of the communication packets is realized with the probability of correct detection of less than 0.1, because recognition is a statistical method and does not take into account the characteristics of the serial communication.

In the second similar significant disadvantage is the inability to obtain a unique solution due to the low level, the reliability and probability of identification communication Protocol (less than 0.3), as the search information blocks implemented dichotomic method without taking into consideration the allowable sequences of packets.

Known the closest analogue (prototype) for their technical nature of the claimed device is the device of the Patent of the Russian Federation No. 2115952 "Device information", IPC G 06 F 17/40 published 20.07.98.

The device prototype includes a memory block, the register search strategy and subtractive counter, frequency divider, the switch, the first, second, third and fourth units of selection, the shaper time intervals and the display unit.

In the device prototype output of the frequency divider is connected with the first inputs of the memory block, subtractive counter, first, second, third and fourth block selection register search strategy. The outputs of the memory block are connected respectively with the fourth-eleventh input switch and the first output of the subtractive counter is connected to the tenth input of the memory block, the twelfth sign of the switch, the eleventh sign of the first block selection, tenths inputs of the second, third and fourth units of selection, a third input register search strategy and is a command output device. The second output of subtractive counter is connected to the eleventh inputs of the second, third and fourth units of selection, and the third output calc the melting of the counter is connected to the twelfth sign of the first block selection. The outputs of the switch are connected with the second-ninth inputs of the first, second, third and fourth units of selection, respectively, and first and second outputs of the first block selection connected respectively with the first and second inputs of the switch. In this third output of the first block selection is connected with the fourth input register search strategy and fourteenth subtractive input of the counter, and the fourth output of the first block selection is connected to the fifth input of the register search strategy, the fourteenth subtractive input of the counter and the input of the shaper time intervals. The fifth output of the first block selection connected with a third input of the switch. The sixth output of the first block selection and the first outputs of the second, third and fourth unit of selection, the output of register search strategy is connected to the first input of the display unit, the tenth sign of the first block selection and fourteenth subtractive input of the counter. The second output of the second block selection connected with a second input register search strategy, and the second output of the third block selection connected with a third input of the register search strategy. The second output of the fourth block selection and the output of the shaper time intervals connected with a second input of the display unit and the fourteenth subtractive input of the counter. The input of the frequency divider, the second of the ninth WMO is s memory block and the second to the thirteenth subtractive inputs of the counter are respectively the input clock frequency, signal and data inputs of the device.

This scheme allows for comparison with devices with peers to carry out the opportunity to use the device in near real time, and to provide a zero probability of missing (in case of availability of reliable a priori information about the Protocol) at the expense of syntactic recognition for the TFTP Protocol, based on the transaction identification transmitted over the channel packages and rules of the share during a communication session.

However, this device has the disadvantage of a narrow field of application, namely only for the analysis of the TFTP Protocol. In addition, identification of packets in the device prototype is carried out by the method of successive structural parsing. Packet analysis Protocol stack packet data showed that identification of packets of different protocols are possible by comparing the values of the fields in the package or combinations thereof with reference values that are unique for each of the protocols, and this comparison can be performed in parallel (Zolotov, S. Internet Protocols. - SPb.: BHV - Saint Petersburg, 1998. - 304 S.: ill.). The analysis of networks constructed on the basis of TCP/IP showed that the vast majority of security breaches in the network of this type is associated with the DDoS, which are in the formation directed the first storm of packets (for example, requests for establishment of a connection) to the address of the attacked network node, causing unintended consumption of host resources, which reduces the efficiency of the operation, and sometimes to the complete unavailability of resources for network subscribers (Medvedovsky I.D. and other Attack on the Internet. - M.: DMK, 1999. - 336 S.: ill.). The sequence of receipt of these packets can fully comply with the rules of exchange of information, provided the specifications for the appropriate Protocol (e.g., agreements taken to stack the TCP/IP Protocol number of consecutive incoming requests on the connection is not limited). The device is a prototype allows you to parse protocols without regard to possible abuses associated with the presence of a large number of duplicate packet types.

The purpose of the claimed technical solution is to develop a device search information, ensuring the expansion of the application area and improve performance by implementing parallel structural identification of packages of a wide range of packet data transmission, and detection of repetitive sequences of packets with valid control intervals in which they appear.

The goal in the claimed device information search shortcuts is presumed to those in the known device service requests of subscribers of a computer system containing N shapers time intervals, where N≥1, N units of selection, the frequency divider, the input of which is the first clock input devices, inputs of N registers for temporary storage, the N input elements And permitting trekhgolovy element And N-shadowy the element OR NOT, electronic key, the register storing a mask, N-shadowy element And the control unit.

In the inventive device the output of the frequency divider is connected to the second clock input shapers time intervals. The corresponding bits of the K-bit input Code storage time, where K≥1 - bit time code storage, shapers time intervals are interconnected and are the corresponding bits of the K-bit input Code time storage devices. Enabling inputs N shapers time intervals and the first entrance allowing Tregubova element And connected with each other and are permissive input device. The corresponding bits of M-bit information inputs, where M≥1 - the number of binary digits of the analyzed block of information N registers for temporary storage, N units of selection and the electronic key are interconnected and are relevant bit is DAMI first M-bit information input device. Inputs Initializing N shapers time intervals and the storage register masks are interconnected and are a sign of Initializing the device. Output allowing Tregubova element And is connected to the input "Enable" shapers of time intervals, an electronic key and is the output Resolution of the device. Thus the i-th output Selection block control unit, where i=1, 2...N, is connected to the input Selection block of the i-th imaging unit time intervals. The output of the i-th input element And is connected to the i-th entry of the N-Vodolaga of the element OR NOT and entry the result of the comparison of the i-th imaging unit time intervals. The output of the "Installation" of the i-th imaging unit time intervals connected with input "Setting" of the i-th register of temporary storage. Exit Status block the i-th imaging unit time intervals connected with a second input of the i-th input element And the i-th input of the control unit and the i-th entry of the N-Vodolaga element. Output N-Vodolaga item AND IS NOT connected with the third input Tregubova element And is output "device Status" device. The bits of the M-bit input "setting the mask register storing masks are the corresponding bits of M-bit input "set mask" device. Bits M-bit output of the register storing the mask connected to the corresponding bits of the M-rasra the data input Mask N block selection. M-bit output of the i-th register of temporary storage is connected to the second M-bit information input of the i-th block selection. Exit "Preliminary results" of the i-th block selection connected to the first input of the i-th input element And. Inverted output N-Vodolaga item OR IS NOT connected to the second input allowing Tregubova element And. M-bit information output electronic key is the third M-bit information output device.

The shaper time intervals comprises first, second, third and fourth two-input elements And the first and second input elements OR NOT, two-element AND-NOT two-element OR RS-flip-flop and counter. K-bit counter input is a K-bit input Code storage time" shaper. The first input of the first input element And is connected to the second input of two-input element AND IS NOT and is the input Selection block shaper. The second input of the first input element And an input Resolution of the shaper, the output of the first input element And connected to the first information input of the RS-flip-flop, the first input of the first input element OR NOT and is the output of the Installation of the driver. The second input of the first input element OR NOT an entrance "is the result of the comparison of the shaper. Inverted output of the first input element OR IS NOT connected with an inverted installation of the meter inlet. The first input of two-input element OR an input of the Initialization of the driver. The output of two-input element OR is connected with the second information input of the RS-flip-flop. Thus the output of RS flip-flop connected to the first input of the third two-input element And the second input of the second input element And the first input of the fourth two-input element And. the fourth input element And an output of "Status block" shaper. The first input of the second input element And is the second clock input of the shaper. The output of the second input element And is connected to the counting input of the counter and its inverted output overflow is connected to a second input of the second input of the element OR NOT. Inverted output of the second input element OR IS NOT connected to the second input of the third two-input element And. the Output of the third two-input element And is connected to the reset input of the counter and a second input of two-input OR. Inverted output of two-input element AND is connected to a second input of the fourth two-input element And. the First input of the second input element OR IS NOT connected to the first input of two-input element AND IS NOT and is permissive input FD is MyRoutes.

The block selection consists of the first and second groups of input elements And M elements in each group and the comparator. The first input of the j-th input element And the first group of input elements And, where j=1, 2...M, is the j-th digit of the first M-bit information input unit selection. The first input of the j-th input element And the second group of input elements And is the j-th digit of the second M-bit information input unit selection. The second input of the j-th input element And the first group of input elements And is connected to a second input of the j-th input element And the second group of input elements And is the j-th category of the M-bit input Mask block selection. The output of the j-th input element And the first group of input elements And connected to the j-input of the first group of information inputs of the comparator. The output of the j-th input element And the second group of input elements And connected to the j-input of the second group of information inputs of the comparator, and the output of the equality comparator is the output of "Preliminary result" unit of selection.

Electronic key consists of M input elements And. the first input of the j-th input element And is the j-th category of M-bit information input electronic key is. The second inputs of two-input elements And are interconnected and are the input "Enable" electronic key. The output of the j-th input element And is the j-th category of M-bit information output electronic key.

The control unit consists of an encoder of priorities, the first group of inverters of the P inverter, wherethe second group of N inverters inverters decoder. Thus the i-th inverted input encoder priorities is the i-th entry Status block control unit, and the k-th inverted output of the priority encoder, where k=1, 2...P, is connected to the input of the k-th inverter of the first group of inverters. Inverted output of the k-th inverter of the first group of inverters connected to the k-th input of the decoder, the i-th inverted output of the decoder is connected to the input of the first inverter of the second group of inverters. Inverted output of the first inverter is the i-th output Selection block control block.

Specified a new set of essential features due to the introduction of N registers for temporary storage, the N input elements And allowing Tregubova element And N-Vodolaga of the element OR NOT, electronic key, the register storing a mask, N-Vodolaga element AND-NOT and the control unit increases the performance of the device, the possibility of expanding the range of identification packages and the opportunity is present is ugenia sequence of duplicate packets by checking the tolerance intervals of the journey, which leads to the possibility of using the claimed device for identification protocols by structural analysis packages, and to protect against potential abuses associated with the presence of a large number of duplicate packet types.

Conducted by the applicant's analysis of the level of technology has allowed to establish that the analogs are characterized by the sets of characteristics is identical for all features of the declared unit of search information is missing. Therefore, the claimed invention meets the condition of patentability "Novelty".

Search results known solutions in this and related areas of technology in order to identify characteristics that match the distinctive features of the prototype of the characteristics of the claimed invention, have shown that they do not follow explicitly from the prior art. Of certain of applicant's prior art there have been no known impact provided the essential features of the claimed invention to the achievement of the technical result. Therefore, the claimed invention meets the condition of patentability "Inventive step".

The stated objects of the invention are illustrated by the drawings, in which:

figure 1 - the unit of search information;

figure 2 - shaper time intervals;

figure 3 - block selection

figure 4 - electronic key;

figure 5 - control;

figure 6 - timing diagram of the operation of the device.

The device (see figure 1) consists of N shapers time intervals 1.1-1.N, where N≥1, N block selection 3.1-3.N, the frequency divider 8, N registers for temporary storage 2.1-2.N, N input elements And 4.1-4.N allowing Tregubova element And 6, N-Vodolaga of the element OR NOT 5, an electronic key 7, the register storing the mask 9, N-Vodolaga element AND-NOT 10, control unit 11.

The elements are connected as follows (see figure 1). The input of the frequency divider 8 is the first clock input 18 of the device, and its output connected to the second clock inputs 19 shapers time intervals 1.1-1.N. the Corresponding bits of the K-bit input Code storage time", where≥1 - bit time code storage, shapers time intervals 1.1-1.N are interconnected and are the corresponding bits of the K-bit input "time Code storage device 14. Enabling inputs 13 shapers time intervals 1.1-1.N and the first entrance allowing Tregubova element And 6 are interconnected and are permissive input device 13. The corresponding bits of M-bit information input, where M≥1 - the number of binary digits of the analyzed block of information N registers the belt storage 2.1-2.N, N block selection 3.1-3.N and electronic key 7 are interconnected and are the corresponding bits of the first M-bit information input device 12. Inputs Initializing shapers time intervals 1.1-1.N and the register storing the mask 9 are interconnected and are input Initializing device 15. Output allowing Tregubova element And 6 are connected to inputs "Resolution" 29 shapers time intervals 1.1-1.N, electronic key 7 is the output Resolution 29 of the device. When the output Selection block 21.i each control unit 11 is connected to the input Selection block corresponding shaper time intervals 1.i. The output of the i-th input element And 4.i connected with i-th entry of the N-Vodolaga of the element OR NOT 5 and the entrance to the Result of comparison of the i-th imaging unit time intervals 1.i. Exit "Setup" 22.i each shaper time intervals 1.i connected to the input of "Installing" the relevant register of temporary storage 2.i. The exit Status of the block 24 of each shaper time intervals 1.i connected to the second input of the corresponding input element And 4.i, i-m input control unit 11 and the i-th entry of the N-Vodolaga element AND-NOT 10. Output N-Vodolaga item AND NOT 10 is connected to the third input allowing Tregubova element And 6 is the exit status of the device is VA 20 devices. The bits of the M-bit input "set mask" 16 register storing the mask 9 are the corresponding bits of M-bit input "set mask" 16 devices. Bits M-bit output of the register storing the mask 9 is connected to the corresponding bits of M-bit input Mask 17 N block selection 3.1-3.N. M-bit output of the i-th register of temporary storage 2.i connected to the second M-bit information input 25.i block selection 3.i. Exit "Preliminary result" 26.1-26.N each block selection 3.1-3.N connected to the first input of the corresponding input element And 4.1-4.N. Inverted output N-Vodolaga of the element OR NOT 5 is connected to the second input allowing Tregubova element And 6, and M-bit information output electronic key 7 is the third M-bit information output device 28.

Registers are temporary storage 2.1-2.N are designed to retain a copy of the received block of information. The register storing the mask 9 is designed to store a bit mask is necessary to compare significant bits of a data block. Job description and diagram of such registers is known and described, for example, in the book: Law, Nsize and other "Digital integrated circuits". The Handbook. - M.: Radio and communication, 1994, p.57-62.

The frequency divider 8 is intended to provide a synchronizing sequence is lnasty pulses and can be built by any known scheme. See, for example, Law, Nsize and other Reference "Digital integrated circuits". - M.: Radio and communication, 1994, pp.62-74. When the input divider is the counting input of the counter, and the output of the divider is one of the outputs of the counters.

Shapers time intervals (FWI) 1.1-1.N are designed to control entry into the appropriate registers for temporary storage, control, time keeping and generating a status signal corresponding registers for temporary storage. PVI may be implemented by any known scheme taking into account the described functions. In particular, its scheme is shown in figure 2, consists of the first 1.1, 1.9 second, third, 1.4 and 1.10 fourth two-input elements And the first 1.7 and 1.3 second two-input elements OR NOT, two-input element AND NOT 1.11, input element OR 1.6, RS-flip-flop 1.2, 1.8 meter. K-bit counter input 1.8 is a K-bit input Code storage time" 14 FWY. The first input of the first input element And 1.1 is connected to the second input of two-input element AND NOT 1.11 and is the input Selection block 21 FWY. The second input of the first input element And 1.1 is the entrance of "Resolution" 29 FVI. The output of the first input element And 1.1 is connected to the first information input of the RS-flip-flop 1.2, the first input of the first input element OR NOT 1.7 and it is you who Odom "Installation" 22 FWY. The second input of the first input element OR NOT 1.7 is the entrance of "comparisons" 27 FVI. Inverted output of the first input element OR NOT 1.7 is connected with the inverse of the installation of the meter inlet 1.8. The first input of two-input element OR 1.6 is the entrance to the "Initializing" 15 FWY. The output of two-input element OR 1.6 is connected with the second information input of the RS-flip-flop 1.2. The output of the RS-flip-flop 1.2 connected to the first input of the third two-input element And 1.4, the second input of the second input element And 1.9 and the first input of the fourth two-input element And 1.10, the output of which is the exit Status of the block 24 FVI. The first input of the second input element And 1.9 is the second clock input 19 FVI. The output of the second input element And 1.9 is connected to the counting input of the counter 1.8. Inverted output of counter overflow 1.8 is connected to a second input of the second input element OR NOT 1.3. Inverted output of the second input element OR NOT 1.3 is connected to a second input of the third two-input element And 1.4. The output of the third two-input element And 1.4 is connected to the reset input of the counter 1.8 and a second input of two-input element OR 1.6. The first input of the second input element OR NOT (1.3) is connected to the first input of two-input element AND-NOT (1.11) and is permissive input 13 FVI. Inverted output d is ukwholesale element AND-NOT (1.11) is connected to a second input of the fourth two-input element And (1.10).

RS-trigger 1.2 is designed to store a logical value that determines the operating mode of FWI, and can be built by any known scheme. See, for example, Integrated circuits. The Handbook. Edited Tarabrina - 2nd ed., Corr. - M.: Energoatomizdat", 1985, s.

The 1.8 meter is designed to account arriving at its input counting pulses generate a control signal defined by the code of the initial fill on the information inputs and the repetition period of the clock pulses, that is, performs the function of a configurable timer. Job description and diagram of this counter is known and described, for example, in the book: Law, Nsize and other "Digital integrated circuits: a Handbook", - M.: Radio and communication, 1994, p.64-65.

Blocks selection 3.1-3.N designed for comparing bits of the newly received block of information bits of the data blocks previously stored in registers for temporary storage 2.1-2.N (including masks) and the formation of the comparison, and the comparison is based masks. The block selection can be implemented by any known scheme taking into account the described functions. In particular, its scheme is shown in figure 3, the selection consists of the first and second groups of input elements And M elements in each group 3.11-3.1M, 3.21-3.2Mand comparator 3.3 the first input of the j-th input element And the first group of input elements And, where j=1, 2...M, is the j-th digit of the first M-bit information input 12 unit selection. The first input of the j-th input element And the second group of input elements And is the j-th digit of the second M-bit information input 25 of the block selection. The second input of the j-th input element And the first group of input elements And is connected to a second input of the j-th input element And the second group of input elements And is the j-th category of the M-bit input Mask 17 block selection. The output of the j-th input element And the first group of input elements connected to the c j-th information input of the first group of information inputs of the comparator 3.3. The output of the j-th input element And the second group of input elements And connected to the j-input of the second group of information inputs of the comparator 3.3. The output of the equality comparator is the output of "Preliminary result" 26 block selection.

The comparator 3.3 is designed to compare two M-bit binaries installed on its inputs, and generating the comparison result. Job description and diagram of the comparator is shown, for example, in the book: Wllile "Popular chip TTL", - M.: "ARGUS", 1993, .183-184.

The electronic key 7 is designed for switching arriving at its input M-bit binary code at its output PR is the presence of the enabling signal and may be implemented by any known scheme taking into account the functions described. In particular, his scheme, shown in figure 4, consists of M input elements And 7.1.1-7.1.M. The first input of the j-th input element And is the j-th category of M-bit information input electronic key. The second inputs of two-input elements And are interconnected and are input "Resolution" 29 electronic key. The output of the j-th input element And is the j-th category of M-bit information output electronic key.

The control unit 11 is designed to select from the many available for the use of PVI PVI with the lowest number and may be implemented by any known scheme. In particular, its scheme is shown in figure 5, consists of an encoder priorities 11.1, the first group of inverters of the P inverter, wherewhere- the operation of rounding to the nearest larger integer, the second group of N inverters inverters 11.21-11.2P, 11.41-11.4Nand decoder 11.3. Thus the i-th inverted input encoder priorities 11.1 is the i-th input "module Status" 24.i control unit, and each inverted output of the priority encoder 11.1 is connected to the input of the corresponding inverter of the first group of inverters. Inverted output of each inverter of the first group of inverters is connected with the corresponding input of the decoder 11.3. It is jdy inverted output of the decoder 11.3 connected to the input of the corresponding inverter of the second group of inverters. Inverted output of the first inverter of the second group of inverters is the i-th output Selection block 21 of the control unit.

Encoder 11.1 and decoder 11.3 designed to convert one or more low level signals on one of the inputs of the encoder 11.1 binary code is the least of them the output of the decoder 11.3. This conversion is carried out taking into account the priorities of the signals corresponding to the numbers of inputs. Schemes for their implementation are known and described, for example, in the book Wllile "Popular digital circuits", M.: Radio and communication, 1987, s-148.

To explain the operation of the device consider the following modes of operation:

initializing the device.

the operation of the device upon receipt of the first subject analysis block of binary information (BDI);

the operation of the device when receiving the subsequent level.

Initialization of the device is as follows. On the M-bit input "setting the mask 16 is set to a bitmask, bit width equal to the width of the analyzed DND. The bit mask is intended to indicate significant bits DND, through which his identification. The values of logical units digit of this mask correspond to positions of significant bits in the first M-bit information input device 12. In all other positions the operations must be set to logic zero. On the K-bit input Code storage time" 14 device code is set, it specifies the maximum time to keep a copy of the BDI in the device. The lowest retention time corresponds to the greatest code, which is in addition to the maximum number representable in K-bit code. To permit entrance 13 is set to a logical zero, and at the entrance to the "Initializing" 15 - a logical unit. A logical unit at the input of the Initialization 15 is supplied to corresponding inputs of FVI 11-1Nand to the input of the initialization of the register storing the mask 9. A logical unit at the input of the initialization of the register storing the mask 9 provides the bit mask register, with bits M-bit output 17 of the register storing the mask 9 will correspond to the values of the corresponding bits of the mask. A logical zero on permissive input device 13 is supplied to corresponding inputs of FVI 11-1Nand the first entrance allowing Tregubova element And 6. While a logical zero at the first entrance allowing Tregubova element And 6 provides a logical zero at its output regardless of the logical values of the inputs. A logical zero output Tregubova element And 6 output Resolution 29 of the device and the inputs of FVI 11-1Nand according to the corresponding input of the electronic key 7. A logical zero input "Resolution" 29 electronic key 7 is fed to the respective inputs of two-input elements And 7.11-7.1Mproviding at their outputs, respectively, on all bits of the third M-bit information output device 28 logical zeros, regardless of the values of the bits of the first M-bit information input device 12. A logical zero at the output of "Resolution" 29 device means the absence of information to read on the third M-bit information output device 28. A logical zero on permissive input 13 FVI is fed to the input of two-input element AND NOT 1.11, which leads to the appearance at the output of the logical unit that, when the second input of the fourth two-input element And 1.10, ensures compliance with the logical value at the output of the fourth two-input element And 1.10 logical value at its first input. A logical zero input "Resolution" 29 FVI is fed to the input of the first input element And 1 that provides a value of logical zero at its output, which is fed to the input S of the RS-flip-flop 1.2 and on exit "Setting" 22 FWY. Exit "Setup" 22 FWY is designed to control the entry of information into the appropriate register for temporary storage 2. The logic zero at the input S of the RS-flip-flop 1.2 combine the modern with the logical unit at its input R, coming from the entrance to the "Initializing" 15 through the input element OR 1.6, leads to the installation at the output of RS flip-flop 1.2 logical zero, which in turn blocks the entrance to the counting input of the counter 1.8 clock pulses from the second clock input 19 FVI, generates a logical zero at the output Status block 24 FVI. The value of logical zero at the output Status block 24 PWI means that this FVI free and ready to work, and in the corresponding register of temporary storage may contain information that should not affect the logic of the device. In the presence of a logical zero at the output Status block 241-24Nall FVI 11-1Non the respective inputs of the N-Vodolaga of the element OR NOT 5, a control unit 11 and the N-Vodolaga element AND-NOT 10 will be set to logical zeros. On the inverse of the output N-Vodolaga of the element OR NOT 5 will set the logic unit, which will go to the second entrance allowing Tregubova element And 6. On the inverse of the output N-Vodolaga element AND-NOT 10 will set the logic unit, which is supplied to the third input allowing Tregubova element And 6 and the exit Status of the device 20 of the device. This output allows Tregubova element And 6 remains a logical zero, defined by the presence of a logical zero at its first input is. The logical value at the output Status of the device 20 have the following meanings: a logical unit on the specified output indicates that the unit is ready for operation, and a logical zero, the device is busy. Logical zeros at the inputs of the Status block 241-24Nthe control unit 11 receives on the corresponding inverted inputs of the priority encoder 11.1. In accordance with the logic at the output of the priority encoder 11.1 set P-bit code corresponding to the number of the input with the highest priority from among the inverted inputs that have a logical zero (the lower the number the inverse log, the higher its priority). Next, the first group of inverters 11.21-11.2Pinverse code is converted into direct and to the input of the decoder 11.3. In accordance with the logic decoder 11.3 establishes a logical zero on one of its N inverted outputs, the number of which corresponds to code that is installed on the inputs of the decoder, while the rest inverted outputs of the decoder will be set logical unit. In order to ensure correct operation of the control unit outputdecoder 11.3 is not used, because in the situation when all FVI busy at all entrances Status block 241-24Nthe control unit 11 will be set to logical zeros, that is going to establish the output decoder 11.3 logical units. Signals with inverted outputs of the decoder are inverted second group of inverters 11.41-11.4N. Thus, one of the output Selection block 211-21N. the control unit 11, the number of which corresponds to the smallest number of free and ready to work FWI will be set logical unit, and all the other logical zero. In the initializing device logical unit will be established at the first output Selection block 211the control unit 11. Initializing device end with the installation at the entrance of Initializing device 15 logical zero, which translates into storage mode register storing the mask 9, and leads to the installation at the output of two-input element OR 1.6, FVI logical zero, which translates RS-trigger 1.2 FWI in the mode information storage. The initialization procedure of the device does not reset the registers for temporary storage 21-2Nand at the end of the specified registers is random information.

In the initial period, when subject to analysis of the BDI does not, on the bits of the first M-bit information input 12, to permit the inlet 13, the input of the Initialization device 15 is set to logical zeros. To the input of the frequency divider 8 through the first clock input 18 of the device from HV the community generator receives the clock pulses. On the K-bit input "time Code storage device 14 has a code that specifies the maximum time to keep a copy of the BDI in the device. Output "Resolution" 29 device is set to a logical zero. Output "device Status" 20 device logical unit. Clock pulses from the second clock output 19 of the frequency divider 8 is coming to corresponding inputs of all FVI 11-1N.

Upon receipt of the first to be analyzed keep vigil on the first M-bit information input device 12 are logical values corresponding to the values of bits DND. The time corresponding to the setting DND for the first M-bit information input device 12, figure 6 is designated as t1. From the first M-bit information input device 12 BDI comes to M-bit information inputs of registers for temporary storage 21-2Nthe first M-bit input block selection 31-3Nand M-bit input of the electronic key 7. In 3.3 Comparators each block selection 31-3Nthere is a comparison of significant bits of the received level with the information stored in the respective registers are temporary storage 21-2Nthat comes on the second M-bit information input 25 of the respective units of selection. The allocation of significant betonosmesitel in the first and second groups of input elements And 3.1 1-3.1M, 3.21-3.2Mblock selection 31-3Nbased on the bitmask coming to M-bit input Mask 17. In case of equality of the compared values at the output "a=b" of the comparator 3.3, respectively, and the output of "Preliminary result" 26 block selection 3 will set the logic unit, otherwise a logical zero. The flow of the logical values of the comparison results from outputs of "Preliminary result" 261-26Nblock selection 31-3Nthe inputs of the N-Vodolaga of the element OR NOT 5 subject to the relevant input elements And 41-4Nbased on the logical values of the outputs Status block 241-24NFWI 31-3N. In this case, if the output of "Status block" FBI has a logical zero, the result of the comparison obtained in the corresponding block selection, is considered invalid and should not affect the decision. Thus, outputs the Result of comparison 271-27Nall input elements And 41-4Nwill be a logical zero, as in the case under consideration (the receipt of the first level) outputs the Status of the block 241-24Nall FVI 11-1Ninstalled a logical zero. The value of a logical zero on the outputs the Result of comparison 271-27Nwill result in a moment of time and t 2(see Fig.6) to the formation of the output N-Vodolaga of the element OR NOT 5 the final result of the comparison significant bits of the received level information stored in each of registers for temporary storage 21-2N. In this case, the comparison result will be negative and the output N-Vodolaga of the element OR NOT 5 will be set logical unit. The time t2is defined as follows:

where ΔT3.1the time delay of the parallel operation of two-input elements And 3.11-3.1Mand 3.21-3.2M;

ΔT3.3the time delay of the parallel operation of the Comparators 3.3;

ΔT4.1the time delay of the parallel operation of two-input elements And 41-4N;

ΔT5- the response time N-Vodolaga of the element OR NOT 5.

The final decision about the possibility of passing the received level at the output of the device is made permissive trehochkovym element 6 when receiving at its first input the value of the logical unit enable input 13. To provide an objective decision about the possibility of passing the received level at the output of the logical unit's device to permit the entrance 13 of the device must be installed no earlier than time t2. Logical edit the Itza with the enabling input device 13 will be transferred to corresponding inputs of FVI 1 1-1Nand the first entrance allowing Tregubova element And 6. In this case, given the presence of logical units on the second and third inputs allow Tregubova element And 6, its output will be a logical unit, which will arrive on the release of "Resolution" 29 device inputs FVI 11-1Nand input "Resolution" 29 electronic key 7. A logical unit of output "Resolution" 29 device indicates permission to read BDI and the time t3defined as

where ΔT6the time delay allows Tregubova element And 6,

ΔT7.1the time delay of the parallel operation of two-input elements And 7.11-7.1M,

allow receipt of DND from the first M-bit information input device 12 on the third M-bit information output device 28. Thus, the reading level from the third M-bit information output device 28 is only possible after the appearance of the logical unit of output "Resolution" 29 and not the earlier time t3.

Simultaneously piped "Resolution" 29 FVI 11-1Nlogical unit initiates the recording process copies keep vigil in the register of temporary storage (for further comparison with the next incoming BDI) and the process for the ISI time code stored in the counter. The entry level is carried out in the register of temporary storage corresponding to the first free FBI. The first free FVI is determined by the control unit 11 by setting the input Selection block 21 corresponding to FBI logical units. In this mode of operation, the logical unit will be installed at the input Selection block 211FVI 11. The logical unit with the input Selection block 211and authorizing the entrance 13 FVI 11go to corresponding inputs of two-input element AND NOT 1.11 and form at its output a logical zero, which is supplied to the second input of the fourth two-input element And 1.10. This maintains the output Status block 241FVI 11the logic zero regardless of the state of the first input of the fourth two-input element And 1.10. In addition, a logical unit that is installed on permissive input 13 FVI 11goes to the first input of the second input element OR NOT 1.3, forming at its output a logical zero, which is supplied to the second input of the third two-input element And 1.4. At the output of the third two-input element And 1.4 regardless of the logic level at its first input will be a logical zero, which in the presence of a logic zero at the input of the Initialization 15 will provide a logical zero in the course of the two-element OR 1.6, accordingly, the input R of the RS-flip-flop 1.2. Logical unit to input "Resolution" 291at the same time a logical unit on the input Selection block 211leads to the formation of logical units on the output of the first input element And 1.1, which is fed to the input S of the RS-flip-flop 1.2, the first input of the first input element OR NOT 1.7 and exit "Setup" 22 FWY. A logical unit on the first input of two-input element OR NOT 1.7 generates at its output a logical zero, which, when inverted enable input write With counter 1.8, writes code with K-bit input Code storage time" 14 FBI in counter 1.8. At the inverse output overflowcounter 1.8 will be a logical unit, which will go to the second input of the second input element OR NOT 1.3 and in the future in the absence of logical units to permit the inlet 13 will maintain the output of two-input element OR NOT 1.3 logical zero. A logical unit at the input S of the RS-flip-flop 1.2 in the presence of a logical zero at its input R sets the output to RS-flip-flop logic unit, which allows the flow of clock pulses from the second clock input 19 to the counting input "+1" counter 1.8 through the second input element And 1.9 and simultaneously supplied to the first input included four is also input element And 1.10. A logical unit of output "Setting" 221FVI 11doing to the input of the initialization of the register of temporary storage 21provides an entry in his copy of DND.

To put the device in readiness to receive the next level, you need to permit the inlet 13 and the bits of the first M-bit information input device 12 to set the value of logical zero. Installing the logic zero at the permissive input device 13 and the logical values of the respective bits keep vigil on the first M-bit information input device 12, may be executed upon completion of the reading level from the third M-bit information output device 28, but not the earlier time t4defined as the sum of t3and maximum of:

the delay time of the logical unit in the RS-trigger FVI;

delay time when the recording copies of the BDI in the register of temporary storage;

the total time delay of the first input element OR NOT 1.7 and write counter 1.8.

Thus, the time t4defined:

where: ΔT1.2the time delay record in the RS-trigger 1.2,

ΔT2.1the delay register is temporary storage 2.1,

ΔT1.7the time delay of the first input element OR NOT 1.,

ΔT1.8the time delay of the write counter 1.8.

Upon installation, the logic zero at the permissive input device 13 indicated in Fig.6 as t5. A logical zero to a permission input device 13 is supplied to corresponding inputs of FVI 11-1Nand the first entrance allowing Tregubova element And 6. This output allows Tregubova element And 6 will be a logical zero, which goes to the output Resolution 29 of the device, the input of the electronic key 7 and inputs FVI 11-1N. The logic zero at the input of the electronic key 7 establishes a logical zero on all bits of the third M-bit information output device 28. A logical zero on permissive input 13 FVI 11received at the first input of the second input element OR NOT 1.3 and the first input of two-input element AND NOT 1.11. Due to the presence of a logical unit to a second input of the second input element OR NOT 1.3, at its output, and accordingly, the output of the third two-input element And 1.4 remains a logical zero. A logical zero at the first input of two-input element AND NOT 1.11 leads to the formation at its output a logical unit that is doing to the second input of the fourth two-input element And 1.10, ensures compliance with the logical values in the course of the fourth two-input element And 1.10 logical value at its first input. Thus, the logical unit for output RS-flip-flop 1.2 through fourth input element And 1.10 output Status block 241FBI. Logical unit with exit Status block 241FVI 11supplied to the second input of the corresponding input element And 41and the corresponding input of the control unit 11 and the N-Vodolaga element AND-NOT 10. A logical unit to a second input of two-input element And 41further authorizes the receipt of the comparison result stored copy of DND with newly arriving DND. A logical zero, the received input "Resolution" 29 FVI output allowing Tregubova element And 6, forms the output of the first input element And 1.1 logical zero, which translates RS-trigger 1.2 FWI 11and the appropriate register for temporary storage 21in the storage mode. In addition, a logical zero at the output of the first input element And 1.1 in the presence of a logic zero at the input of the Result of comparison 271FVI generates an inverted output of the first input element OR NOT 1.7 logical unit, which is supplied to an inverse input recording resolution With counter 1.8 and completes the recording time code storage. Logical unit received with exit Status block 2414FVI 11to the corresponding input of the control unit 11, initier the em procedure of choosing another free FBI. For time t6defined as:

where: ΔT1.11the time delay input element AND NOT 1.11,

ΔT1.10the time delay input element And 1.10,

ΔT11.1the time delay of the encoder priorities 11.1,

ΔT11.2the delay time of the inverter 11.2,

ΔT11.3the time delay of the decoder 11.3,

ΔT11.4the delay time of the inverter 11.4,

the output Selection block 212corresponding to the first free FVI 12will generate a logical unit, and the output Selection block 211corresponding to FVI 11- a logical zero, then the device is ready to receive the next level. Thus, another level can be set on the first M-bit information input device 12 no earlier than time t6.

When receiving subsequent DND operation of the device is as follows. Another DND is set on the first M-bit information input device 12 and the input block selection 31-3Nthat compares significant bits of the next level with saved copies of previously received and stored in the temporary storage registers is s 2 1-2NBDI. The results of the comparison in block selection 31-3Nare formed at the outputs of the respective input elements And 41-4Nas follows:

1) a logical zero at the output of two-input element And will be installed in two cases:

1.1) in the corresponding register of temporary storage is a copy of one of the previously received DND, but in the unit of selection is not detected coincidences significant bits of the received level with the stored copy (output "Preliminary results" of the corresponding block selection is set to logical zero, the output Status of the block corresponding to FBI logical unit);

1.2) in the appropriate register for temporary storage no information is available for comparison (output "Preliminary results" of the corresponding block selection is set logical one or a logical zero, and the output "Status block" appropriate FBI has a logical zero).

2) logical unit for output of two-input element And will be installed only in one case:

2.1) in the corresponding register of temporary storage is a copy of one of the previously received level and the block selection match all significant bits of the received level with the stored copy (output "Preliminary result" corresponding to the Loka selection set logical unit, on the exit Status of the block corresponding to FBI logical unit).

The results of the comparison with the outputs of two-input elements And 41-4Ngo to corresponding inputs of N-Vodolaga of the element OR NOT 5, the output of which is formed a logical unit only if for all inputs will be set to logical zero. This means there are no coincidences significant bits of the analyzed DND stored in registers temporarily store copies of the previous level. The logical value of the output N-Vodolaga of the element OR NOT 5 is supplied to the second input of allowing Tregubova element And 6, which after installation, the logical unit for allowing the input device 13 generates at its output a Boolean value that indicates whether the passage analyzed keep vigil on the output device. Forming the logical value at the output allowing Tregubova element And 6 is as follows:

1) logical unit output allowing Tregubova element And 6 will be generated if the logical unit for output "device Status" 20 N-Vodolaga element AND-NOT 10, the logical unit to permit entrance 13 and logical unit output N-Vodolaga of the element OR NOT 5;

2) a logical zero at the output allowing the Tr is ghodasara element And 6 will be formed in the presence of a logical zero on any of its inputs.

A Boolean value that is generated at the output allowing Tregubova element And 6 after installation to allow the input device 13 of the logic unit determines not only the passing of the analyzed keep vigil on the third M-bit information output device 28, and further the operation of the device associated with the processing of this level.

If allowing Tregubova element And 6 will be a logical unit, it will mean significant bits of the received level does not coincide with any one of the stored copies of the previous level and in accordance with the logic operation of the device the copy of the received BDI must be written to the first available register for temporary storage, which is determined by the control unit, and the counter corresponding to FBI should be recorded time code storage. The device for recording copies of DND and the setting time storage is carried out similarly to the above-described operation of the device upon receipt of the first level.

If allowing Tregubova element And 6 will be a logical zero, this will mean a significant coincidence of bits received BDI significant bits of one of the stored copies of the previous level. In this case, in accordance with the logic operation of the device analyzed DND should not be received by the output device, and the count of times the storage of the corresponding copies of the BDI should be started since the establishment of the repeat by overwriting code storage time in PWI, corresponding to the register for temporary storage, in which the match was found significant bits. When this operation is carried out as follows. Output "Resolution" 29 permitting Tregubova element And 6 remains a logical zero, which prevents the passage of newly admitted keep vigil on the third M-bit information output device 28. To permit entrance 13 all FVI 11-1Nset logical unit, which prohibits the reset 1.8 by blocking the receipt of the logic zero from the output of the overflow R counter 1.8 input of two-input element OR NOT 1.3 and simultaneously blocks the change in the logical value of the output "Status block" 24 FVI. While the input "comparisons" 27 FVI, corresponding to the case of temporary storage, in which the match was found significant bits will be set logical unit. A logical unit of input "comparisons" 27 this FVI is supplied to the second input of the first input element OR NOT 1.7, inverse output of which is formed a logical zero. A logical zero with the inverted output of the first input element OR NOT 1.7 is supplied to an inverse input recording resolution With counter 1.8, which leads to the entry in the 1.8 meter time code storage that is installed on the-bit input Code storage time" 14 FWY. The translation device in readiness for the reception of the next level is a logic zero to allow the input device 13. Installing the logic zero at the permissive input device 13 must be completed no earlier than time t4(see Fig.6).

After the time limit for storing one or more copies of the BDI, is their destruction by resetting the corresponding PVI and bring them into a state of readiness to receive the next level. Reset FVI possible only in the intervals of time when the enabling input 13 is set to logical zero, i.e. when the analysis of the BDI does not occur. After a storage time of up keep vigil in the counter 1.8 respective FVI overflow occurs. At the output overflowcounter 1.8 formed a logical zero, which is supplied to the second input of the second input element OR NOT 1.3 and subject to the availability of the logic zero at the permissive input 13 FVI generates the inverse of the output of two-input element OR NOT 1.3 logical unit. A logical unit on the inverse of the output of two-input element OR NOT 1.3 in conjunction with the logical unit for output RS-flip-flop 1.2 forms the output of the third two-input element And 1.4 logical unit, which is supplied to the reset input R of the counter 1.8 and vtoro the input of two-input element OR 1.6. A logical unit on the input R of the counter 1.8 performs a reset. A logical unit to a second input of two-input element OR 1.6 generates at its output a logical unit, which is fed to the input R of the RS-flip-flop 1.2. At the output of RS flip-flop 1.2 is formed a logical zero, so as to receipt at its input R logical units at its input S will be set to logical zero. A logical zero output RS-flip-flop 1.2 is supplied to the second input of the second input element And 1.9, the first input of the third two-input element And 1.4 and the first input of the fourth two-input element And 1.10. The logic zero at the second input of the second input element And 1.9 blocks the flow of clock pulses from the second clock input of FWI at the counting input of the counter 1.8. A logical zero at the first input of the third two-input element And 1.4 leads to the formation at its output a logical zero, which is fed to the input R of the counter 1.8 and through input element OR 1.6 to the input R of the RS-flip-flop 1.2. A logical zero input R of the RS-flip-flop 1.2 together with a logical zero at its S input translates RS-trigger 1.2 mode of information storage. A logical zero at the first input of the fourth two-input element And 1.10 leads to unconditional formation at its output, respectively, and output the status of the block 24 FVI logical zero. The log is static with zero exit Status block 24 FBI went to a corresponding input of the control unit 11.

During operation of the device may be a situation in which all registers are temporary storage 21-2Nwill be used to store copies of previously submitted DND. This outputs the Status of the block 241-24Nall FVI 11-1Nwill be set logical unit, which will lead to the formation of the inverted output N-Vodolaga element AND-NOT 10 logical zero. A logical zero with inverted output N-Vodolaga element AND-NOT 10 arrives at the third entrance allowing Tregubova element And 6 and the exit Status of the device 20 of the device. A logical zero on the third entrance allowing Tregubova element And 6 will lead to unconditional formation at its output, and accordingly, the output of "Resolution" 29 logical zero, which in turn blocks the passage of newly admitted keep vigil on the third M-bit information output device 28 via an electronic key 7. The value of logical zero at the output Status of the device 20 will mean that the device is busy and not ready to receive the next level, and a value of logical zero at the output of "Resolution" 29 device - the absence of the third M-bit information output device 28 information to read. Thus, blocking the passage of new entrants keep vigil on the third M-bit information Vyhod device will continue until the expiration of the storage time for one or more stored copies of DND. Thus, the operation of the device depends on the variations of its use.

The first option of using the device is that the next level is not served on the first M-bit information input device 12 to change the value of the output "device Status" 20 devices. The formation of the inverted output N-Vodolaga element AND-NOT 10, and accordingly, the output "device Status" 20 logical unit occurs after the expiration of the storage time of one or more copies of the BDI in registers for temporary storage and reset the corresponding PVI.

The second option of using the device is that the next level is served on the first M-bit information input device 12 (together with the change in input value 13). In this case, each newly arriving DND on the output device is not passed, but is a comparison of the significant bits with the stored level in the case of a positive result overwrites the time code stored in the corresponding PVI.

Thus, the proposed device performs the following functions to control the incoming BDI:

allows admission to the output of the first level;

saves a copy of the BDI in a specified period of time, store a copy of the DND and allows you to change the time keep a copy of the BDI during device operation;

p is inimal decision to apply to the output device the next level according to the comparison result of its significant bits with the corresponding bits of the stored copies of DND;

saves the position of the significant bits and allows dynamic change during device operation;

off disables the DND next to the output device after filling in all the registers for temporary storage device.

1. Device information containing N shapers time intervals, where N≥1, N units of selection, the frequency divider, the input of which is clocked by the input device, wherein the inputs of N registers for temporary storage, the N input elements And permitting trekhgolovy element And N-shadowy the element OR NOT, electronic key, the register storing a mask, N-shadowy element AND IS NOT, the control unit, and the output of the frequency divider is connected to a clock input shapers time intervals, the corresponding bits of the K-bit input Code storage time", where≥1 - bit time code storage, shapers time intervals are interconnected and are the corresponding bits of the K-bit input Code time storage devices, enabling inputs N shapers time intervals and the first entrance allowing Tregubova element And connected with each other and are permissive input of the corresponding bits of M-bit information inputs, where M≥1 - quantity DV is ary digits of the analyzed block information, N registers for temporary storage, N units of selection and the electronic key are interconnected and are the corresponding bits of the first M-bit information input device that inputs the Initialization N shapers time intervals and the storage register masks are interconnected and are input device initialization exit allowing Tregubova element And is connected to the input "Enable" shapers of time intervals, an electronic key and is the output Resolution of the device, the i-th output Selection block, where i=1, 2...N, a control unit connected to the input Selection block i th shaper time intervals, the output of the i-th input element And is connected to the i-th entry of the N-Vodolaga of the element OR NOT and entry the result of the comparison of the i-th imaging unit time intervals, the output of the "Installation" of the i-th imaging unit time intervals connected with input "Setting" of the i-th register of temporary storage, the exit Status block the i-th imaging unit time intervals connected with a second input of the i-th input element And the i-th input of the control unit and the i-th entry of the N-Vodolaga element And-NO, exit N-Vodolaga item AND IS NOT connected to the third input allowing Tregubova element And is output "device Status" device, bits M-bit input "setting the mask register is stored the I mask are the corresponding bits of M-bit input "set mask" device, and the bits M-bit output of the register storing the mask connected to the corresponding bits of M-bit input Mask N block selection, M-bit output of the i-th register of temporary storage is connected to the second M-bit information input of the i-th block selection, "Preliminary results" of the i-th block selection connected to the first input of the i-th input element And the output N-Vodolaga item OR IS NOT connected to the second input allowing Tregubova element And a M-bit information output electronic key is M-bit information output device.

2. The device according to claim 1, characterized in that the imaging unit time intervals is comprised of first, second, third and fourth two-input elements And the first and second input elements OR NOT, two-element AND-NOT two-element OR RS-flip-flop, counter, while the K-bit counter input is a K-bit input Code storage time" of the shaper, the first input of the first input element And is connected to the second input of two-input element AND IS NOT and is the input Selection block shaper, the second input of the first input element And an entry "Resolution" of the shaper, the output of the first input element And is connected to the S input of RS flip-flop, the first input of the first two the running of the element OR NOT and is the output of the Installation of the driver, the second input of the first input element OR NOT an entrance "comparisons" shaper, the output of the first input element OR IS NOT connected with an inverted installation counter input, the first input of two-input element OR an input of the Initialization of the shaper, the output of two-input element OR connected to the R input of RS flip-flop, the output of which is connected to the first input of the third two-input element And the second input of the second input element And the first input of the fourth two-input element And whose output is the output of "Status block" shaper, the first input of the second input element is a clock input of the shaper the output of the second input element And is connected to the counting input of the counter, inverted output overflow which is connected to a second input of the second input element OR NOT, the output of which is connected to a second input of the third two-input element And the output of which is connected to the reset input of the counter and a second input of two-input element OR the output of two-input element AND is connected to a second input of the fourth two-input And gates and the first input of the second input element OR IS NOT connected to the first input of two-input element AND IS NOT and is permissive input of the shaper.

3. The device according to claim 1, distinguished by the Eesa fact, the block selection consists of the first and second groups of input elements And M elements in each group and the comparator, the first input of the j-th input element And the first group of input elements And, where j=1, 2...M, is the j-th digit of the first M-bit information input unit selection, the first input of the j-th input element And the second group of input elements And is the j-th digit of the second M-bit information input unit selection, the second input of the j-th input element And the first group of input elements And connected to a second input of the j-th input element And the second group of input elements And is the j-th category of the M-bit input Mask block selection, the output of the j-th input element And the first group of input elements And connected to the j-input of the first group of information inputs of the comparator, the output of the j-th input element And the second group of input elements And connected to the j-input of the second group of information inputs of the comparator, and the output of the equality comparator is the output of "Preliminary result" unit of selection.

4. The device according to claim 1, wherein the electronic key comprises M input elements And the first input of the j-th input element And where j=1, 2...M is j-m discharge M-Izryadnova information input electronic key, the second inputs of two-input elements And are interconnected and are the input "Enable" electronic key, the output of the j-th input element And is the j-th category of M-bit information output electronic key.

5. The device according to claim 1, characterized in that the control unit consists of an encoder of priorities, the first group of inverters of the P inverter, wherethe second group of N inverters inverters, decoder, while the i-th inverted input encoder priorities is the i-th entry Status block control unit, the k-th inverted output of the priority encoder, where k=1, 2...P, is connected to the input of the k-th inverter of the first group of inverters, the output of which is connected to the k-th input of the decoder, the i-th inverted output of which is connected to the input of the first inverter of the second group of inverters, and the output of which is the i-th output Selection block of the control unit.



 

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2 cl, 3 dwg, 1 apl

FIELD: digital data processing using electrical devices; informational search means and database structures; foreign language learning.

SUBSTANCE: electronic documents data is entered into the computer. Electronic documents objects to be searched in informational system are discovered. Electronic documents objects to be searched in informational system are compared to informational system database objects. Electronic documents data is transformed by marking objects of electronic documents. Electronic documents with marked electronic documents data objects are visualized. Before entering electronic documents data into the computer data objects to be searched in informational system are entered, data objects to be searched in informational system are compared to informational system database data objects and buffer database of data objects is formed. Comparison of electronic documents objects to be searched in informational system is done with data objects in buffer database of data objects.

EFFECT: creation of effective method for searching and marking of information data, that is to implement the learning function "learned repetition", which is based on individual approach to learning.

18 cl

FIELD: distribution devices, terminal devices.

SUBSTANCE: in distribution device groups of two or more informational products which represent digital informational content are stored with information about policy administration which indicates user's rights to this group by interrelated method. Distribution device transfers the user requested informational content from group to the terminal device with license certificate (LC), refreshes information about policy administration decreasing policy validity. On return of the renewed LC distribution device increases the decreased policy validity taking into account the part of policy validity which is indicated in the renewed LC. On user's demand distribution device again transfers LC or other digital informational content.

EFFECT: distribution of digital content for a more complete satisfaction of user's demand.

22 cl, 58 dwg

FIELD: data access technologies.

SUBSTANCE: method includes assignment of simplified network address, recording URL and converting numbers into storage system with net access, inputting assigned number into computer, transferring inputted number to storage system, converting number to URL, receiving page matching URL, and displaying it. Method for use in operation systems for message transfer include intercepting system level messages to certain objects and forming pseudonym messages during that. Systems realize said methods.

EFFECT: broader functional capabilities.

12 cl, 30 dwg

FIELD: computers.

SUBSTANCE: system has entries memory block, words memory block, control block, substitutions block, n blocks for searching and replacing.

EFFECT: broader functional capabilities.

17 dwg

FIELD: computers.

SUBSTANCE: system has nine registers, four address selectors, triggers, AND elements, OR elements and delay elements.

EFFECT: higher speed.

8 dwg

FIELD: computers.

SUBSTANCE: system has operation mode setting block, first and second blocks for selecting records addresses, block for forming addresses for reading records, data output block, first and second record codes comparison blocks, records quality comparison block, year intervals comparison block, records selection control block, register, adder and OR elements.

EFFECT: higher speed of operation.

10 dwg

FIELD: computers.

SUBSTANCE: system has memory for programs, including browser, display block, database for storing documents, addressing control block, while each document of base has at least one link with indicator of its unique number and indicator with address of program for control stored in addressing control block, system contains also, connected by data buses and control of other blocks of system, memory for links of couples of unique numbers of links and forming means for lists of unique numbers of documents links, which are interconnected.

EFFECT: higher efficiency.

2 cl, 1 dwg

FIELD: telecommunication networks.

SUBSTANCE: messages, sent by cell phones, are formed by means of printed and public-distributed classifier, wherein at least one category is made with possible detection of at least one identifier of individual mark of object, identifier is sent by sender via at least one message to computer server with software, which transfers such message into database record at server for its transfer to at least one receiver, or searches for such record in database at server in accordance to received message and transfers to sender of such message at least one found database record.

EFFECT: broader functional capabilities.

2 dwg

FIELD: web technologies.

SUBSTANCE: method for integration of printed business documents, requiring original signature, with electronic data concerning these documents and later extraction of data, inputted for forming documents, is characterized by steps for forcing end user or agent to input all necessary data for forming of required document, saving collected data in database, linking saved data to unique ID code and printing unique ID code on printed document during printing. Printed documents is signed by end user and sent together with supporting documentation. When document is received by business-client, business-client inputs ID code, which is then used for access to saved data, and updates private database of business-client with all data, used for creation of original documents.

EFFECT: higher efficiency.

2 cl, 7 dwg

FIELD: computer science.

SUBSTANCE: device has string memory block, comparator, memory block for words and substitutes, block for analysis and forming of displacement results, block for storing string address, control block.

EFFECT: broader functional capabilities, higher reliability.

10 dwg

FIELD: data bases.

SUBSTANCE: method includes presenting operations at all levels of company in form typical product life cycle tree, wherein existing objective functional-technological connections of each manufacture stage are decomposed, and forming information system in form of pertinent-relevant complex information system and search, for which typical structure-information modules of information system are formed, system objective information requirements of data consumers, being a result of decompositions by levels of operations and problems, are determined as precisely as possible, data base of found documents in form of files is formed of key nodes with set of elementary data block for each system information requirement and files of information system modules, starting from lower levels of current stage and then upwards, while each data block has a list of pertinent documents ordered by determined information requirements.

EFFECT: higher search efficiency.

13 cl, 11 dwg

FIELD: computer science.

SUBSTANCE: system has first, second, third, fourth and fifth registers, first and second memory blocks, first, second and third decoders, triggers, elements AND, OR and delay elements.

EFFECT: higher speed of operation.

1 dwg

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