Automated system for collecting and processing electronic polls data of gas "election"

FIELD: computer engineering, automated system for collecting and processing electronic polls data.

SUBSTANCE: system consists of input messages receiving unit, data from server database receiving unit, election committee identification unit, first and second units for candidates base addresses identification, polls results disclosure time cycles selection unit, polls results recording time cycles selection unit, input messages receiving time cycles selection unit, database read and write signals forming unit, final polls results data forming unit.

EFFECT: increased system performance due to database entries address localization using receiving messages identifiers and forming of progressive total of polls results in real-time.

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The invention relates to computer technology, in particular to the automated system of data collection and processing e-voting state automated system (GUS) "ELECTION", which represents a geographically distributed system, the organizational structure is determined by the electoral system of the Russian Federation and corresponds to the structure of election commissions.

System objects are equipped with automation systems, forming a four-level hierarchical structure, aimed at the implementation of new information and electoral technologies applied in the development of this system.

The upper (first) tier of the system is an automation system (hereinafter - KSA) the Central electoral system of the Russian Federation, the second level system - KSA election commissions of subjects of the Russian Federation, the third level - KSA district election commissions, the fourth level - KSA territorial election commissions. The development system provides further automation of precinct election commissions and the creation of KSA fifth level - KSA precinct election Commission.

KSA all levels consist of technical, software and information support are combined in the information and the communications network using public and commercial channels, networks and data communications.

The system should provide the solution of complex functional tasks, including the task of tabulation in all the subjects of the Russian Federation, the peculiarity of which consists in that after the completion of voting at polling stations and tabulation of the territorial election commissions of subjects of the Russian Federation (RF), automated system for the collection and processing of electronic voting could ensure in the shortest possible time collection and automatic processing totals vote in all constituent entities of the Russian Federation with the issuance of the final results of voting for each candidate

Known systems that could be used to solve the task [1, 2].

The first of the known systems contains blocks receiving and storing data, connected to the control blocks and data blocks search and selection, connected to the blocks of the data storage and display, the clock inputs are connected to outputs of control unit [1].

A significant disadvantage of this system consists in the impossibility of solving the problem operational update of data stored in memory in the form of relevant documents in real time.

Known and other si the subject, containing telecommunication network blocks data processing, information inputs which are connected with the blocks receive data and control outputs connected to the first group of blocks of memory, Central processor, the inputs of which are connected to the outputs of the memory blocks of the first group and block data, and outputs connected to inputs of memory blocks of the second group and block data display [2].

The last of the above technical solutions closest to being described.

Its disadvantage is the low system performance, due to the fact that the procedure of updating the data collected by the system from the distributed object system for a telecommunication network, a data transfer is realized through the process of their search in the whole volume of the system database and then processing the updated data by the Central processor, that when large amounts of data of the database system inevitably leads to higher costs time.

The purpose of the invention is the improvement of the system performance by localization of address records database identifiers received by the messaging system and the formation of the growing up of the voting results in real time

This objective is achieved in that in the known system, the soda the containing block receiving an input message, information and clock inputs of which are the first information and the clock inputs of the system, and the first information output is the first information output system, the information input unit receiving an input message is intended for reception patterns from electoral commissions, the clock input unit receiving an input message is intended for the reception of the synchronizing signal recording patterns of electoral commissions in the block receiving the input message, and the first information output unit receiving the input message is intended for generation of patterns of electoral commissions on the information input server unit receiving records database servers, data and clock inputs of which are the second information and the clock inputs of the system, when this information input unit receiving records database server is designed to receive the records of the database server, and the clock input unit receiving records database server is designed to receive a synchronizing signal adding records server database in block receiving records database of the server block data summary of the voting results, one data input connected to the output unit receiving records of the database server, the other is the information input unit data summary of the voting results is connected to the second output unit receiving an input message, and the output of block data summary of the voting results is the second information output system, the signal read and write data output of which is the address of the system output, and one clock output signal read and write the database is the first clock output system, wherein the system contains the block identification electoral commissions, the information input connected to the third information output unit receiving an input message, the clock input of the identification block of the electoral commissions is connected to the first clock input of the system, the information output unit identification electoral commissions connected with the first information input unit a signal read-write database, and synchronizes the output of block identification of the electoral commissions is the second synchronizing system output, the first identification block of the reference addresses of the candidates, an information input connected to the fourth output unit receiving an input message, and the clock input is connected to the synchronizing output of the identification block of election commissions, the data output of the first block identification and the reference addresses of the candidates is connected with the second information input of the signal read-write database, and the clock input of the first identification block of the reference addresses of the candidates is connected to the first clock input signal read-write database, the second identification block of the reference addresses of the candidates, the information output of which is connected with the third information input of the signal read-write database, and synchronizes the output of the second identification block of the reference addresses of the candidates is connected to the second clock input signal read-write database, the unit of selection cycles in time record of voting results, the input of which is connected with the second clock input system, the first output of the block selection time cycles record the results of voting is connected to the clock input block data summary of results of voting, the second output of the block selection time cycles record of voting results is the third synchronizing system output and the third output block selection time cycles record of voting results is connected with the mounting unit identification electoral commissions, the block selection cycles in time of reception of the input message, the input of which is connected to the third output block selection time writes the result is the ATA voting and one output unit of selection cycles in time of reception of the input message is the first signal output of the system, and the block selection time cycles of the results of voting, one input of which is connected to another output of the block selection cycles in time of reception of the input messages, the other input of the block selection time cycles of the results of voting is connected to the second clock output signal of the read and write databases, information output unit selection time cycles issuance of voting results is connected with the information input of the second identification block of the reference addresses of the candidates, which synchronizes the output of the block selection time cycles of the results of voting is connected to the clock input of the second unit identification reference addresses of candidates, and the signal output unit selection time cycles of the results of voting is the second signal output of the system.

The invention is illustrated by drawings, where figure 1 shows the block diagram of the system, figure 2 presents an example of a specific structural embodiment of the identification block of election commissions, figure 3 - example of a specific structural embodiment of the first identification block of the reference addresses of the candidates figure 4 - example con the specific structural embodiment of the second identification block of the reference addresses of the candidates, figure 5 - example of a specific structural embodiment of the block selection time cycles issuance of voting results, figure 6 - example of a specific structural embodiment of the block selection time cycles record of voting results, figure 7 - example of a specific structural embodiment of the block selection cycles in time of reception of the input message, Fig is an example of a specific structural embodiment of the signal read-write database, figure 9 shows a typical structure of a distributed election commissions of gas "Vybory".

The system (figure 1) contains the unit 1 receiving the input message block 2 admission records of the database server, block 3 identification of election commissions, the first 4 and second 5 blocks identify the reference addresses of candidates, the unit 6 selection of the timing cycles of the results of voting, block 7 breeding cycles in time record of voting results, block 8 breeding cycles in time of reception of the input message block 9 of the signal read-write database, block 10 data summary of the voting results.

Figure 1 shows the first 21 and second 22 information input system, the first 23 and second 24 clock inputs of the system, the first 25 and second 26 information system outputs, address 28 output system the volumes, and the first 29 and second 30 and third 31 synchronizing the system outputs, the first 32 and second 33 signal outputs of the system.

Block 1 receive input messages from election commissions, made in the form of the register with the information input 21, the clock input 23, and the first 12, second 13, 14 third and fourth 15 information outputs.

Unit 2 admission records of the database server in the form of register with the information input 22, the clock input 24, and information output.

Unit 3 identification of election commissions (2) contains a decoder 40, block 41 memory, made in the form of a persistent storage device, the counter 42, the trigger 43, item 44 OR elements 45-49 And elements 50-52 delay.

The drawing shows information 53, the clock 54 and installation 55 inputs, as well as information 57 and clock 58 outputs.

The first block of 4 identification of the reference addresses of the candidates (figure 3) contains the decoder 60, block 61 memory, made in the form of a persistent storage device, the register 62, the elements 63-65 And the elements 66, 67 delay.

The drawing shows information 68 and the clock 69 inputs, as well as information 70 and the clock 71 outputs.

The second block 5 identification of sample addresses candidates (figure 4) contains the decoder 80, block 81 memory, the imp is United in the form of a persistent storage device, elements 82-84 And elements 85-1, 85-2 delay, the register 86.

The drawing shows information 87 and clock 88 inputs, as well as information 89 and synchronizing 90 outputs.

Unit 6 selection of temporal cycles issuance of voting results (figure 5) contains a counter 91, the register 92, a comparator 93, element 94 and the element 95 delay.

The drawing shows the first 97 and 98 second clock inputs, as well as information 99, the first 100 and second 118 clock outputs.

Unit 7 breeding cycles in time record of voting results (6) contains a counter 101, a register 102, a comparator 103, and the elements 104, 105 delay.

The drawing shows the clock 106 entrance, as well as the first 107 and second 108 and 109 third clock outputs.

Unit 8 breeding cycles in time of reception of the input message (7) contains a counter 111, a register 112, a comparator 113 and the delay element 114.

The drawing shows the clock 115 entrance, as well as the first 116 and second 117 outputs.

Unit 9 signal read and write database (Fig) contains triggers 120-121, group 122-124 elements And group 125 elements OR element 126 OR elements 127, 128 delay.

The drawing shows information 130-132, clock 133-134 and installation 135 inputs, as well as information 28 output, the first 29 and second 136 clock outputs.

The block 10 is of formirovaniya totals of the voting results in the form of adder, having the first 137 and second 138 information and synchronization 139 inputs and information 26 output.

All nodes and elements of the system are made on the standard of potentially switching elements. To simplify the circuit drawing of the initial installation of assemblies and units of the system to its original state is not shown.

This system equipped with election commissions of all levels of the hierarchy with the exception of precinct election commissions that control elections act as sources of data on the number of voters who participated in voting for a certain time, and the number of votes cast for the respective candidates.

When solving the problem of collecting and processing data on the electronic voting results information input 21 system transmission path of data sequentially received messages (codogram) of Election commissions of subjects of the Russian Federation on the voting of the voters in the respective subjects of the Russian Federation in the form of the final file with the following entries:

The record number in the messageThe ID of the election Commission of subject of the Russian FederationThe identity of the applicant in the form of the initial Boo is in his name, nameThe TOTAL number of votes cast for this candidate
The first recordIdentification number IRCandidate No. 1K1
The second entryCandidate No. 2K2
...............................................................
The last entryThe candidate AGAINST ALLKPV

The first record of codogram with information input 21 of the system is recorded in the register of unit 1 clock pulse input 23, which passes on the clock input of the register block 1.

With the release of 12 all contents of register block 1 available at the output 25 of the system for subsequent documentation of records in the database system.

Output 14 of block 1 the identifier of the election Commission of subject of the Russian Federation to the input 53 of the block 3 and then fed to the input of the decoder 40, which decrypts the ID code of the electoral Commission, and opens one of the items 45-47 And one input.

For definiteness, suppose that a high potential is received at one input element 45 I.

At this time, the clock pulse from the input 23 of the system arrives at the I the d 54 unit 3 and further to the inputs of the elements 48 and 49 I. To this point in time, the trigger 43 is in original condition and in its inverted output is high potential, the opening element 48 And to one input. As a result of this clock pulse from the input 23 of the system passes through the element 48 And the delay element 50 at the time of the reception code input message in block 1 and the operation of the decoder 40 and enters the status of items 45-47 I.

Given the fact that open on one input will be only element 45 And then passing this element And the sync pulse arrives, firstly, to the input of the read fixed memory permanent storage device 41, which stores the base address of the memory cell in the database server assigned to the given election Commission, and reads it to the input of counter 42.

In addition, the same pulse code read base address of the election Commission with the output element 50 is delayed by element 51 at the time of reading the contents of a fixed cell ROM and supplied to the clock input of the counter 42, locking it the base address of the memory cell assigned to the given election Commission.

Code output from the counter 42 through the output 57 of the block 3 is given to the input 130 of the block 9, and then supplied to one input elements 122 And groups, on the other inputs to this point in time with the inverse of the outputs of the trigger 120 and 121 serves high potentials since both triggers are in the initial state. The code base address through the elements 122 And group via elements 125 OR group is given the address output 28 of the system.

In parallel, the pulse reading from the output element 51 passes through the element 44, OR, then delayed element 52 at the time of adding the base address of the electoral Commission in the counter 42 and forth, first, with the output element 52 delays are issued for a single input trigger 43, setting it in one state, in which the element 49 And will be opened and the element 48 And is closed, and, secondly, from the output 58 of the block 3 it is issued at the output 31 of the system and further to the input of the first interrupt server (not shown).

On this signal, the server goes to the subroutine of the document the first record of codogram from the output 25 of the system at the base address of the electoral Commission, which is output from the counter 42 is issued for the address 28 the system output.

In parallel with the process of documenting the first record in the database system, the same clock pulse recording output 58 unit 3 is fed to the input 69 of the block 4, the information input 68 which enters code candidate ID of the first record from the output 15 of block 1. The received code is decoded by decoder 60 and opens to one input of one of the elements 63-65 I.

For definiteness, olaim, the high potential received at one input element 63 I.

At the same time the clock pulse input 69 unit 4 is supplied to poll the status of the elements 63-65 I. Considering the fact that open on one input will be only element 63 And, after this item, the sync pulse arrives, firstly, to the input of the read fixed memory permanent storage device 61, which stores the address of the memory cell in the database server, assigned to the applicant, and reads its contents to the information input of the register 62.

Secondly, the same pulse code read address of the memory cell in the database server assigned to the first candidate delay element 66 delay time read the contents of a fixed cell ROM, is fed to the clock input of register 62, locking it the address of the memory locations assigned to the first candidate from the first record of the input message. Code from the output of the register 62 through the output 70 of the block 4 is fed to the input 131 of the block 9 and further to one input elements 123 And group 123, on the other inputs of which are served potentials with direct access to the trigger 120 and the inverted output of the trigger 121.

In parallel with this process the sync pulse from the output element 66 unit 4 delayed element 67 at the time of entering the address of the memory, keeping the Noi for the first candidate from the first record of the input message register 62, and then exit 71 unit 4 is fed to the input 133 unit 9, from whence he is, first, immediately goes to the direct input of the trigger 120, setting it in one state, in which a high potential with direct access to the trigger 120 opens the elements 123 and groups, And low potential with inverted output trigger 120 closes the elements 122 group I.

Thus, the elements 123 And the group will be open, because their inputs go high potentials with direct access to the trigger 120 and the inverted output of the trigger 121. Thanks to this address code memory cells assigned to the first candidate from the first record in the input message passes through the elements 123 And groups and elements 125 OR group address output 28 of the system.

Secondly, at about the same time the clock pulse input 133 is delayed element 126 at the time of the trigger 120 and outputting a code address memory cell assigned to the first candidate from the first record of the input message to the address output 28, and then through the exit 29 of the system is given to the input of the second channel interrupt server (not shown).

On this signal, the server goes to the subroutine to read the contents of the memory cells assigned to the first candidate from the first record in the input message, which stores the number of votes cast this ka is the candidate.

The contents of the address of the memory assigned to the first candidate from the first record in the input message is read from the database server and information through the entrance 22 of the system is supplied to the information input of the register block 2, where it is recorded synchronizing pulse server received at the clock input 24 of the system.

In addition, the clock pulse from the output element 127 is delayed element 128 at the time of reading the contents of a memory cell and is supplied on the installation log trigger 120, returning it to its original condition in which it has high potential with inverted output reopens elements 122 And groups connecting the output of the counter 42 unit 3 to the address output 28 of the system.

Note that before you begin system all its nodes and blocks were set in the initial state, and the contents of the memory cells of the database server allocated to each of the candidates was set to zero. Therefore, when reading the content of the memory cell of the database assigned to the first candidate on the input of the register block 2 will read zero code, and, therefore, the register block 2 will remain in its original state.

The contents of register block 2 (in this case it is zero) is fed to the input 138 of the block 10, is made in the form of an adder. To another input of the adder 137 10 output Belka 1 filed code of the number of voters who gave their votes for a particular candidate.

Simultaneously, the clock pulse server sign-24 system is fed to the input 106 of the block 7, which is delayed by element 104 at the time of entering code in the register of unit 2 and then fed to the clock input of the comparator 103 unit 7, the information inputs which are served codes from outputs of the counter 101 and the register 102.

Simultaneously, the pulse from the output 107 of the comparator 103 is delayed by the delay element 105 at the time of actuation of the adder 10 and first output 108 of the block 7 available at the output 32 of the system and further to the input of the third channel interrupt server. On this signal, the server goes to the subroutine record number of voters from the output 26 of the system to the address of the memory locations assigned to the first candidate with the address of the exit 28 of the system, and the signal on the reception of the next record from the input codogram (not shown).

Secondly, the same pulse from the output of the delay element 105 is supplied to the counting input of the counter 101, fixing the fact of recording the number of votes for the first candidate in the database system.

The signal reception of the next record from the input codogram containing information on the number of voters who voted for the second member, with the input 21 is again sent to the information input of the register block 1, where it is logged sin is toniziruushii pulse input 23.

The next entry codogram with information input 21 of the system is recorded in the register of unit 1 clock pulse input 23, which passes on the clock input of the register block 1.

With the release of 12 all contents of register block 1 again available at the output 25 of the system for subsequent documentation of records in the database system.

In contrast to the reception mode, the first write clock pulse from the input 23 of the system through the inlet 54 unit 3 passes through the element 48, And through the element 49 And, since this point in time, the trigger 43 is in a single state and its direct output will be high potential, the opening element 49 And one entrance. As a result of this clock pulse input 54 unit 3 passes through the element 49 And immediately fed to the counting input of the counter 42, by adding to the base address of the memory cell assigned to the given election Commission, unit, and thereby, forming another address for documenting the second record from the input codogram.

Code output from the counter 42 through the output 57 of the block 3 is given to the input 130 of the block 9, and then supplied to one input elements 122 And groups, on the other inputs to this point in time with the inverted outputs of the trigger 120 and 121 serves high potentials, since both triggers are in the initial state. Code base Adra is and through the elements 122 And group via elements 125 OR group is given the address output 28 of the system.

In parallel, the pulse reading from the output element 51 passes through the element 44, OR, then delayed element 52 during operation of the counter 42 and forth, first, with the output element 52 delay is again sent to a single input trigger 43, confirming its isolated state in which the element 49 And will remain open, and the element 48 And is closed, and, secondly, from the output 58 of the block 3 it is issued at the output 31 of the system and then again fed to the input of the first interrupt server (not shown).

On this signal, the server goes to the subroutine documentation next record codogram from the output 25 of the system on the next address, which is output from the counter 42 is issued for the address 28 the system output.

In parallel with the process of documenting the next entry in the database system, the same clock pulse recording from the output 58 of the block 3 is again fed to the input 69 of the block 4, the information input 68 which receives ID code of the candidate next record from the output 15 of block 1. The received code is decoded by decoder 60 and opens to one input of one of the elements 63 and 65 I.

For definiteness, suppose that a high potential is received at one input element 64 I.

At the same time the clock pulse input 69 unit 4 is supplied to poll the status of the elements 63-65 And. Teach what they the fact, what is open on one input will be only element 64 And, after this item, the sync pulse arrives, firstly, to the input of the read fixed memory permanent storage device 61, which stores the address of the memory cell in the database server reserved for another candidate, and reads its contents to the information input of the register 62.

Secondly, the same pulse code read address of the memory cell in the database server reserved for another candidate, delay element 66 delay time read the contents of a fixed cell ROM, is fed to the clock input of register 62, locking it the address of a memory location reserved for a candidate from the next record in the input message. Code from the output of the register 62 through the output 70 of the block 4 is fed to the input 131 of the block 9 and further to one input elements 123 And group 123, on the other inputs of which are served potentials with direct access to the trigger 120 and the inverted output of the trigger 121.

In parallel with this process the sync pulse from the output element 66 unit 4 delayed element 67 at the time of entering the address of the memory assigned to the first candidate from the first record of the input message register 62, and then exit 71 unit 4 is fed to the input 133 unit 9, from whence he is, first, immediately comes to direct entry trigger is 120, setting it in one state, in which a high potential with direct access to the trigger 120 opens the elements 123 and groups, And low potential with inverted output trigger 120 closes the elements 122 group I.

Thus, the elements 123 And the group will be open, because their inputs go high potentials with direct access to the trigger 120 and the inverted output of the trigger 121. Thanks to this address code memory cell assigned to the candidate from the next record in the input message passes through the elements 123 And groups and elements 125 OR group address output 28 of the system.

Secondly, at about the same time the clock pulse input 133 is delayed element 126 at the time of the trigger 120 and outputting a code address memory cell assigned to the candidate from the next record in the input message, the address output of the system, and then through the exit 29 of the system is given to the input of the second channel interrupt server (not shown).

On this signal, the server goes to the subroutine to read the contents of a memory location reserved for a candidate from the next record in the input message, which stores the number of votes given to the candidate.

The contents of the address of the memory assigned to the candidate from the next record in the input message, reads the I from the database server and information through the entrance 22 of the system is supplied to the information input of the register block 2, where it is recorded synchronizing pulse server received at the clock input 24 of the system.

In addition, the clock pulse from the output element 126 of the block 9 is delayed element 129 at the time of reading the contents of a memory cell and is supplied on the installation log trigger 120, returning it to its original condition in which it has high potential with inverted output reopens elements 122 And group re-connecting the output of the counter 42 unit 3 to the address output 28 of the system.

The contents of register block 2 (in this case, it is also zero) is fed to the input 138 of the block 10, is made in the form of an adder. To another input of the adder 137 10 output 13 of the block 1 filed code of the number of voters who voted for another candidate.

Simultaneously, the clock pulse server sign-24 system is fed to the input 106 of the block 7, which is delayed by element 104 at the time of entering code in the register of unit 2 and then fed to the clock input of the comparator 103 unit 7, the information inputs which are served codes from outputs of the counter 101 and the register 102.

Given that this time, the counter 103 will be still less than the number of candidates in the register 102, the output 107 of the comparator 103 is formed impulse, which is supplied to the clock input 139 of the adder 10, which fix the positions, the number of voters who voted for that candidate, and outputs the result to the output 26 of the system.

Simultaneously, the pulse output 107 is delayed by the delay element 105 at the time of actuation of the adder 10 and first output 108 of the block 7 available at the output 32 of the system and further to the input of the third channel interrupt server. On this signal, the server goes to the subroutine record number of voters from the output 26 of the system to the address of the memory locations assigned to the first candidate with the address of the exit 28 of the system, and the signal on the reception of the next record from the input codogram (not shown).

Secondly, the same pulse from the output of the delay element 105 is supplied to the counting input of the counter 101, fixing the fact of recording the number of votes for the first candidate in the database system.

The signal reception of the next record from the input codogram containing information on the number of voters who voted for another MP with input 21 is again sent to the information input of the register block 1, where she is a synchronizing pulse from the entrance 23. With the release of 12 all contents of register block 1 again available at the output 25 of the system for subsequent documentation of records in the database system.

Described the process of recording the number of votes cast for the respective deputies, in fixed cells b the PS data assigned to respective candidates continues until the comparator 103 unit 7 will not fix the fact of the equality of the number of records counter 101 number of candidates stored in the register 102. At this point in time at the output 109 of the comparator, a signal is generated indicating that all records from the input message from the corresponding election Commission are listed in the corresponding memory cell assigned to the respective candidates.

The pulse output from the comparator 109, firstly, comes to the installation log 55 unit 3, where applied to the installation log trigger 43, setting it in the original condition in which a high potential with inverted output of the trigger 43 opens the element 48 And prepares a circuit for the passage of the clock pulse from the inlet 54 through the element 48 I.

Secondly, the pulse output 109 unit 7 is fed to the input 115 of the block 8, whence it is fed to the counting input of the counter 111 to count the electoral commissions, who have sent their messages. In this case, the counter 111 will record the receipt of records from the first election Commission. In the same register 112 keeps the number of election commissions, which shall send their messages about the voting results.

In addition, the clock pulse input 115 is delayed by the delay element 114 and the actuation time counter 111, and then is supplied to the clock input of the comparator 113, who, on this clock signal, compares the counter 111 and the register 112. Given the fact that the counter 111 has recorded only one electoral Commission, who have sent their results, the indications for this point in time will be less than the total number of election commissions, registered in the register 112.

As a result, the output 116 of the comparator 113 is formed the signal to begin reception of the input data following the electoral Commission, which is available at the output 33 of the system and then enters the admission control input messages the following electoral Commission (not shown).

After that receive input messages the next electoral Commission, documentation of accepted entries, the tabulation of votes cast for their respective deputies, and recording of the final results in the memory cell assigned to the respective candidates as described above.

Receiving an input message from the election commissions of subjects of the Russian Federation and processed in the manner described above continues until the comparator 113 unit 8 will not fix the fact of the equality of the counter 111 and the register 112, the formation of the pulse at the output 117. The appearance of this pulse indicates that all message of the election is athelny commissions documented, and the number of votes cast for the respective deputies, summarized, recorded in the selected memory cell assigned to the respective candidates, and is ready to issue on the scoreboard display and printing.

To this end, the pulse output 117 unit 8 is fed to the input 97 of the block 6, where the element 94 and then is supplied to the counting input of the counter 91, which records the fact of reading and the issuance of the final data vote for the first candidate. In this case, the counter 91 recorded the first unit and its readings via exit 99 unit 6 is fed to the input 87 of the block 5 and then input to the decoder 80. In register 92 unit 6 included the number of candidates who took part in the voting.

In addition, the pulse from the output of element 94 OR delayed element 95 on the actuation time counter 91 and is supplied to the clock input of the comparator 93, which clock signal compares the counter 91 and register 92. Given the fact that the counter 91 has recorded only one candidate, the results of the voting which shall be subject to extradition, his evidence to this point in time will be less than the total number of candidates registered in the register 92.

As a result, the output 100 of the comparator 93 is formed a signal of the beginning of the issuance of the final data vote for the first candidate to the second is fed to the input 88 of the block 5 and then goes on to survey the state of the elements 82-84 I. The status of the specified elements is determined by the decoder 80, which decodes the input code and opens the corresponding element 82-84 I. Suppose that this element is the element 82 I.

The clock pulse input 88, first of all, is the element 82 And is fed to the input of the read fixed memory permanent storage device 81, which stores the address of the memory cell in the database server assigned to the first candidate, and reads it to the input of the register 86.

In addition, the same pulse input 88 of the block 5 is delayed element 85-1 at the time of reading the contents of a fixed cell ROM and supplied to the clock input of the register 86, recording therein the address of the memory locations assigned to the first candidate. Code from the output of the register 86 through the outlet 89 of the block 5 is given to the input 132 of the block 9, and then supplied to one input elements 124 And groups.

In parallel, the pulse from the output element 85-1 delayed element 85-2 at the time of entering the address of the memory register 86 and then exit 90 unit 5 through the inlet 134 of the block 9 is issued for a single input trigger 121, setting it in one state, where the elements 124 And group and element 129 And will be opened, and the elements 122, 123 And groups - closed.

Simultaneously with this process synchronization pulse input 134 is delayed element of the om 127 at the time of a trigger 121 and outputting a code address memory cell, fixed for the first candidate on the address output 28 through the elements 124 And groups and elements 125 OR group, and then through the output system 30 is given to the input of the third channel interrupt server (not shown).

On this signal, the server goes to the subroutine to read the contents of the memory cells assigned to the first candidate, which stores the total number of votes cast for this candidate, and the issuance of the final number of votes for the first candidate on the scoreboard display and printing (not shown).

In addition, this same pulse issuing from the output element 127 is delayed element 128 at the time of execution of the program reading the final data and issue them on the scoreboard display and printing, and then exit 136 unit 9 is fed to the input 98 of the block 6, where the element 94 and then again fed to the counting input of the counter 91, increasing its readings on the unit. New counter 91 via exit 99 unit 6 is fed to the input 87 of the block 5 and then input to the decoder 80. In the same register 92 unit 6 is still the number of candidates who took part in the voting.

In addition, the pulse from the output of element 94 OR delayed element 95 on the actuation time counter 91 and again fed to the clock input of the comparator 93, which clock is ignal compares the counter 91 and register 92. Given the fact that the counter 91 is fixed now already the second candidate, the results of the voting which shall be subject to extradition, his evidence to this point in time will be less than the total number of candidates registered in the register 92.

As a result, the output 100 of the comparator 93 is formed a signal of the beginning of the issuance of the final data voting for another candidate, which is fed to the input 88 of the block 5 and then goes on to survey the state of the elements 82-84 I. the status of the specified elements is determined by the decoder 80, which decrypts the received code and opens the corresponding element 82-84 I. Suppose that this element is now element 83 I.

The clock pulse input 88, first of all, is the element 83 And fed to the input of the read fixed cell constant of the storage device 81, which stores the address of the memory cell in the database server reserved for another candidate. And reads it to the input of the register 86.

In addition, the same pulse input 88 of the block 5 is delayed element 85-1 at the time of reading the contents of a fixed cell ROM and supplied to the clock input of the register 86, locking it the address of a memory location reserved for another candidate. Code from the output of the register 86 through the outlet 89 of the block 5 is given to the input 132 of the block 9 and the next question is there some inputs elements 124 And groups.

In parallel, the pulse from the output element 85-1 delayed element 85-2 at the time of entering the address of the memory register 86 and then exit 90 unit 5 through the inlet 134 of the block 9 is issued for a single input trigger 121, confirming its one state, where the elements 124 And group and element 129 And will be opened, and the elements 122, 123 And groups - closed.

Simultaneously with this process synchronization pulse input 134 is delayed element 127 at the time of a trigger 121 and outputting a code address memory cell assigned to the next candidate on the address input 28 of the system through the elements 124 And groups and elements 125 OR group, and then through the output system 30 is again fed to the input of the fourth interrupt server (not shown).

On this signal, the server returns to the routine of reading the content of a memory location reserved for another candidate, in which is stored the total number of votes cast for this candidate, the scoreboard display and printing (not shown).

In addition, this same pulse issuing from the output element 127 is delayed element 128 at the time of execution of the program reading the final data and issue them on the scoreboard display and printing, and then output 136 of the block 9 is again fed to the input 98 of the block 6.

This process continues until the eye of the counter 91 will not be equal to the indications of the register 92. This point will be recorded by the comparator 93 by issuing the pulse at the output 118 from which this clock pulse, first, available at the output 34 of the system as a signal of completion of the issuance of the final data, and secondly, it is fed to the input 135 unit 9, where the installation log trigger 121 and returns it to its original state.

Thus, the introduction of new units and new constructive relationships significantly improve system performance by eliminating the time associated with the execution of the pre-record all the received information in a database, and their subsequent search and processing, by the localization of address records database identifiers received by the messaging system and the formation of the growing up of the voting results in real time.

Sources of information

1. U.S. patent No. 0505651, M CL G 06 F 13/40, 13/38, 1992.

2. U.S. patent No. 05129083, M CL G 06 F 12/00, 15/40, 1992 (prototype).

Automated system for the collection and processing of e-voting state automated system "Elections"containing block receiving input messages, information and clock inputs of which are the first information and the clock inputs of the system, and the first information output is first the m information output system, the information input unit receiving an input message is intended for reception patterns from electoral commissions, the clock input unit receiving an input message is intended for the reception of the synchronizing signal recording patterns of electoral commissions in the block receiving the input message, and the first information output unit receiving the input message is intended for generation of patterns of electoral commissions on the information input server unit receiving records database servers, data and clock inputs of which are the second information and the clock inputs of the system, the information input unit receiving records database server is designed to receive the records of the database server, and the clock input unit receiving records the database server is designed to receive a synchronizing signal adding records server database in block receiving records database of the server block data summary of the voting results, one data input connected to the output unit receiving records server database, other information input unit data summary of the voting results is connected to the second output unit receiving the input messages and the output of block data summary of results g is the voting is the second information output system, the signal read and write data output of which is the address of the system output, and one clock output signal read and write the database is the first clock output system, wherein the system contains the block identification electoral commissions, the information input connected to the third information output unit receiving an input message, the clock input of the identification block of the electoral commissions is connected to the first clock input of the system, the information output unit identification electoral commissions connected with the first information input of the signal read-write database, and synchronizes the output of block identification of the election commissions is the third synchronizing system output, the first identification block of the reference addresses of the candidates, an information input connected to the fourth output unit receiving an input message, and the clock input is connected to the synchronizing output of the identification block of election commissions, the data output of the first identification block of the reference addresses of the candidates is connected with the second information input of the signal read and the ISI database, and the word clock output of the first identification block of the reference addresses of the candidates is connected to the first clock input signal read-write database, the second identification block of the reference addresses of the candidates, the information output of which is connected with the third information input of the signal read-write database, and synchronizes the output is connected to the second clock input signal read-write database, the unit of selection cycles in time record of voting results, the input of which is connected with the second clock input system, the first output of the block selection time cycles record the results of voting is connected to the clock input of block data summary of voting results the second output of the block selection time cycles record of voting results is the fourth synchronizing system output and the third output block selection time cycles record of voting results is connected with the mounting unit identification electoral commissions, the block selection cycles in time of reception of the input message, the input of which is connected to the third output block selection time cycles record the results of voting, and one output is the first sign is inim output system, and the block selection time cycles of the results of voting, one input of which is connected to another output of the block selection cycles in time of reception of the input messages, the other input of the block selection time cycles of the results of voting is connected to the second clock output signal of the read and write databases, information output unit selection time cycles issuance of voting results is connected with the information input of the second identification block of the reference addresses of the candidates, which synchronizes the output of the block selection time cycles of the results of voting is connected to the clock input of the second identification block of the reference addresses of the candidates, and the signal output unit selection time cycles of the results of voting is the second signal the system output.



 

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