System for data distribution control in information analytical center network

FIELD: computer engineering; system for data distribution control in information analytical center network of air company commerce unit.

SUBSTANCE: system contains three registers, renewed data entries address identification device, client query data address identification device, decoder, data read control signal forming unit, and data output channels commutation unit.

EFFECT: simplified system, increased performance by excluding memory buffer blocks and time interval selector, and asynchronous mode of server-client interaction implementation.

5 dwg

 

The invention relates to computing, and in particular to systems for managing the distribution of data in the network of information-analytical centre of the commercial unit (IACB) of the airline.

Feature solved the technical problem is that users of information systems working in real time, collecting and processing data from distributed remote sources of information, could get collected and processed on the server information in the form of relevant documents and information in real time.

Known systems that could be used to solve the task (1, 2).

The first of the known systems contains blocks receiving and storing data, connected to the control units and data processing units, search and selection, connected to the blocks of the data storage and display, the clock inputs are connected to outputs of the control unit (1).

A significant disadvantage of this system is that you cannot solve the problem of updating data stored in memory in the form of relevant documents simultaneously with the solution of the issue of the content of these documents to your customers in real time.

Known and other system containing the first, second, and third registers, the first and the second decoders, first, second, third, and fourth memory blocks, the first, second, third and fourth groups of elements And the element And the first element OR the first and second groups of elements OR first, second, third, fourth, fifth and sixth delay elements and a selector time intervals (2).

The last of the above technical solutions closest to being described.

Its drawback is, first, in a constructive complexity, due to the fact that in order for the procedure to update data in an information network client-server it is in addition to the available server memory using two buffer memory unit, and, secondly, implemented in the device mode strict clock synchronization selector time intervals leads to unnecessary loss of time, which, in turn, reduces the system performance when the service user requests.

The purpose of the invention is to simplify the system and increase its performance by excluding the buffer memory blocks and selector timing and implementation of the asynchronous mode of interaction between client and server.

This objective is achieved in that the system containing the first register, the information input of which is the first information input system clock input is the first clock input the om system, one output is an information output system, and the other is connected with the information input device identification address to be updated, the second register, the information input of which is the second information input system clock input is the second synchronizing input of the system, and one output connected to the input of the decoder, the third register, the information input which is the third information input system clock input is the third synchronizing input of the system and switching unit channel data output, control inputs of which are connected to respective outputs of the decoder, the information input connected to the output of the third register and the inputs are outputs of the group entered the device identification address data of the customer's request, an information input connected to other information the output of the second register, a clock input connected to the second clock input of the system, and the control input is connected to control the output device identification address to be updated, the clock input of which is connected to the first clock input of the system, and the signal control reading of data, the first information and the first clock input catalogocucina with information and clock outputs device identification address to be updated accordingly, the second information and second clock inputs connected to information and clock outputs device identification address data of the client request, respectively, the first and second control inputs of the signal control reading of data are first and second control inputs system address output address is the system output, the first clock output is the first synchronizing system output, the second clock output is the second clock output system, and the installation exit is connected with the installation of the inputs of the first register and the device identification address of the updated records, the clock input of the switching unit channel data output connected to the third clock input of the system and the installation output connected installation input of the third register.

The invention is illustrated by drawings, where figure 1 shows the block diagram of the system figure 2 - structural diagram of the device identification address of the updated data records figure 3 - block diagram of the device identification data of the client request figure 4 - block diagram of the signal control reading of data, figure 5 is a structural block circuit switching channels of data output.

With the system (figure 1) contains the first 1, the second 2 and third 3 registers, device 4 identify the address of the updated data record, the device 5 identify the address of the data request from the client, the decoder 6, block 7 of the form the control signals of the read data and the block 8 switching channels of data output.

Figure 1 shows the first 11, second 12 and third 13 the information input system, the first 14 and second 15 and third 16 clock inputs of the system, the first 17 and second 18 control inputs of the system, as well as information output 20, the address output 21, the first 22 and second 23 information and outputs the group of information outputs 24-26 system.

The device identification address of the updated records (figure 2) contains the block 30 memory, made in the form of a persistent storage device, the decoder 31, the trigger 32, the elements 33 to 35 And the element 36 OR elements 37, 38 delay. The drawing shows information 40, the clock 41 and 42 installation inputs of the device, as well as information 43, the clock 44 and the control outputs of the device.

The device identification address data of the customer's request (figure 3) contains the block 50 memory made in the form of a persistent storage device, the decoder 51, the elements 53 and 56 And the element 57 OR elements 58, 59 delay. The drawing shows information 60, the clock 61 and 62 managing the input device, and the information the th 63 and synchronize the 64 outputs of the device.

The signal controls the reading of data (figure 4) contains a reversible counter 70, the elements 71, 72, OR a group of 73 elements OR elements 74, 75, 76 delay. The drawing shows the first 77 and second 78 informational inputs, the first 79 80 and the second clock inputs, the first 17 and second 18 control inputs, as well as address 21, the first 22 and second 23 clock and installation 81 outputs of the device.

Switching unit channel data output (figure 5) contains the group 90-92 elements And the elements 93, 94 delay. The drawing shows information 95 entrance, control 96-98 inputs and clock 99 the input unit, and a group of 24-26 information outputs and installation 100 output block.

All nodes and elements of the system are made on the standard of potentially switching elements.

The system works as follows.

The information input 11 system tract data information network IAC KB sequentially receives messages (codogram) from objects-sources of information containing the indicative and the information part.

Structure codogram has the following form:

The indicative part of codogramInformation part of codogram
Code message IDCode message content

Code codogram input 11 is supplied to the information input of the register 1, where he entered a synchronizing pulse received at the clock input of register with the inlet 14.

Substantial part of codogram with some informational output register 1 output 20 of the system and the indicative part of codogram with other information outputs of the register 1 is supplied to the information input device 40 4 where ID code of the message received at the input of decoder 31, deciphering code ID codogram and outstanding high potential on one of its outputs. For definiteness, suppose that the high potential of the decoder 31 is entered to one input of the element 33 I.

Unlike the prototype, the synchronization of system operation is performed upon receipt of codogram to the input 11 of the system clock pulse input 14, which through the clock input 41 of the device 4 receives as input element 37 delay, and direct entry of the trigger 32, setting it in one state, the inverted output 45 of the trigger 32 will produce a negative potential.

Item 37 delay delays the synchronizing pulse at the time of entry code codogram in register 1. Then the delayed synchronizing pulse from the output element 37 is fed to a survey of the situation of the of the elements 33-35 I.

Because open high potential decoder 31 will be only element 33 And, after this element And the delayed clock pulse, firstly, comes to reading fixed memory permanent storage device 30 that stores the base address of the memory locations of the database server where you want to record information, adopted by the register 1, and reads its information through the output 43 of the device 4, the information input 77 of the block 7 and the elements 73 OR group on the information input of reversible counter 70.

Secondly, the same clock pulse reading on the output element 36 OR device 4 is delayed by element 38 delay time read the contents of a fixed cell ROM 30 and then through the exit 44 of the device 4, the clock input 79 of the block 7 and the element 71 OR arrives at the clock input of the reversible counter, locking code it the base address of the memory locations of the database server, where it is necessary to record a substantial part of the received codogram.

As a result, the address output 21 of the system will appear the code base address of the memory of the database server, where it is necessary to record a substantial part of the received codogram.

Thirdly, the same synchronizing pulse input 79 of the block 7 is delayed by element 75 at the time of entry code base hell the ECA in the reversible counter 70 and through the exit 22 of the system is given to the input of the first interrupt server. On this signal, the server goes to the routine recording of a substantial part of codogram output system 20, the address of which is formed at the output 21 of the system.

In parallel, the pulse from the output element 75 is delayed element 76 delays at the time of recording the contents of codogram output 20 to the address generated at the output 21, and then exit 81 device 4 is issued for the installation of the inputs of the register 1 and the trigger 32 of the device 4, returning to their original state and thus preparing for a new cycle of operation.

The trigger 32 of the device 4 is designed to lock the circuit signals the client requests the update time of the database server.

If this trigger is in the initial state, there is a high potential with its inverted output 45 through the inlet 62 device 5 is supplied to one of inputs of the element 56 And the device 5 and opens it on one input, allowing the system to operate in the mode of data output from the client.

Codes of client requests received from the input 12 to the information inputs of the register 2, where they are assigned to a word clock input 15.

Structure codogram request user has the following form:

CodeCode
ID client request address workplace client

ID code of the client request from one of the output registers 2 through the inlet 60 of the device 5 to the input of the decoder 51, deciphering the code ID of the client request and issuing a high potential to one of its outputs. For definiteness, suppose that the high potential of the decoder 51 is received on one input element 55 I.

Unlike the prototype, the synchronization of the system operation in this mode is performed upon receipt of codogram logon request 12 system clock pulse input 15, which, through the clock input 61 of the device 5 is supplied to the other input element 56 I.

If the element 56 And will be closed low potential trigger 32, so is the procedure to upgrade the database server and the signal flow chain of the request will be blocked.

If the element 56 And is open, the clock pulse from the input device 61 5 passes to the input of the element 58 delay, which delays him at the time of entry code codogram request register 2. Then the delayed synchronizing pulse from the output of the element 58 is supplied to poll the status of the items 53-55 I.

Because open high potential decoder 31 will be only element 55 And, after this element And the delayed clock pulse, first, comes the t, input reading fixed memory permanent storage device 50, which stores the base address of the memory locations of the database server where you want to give the requested information and reads it through the information output 63 of the device 5, the information input 78 of the block 7 and the elements 73 OR group on the information input of reversible counter 70.

Secondly, the same clock pulse reading on the output element 56 OR device 5 is delayed element 59 delay time read the contents of a fixed cell ROM 50 and then through the outlet 64 of the device 5, the clock input 80 of the block 7 and the element 71 OR, is fed to the clock input of the reversible counter 70, the locking code it the base address of the memory locations of the database server.

As a result, the address output 21 of the system will appear the code base address of the memory of the database server, where you can choose the requested information.

Thirdly, the same synchronizing pulse input 80 of block 7 passes through the element 72 OR delay element 74 at the time of entry code base address in the reversible counter 70 and through the exit 23 of the system is given to the input of the second channel interrupt server. On this signal, the server goes to the subroutine reads the contents of codogram from memory database what's the server address, which is formed at the output 21 of the system.

Read from the memory cell database server information is fed to the input 13 of the register 3, where it is recorded synchronizing pulse server log 16.

From the output of the register 3 data upon request via the input 95 of the block 8 are received at the inputs of each of the groups 90-92 elements And the outputs are through the respective outputs 24-26 system connected to the inputs of the respective jobs clients.

The choice of the workplace of the client is carried out by code address coming from other information outputs of the register 2 to the input of the decoder 6. The decoder 6 decodes address code and generates a high potential to one of its outputs, for example, on its first release. The high potential of the first output through the input 96 unit 8 is supplied to one input elements 90 I.

In parallel, the clock pulse from the inlet 16 through the inlet 99 of the block 8 to the input of the delay element 93, detaining him at the time of recording the contents of codogram in register 3, and then passes to the other inputs of the elements 90 And rewriting the data output of register 3 to the input of the relevant workplace client through the exit 24 of the system.

In addition, the clock pulse from the output of element 93 is delayed at the time of issuing a data request to the customer's workplace element 94 delay and then udaetsya output 100 on the installation inputs of register 3, returning it to its original state.

In addition, unlike the prototype, in this system there is no need for the client to re-dial the code of the request, if the identifiers of the data characteristics close to each other.

In this case, after receiving the requested data address is formed in the reversible counter 70 unit 7, to the client at your workplace, simply press one button "Forward" or "Back".

For example, when you press "Forward" to the input 17 of the system receives a pulse which is fed to the counting input of the reversible counter 70, increasing its content per unit and, consequently, the address code at the output 21 of the system also increases by one.

This pulse passes through the element 72 OR delay element 74 at the time of actuation of the reversible counter 70 and through the exit 23 of the system is given to the input of the second channel interrupt server. On this signal, the server goes to the subroutine reads the contents of codogram from another memory database server at the address, which is formed at the output 21 of the system.

If the client in the workplace presses "Back", the pulse is fed to the input 18 of the system and further to the subtractive input of the reversible counter. With the arrival of this pulse reversible counter 70 reduces the base address of the memory cell is a unit.

In addition, this pulse passes through the element 72 OR delay element 74 at the time of actuation of the reversible counter 70 and through the exit 23 of the system is given to the input of the second channel interrupt server. On this signal, the server goes to the subroutine reads the contents of codogram from another memory database server at the address, which is formed at the output 21 of the system.

Thus, the exclusion of buffer memory blocks and selector time intervals were significantly simplify the system, and the implementation of an asynchronous mode of interaction between client and server will significantly improve its performance.

Sources of information

1. U.S. patent No. 5713014, 1998.

2. Patent of the Russian Federation No. 2218595, 2001 (prototype).

Management system data distribution in the network of information-analytical centre, containing the first register, the information input of which is the first information input system clock input is the first synchronizing input of the system, one solution is an information output system, and the other is connected with the information input device identification address to be updated, the second register, the information input of which is the second information input system clock input C the second clock input system, and one output connected to the input of the decoder, the third register, the information input which is the third information input system clock input is the third synchronizing input of the system, and a switching unit channel data output, control inputs of which are connected to respective outputs of the decoder, the information input connected to the output of the third register, and the outputs are a group of information outputs of the system, characterized in that it contains the device identification address data of the customer's request, an information input connected to other information the output of the second register, a clock input connected to the second clock input of the system, and the control input is connected to control the output device identify the address of the updated records, the clock input of which is connected to the first clock input of the system, and the signal control reading of data, the first information and the first clock input of which is connected with information and clock outputs device identification address to be updated accordingly, the second information and second clock inputs connected to information and clock outputs device identification address data for the dew client, respectively, the first and second control inputs of the signal control reading of data are first and second control inputs system address output address is the system output, the first clock output is the first synchronizing system output, the second clock output is the second clock output system, and the installation exit is connected with the installation of the inputs of the first register and the device identification address of the updated records, the clock input of the switching unit channel data output connected to the third clock input of the system and the installation exit is connected with the installation input of the third register.



 

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