Informational traffic monitoring device

FIELD: computer engineering; structure-statistical analysis of informational arrays.

SUBSTANCE: device contains current evaluation signal former, evaluation zones discriminator, pulse distributor, time intervals counter, commutator, search variable former, adding counters, storage units, division units, classifier, search strategy register, reset signals former, data representation and write unit, threshold signals change unit, current day timer, cutoff threshold former unit, structural analyzer.

EFFECT: increased informativity of traffic values, which define informational arrays structure due to structural analysis of determinate combinations.

2 cl, 3 dwg, 1 apl

 

The invention relates to the field of computer engineering and can be used as a device for structural and statistical analysis of data sets.

A device information search, described in the author's certificate of the USSR No. 1711185, IPC4G 06 F 15/40 declared 05.04.89. In this invention the described device information search, containing registers the upper and lower bounds, the adder-myCitadel, case-sensitive search strategy, subtractive and totalizers, the comparison circuit, the memory block, the register key, the output register, groups, items, And and OR, a trigger pulse distributor, input start, input addresses of the upper and lower bounds, the input code criteria change search strategies, input key, the output address output characteristic of a lack of information.

It is also known device information described in the patent of Russian Federation № 2116670, IPC6G 06 F 17/30 declared 07.04.97. In this invention the described device search information containing pulse distributor, the first and second shapers variable search, totalizers and memory blocks, the register search strategy, the driver signals the current assessment, the discriminator areas of evaluation values, the count of time intervals, the switch, the unit, classifier, the unit changes the threshold signals the timer of the current day, the display unit and the driver signals reset, information, input, inputs "Area 1" and "Zone 2", input "Nmax", "Threshold" and "start" and the output of the address.

However, the analogs have drawbacks consisting in a low speed search combinations beginning of the message and in a relatively low information content of the indicators of the graph describing the structure of the information arrays.

The nearest device (prototype) to offer described in the patent of the Russian Federation No. 2149446, IPC7G 06 F 17/30 declared 12.05.99. The device prototype contains the driver signals of the current assessment, the discriminator areas of evaluation values, the pulse distributor counter time intervals, the switch, the first and second shapers variable search, the first and second totalizers, the first and second memory blocks, the block division classifier register search strategy shaper signals reset, the unit changes the threshold signal, the timer of the current day, the shaping unit of the truncation threshold. The shaper's output signals of the current assessment is connected to the control input of the switch. Outputs the status of the situation - ISM" and "No change of state of the environment - UTS switch connected to the inputs respectively of the first and second shapers variable search. The output of the second shaper variable search is connected to the information input of the second sum counter. The output of the second sum counter is connected to the information input of the second memory block and the second information input unit. An output unit connected to the information input of the classifier. Outputs the status of the situation - P" and "Lack of state changes of the situation - On" of the classifier connected to the same inputs of the former (the reset signal. The output of the Reset generator of the signal connected to the reset input Reset of the first and second memory blocks, the count of time intervals and block the formation of the truncation threshold. Output "Maximum number of temporary interval - Nmax" block the formation of the truncation threshold is connected to the same inputs of the register search strategy, the first and second shapers variable search. The output of the first driver search variable is connected to the information input of the first sum counter. The output of the first sum counter is connected to the first information input unit. Outputs the status of the situation - ISM" and "No change of state of the environment - UTS discriminator areas of evaluation values connected to the same inputs of the switch. The first output of the pulse distributor is connected to the input synchronization driver signals of the current assessment, discriminator areas of evaluation values and the clock is input counter time intervals. The output of the current time interval - Ntech" the count of time intervals connected to the same inputs of the processing unit of the truncation threshold and register search strategy. Outputs the Value of the upper threshold classification - PCLVand the Value of the lower threshold classification - PKLN" case sensitive search strategy connected to the same inputs of the classifier. The second output of the pulse distributor is connected to the clock input of the switch. The third output of the pulse distributor connected to the inputs of the synchronization of the first and second memory blocks. The outputs of the first and second memory blocks are connected to information inputs respectively of the first and second summing counters. The fourth output of the pulse distributor is connected to the clock input of the classifier. The output Time of the timer of the current day are connected to the same inputs of the driver signals of the current assessment, discriminator areas of evaluation values, the pulse distributor and unit changes the threshold signals. The outputs of the Upper threshold value of search - Pinand the Lower threshold value of search - Pn" unit changes the threshold signals are connected to the same inputs of the register search strategy and block the formation of the truncation threshold. Inputs "start" and "Threshold" unit changes the threshold signal is connected to the od of omonim inputs of the processing unit of the truncation threshold and are respectively the inputs "start" and "Threshold" of the device. Inputs Maximum number of the time interval - Nmax"-, "Numerical unit value - 1" and "sample interval analysis - VSEL" block the formation of the truncation threshold are the same input device. Inputs "Area" of the first and second shapers search variable are respectively inputs "Area 1" and "Zone 2" of the device.

The described device has a higher speed of search combinations beginning of the message, compared to the devices described earlier, through the use of a range of new blocks and adjusting the maximum number of time intervals throughout the analysis interval adequate input information stream.

However, the device prototype has the disadvantage of relatively low information content of indicators chart showing the structure of data sets, due to the fact that it measures only the intensity of the input graph for combinations beginning of the message.

The aim of the invention is a device that increases the information content of the traffic figures showing the structure of data sets, due to the structural analysis of the deterministic combinations.

This objective is achieved in that in the known device search information containing the driver signal is in the current assessment, the discriminator areas of evaluation values, the pulse distributor counter time intervals, the switch, the first and second shapers variable search, the first and second totalizers, the first and second memory blocks, the block division classifier register search strategy shaper signals reset, the unit changes the threshold signal, the timer of the current day, the shaping unit of the truncation threshold, the output of the shaper signal current assessment is connected to the control input of the switch outputs the status of the situation - ISM" and "No change of state of the environment - UTS which are connected to the inputs respectively of the first and second shapers variable search the output of the second shaper search variable is connected to the information input of the second summing counter, the output of which is connected to the information input of the second memory block and the second information input unit, the output of which is connected to the information input of the classifier outputs the status of the situation - P" and "Lack of state changes of the situation - which is connected to the same inputs of the driver signal from the reset output the Reset button which is connected to the input "Reset" of the first and second memory blocks, the count of time intervals and block the formation of the truncation threshold, the output"Maximum number time frame - Nmax" which is connected to the same inputs of the register search strategy, the first and second shapers search variable, the output of the first driver search variable is connected to the information input of the first summing counter, the output of which is connected to the first information input unit that outputs the status of the situation - ISM" and "No change of state of the environment - UTS discriminator areas of evaluation values connected to the same inputs of the switch, the first output of the pulse distributor is connected to the input synchronization driver signals of the current assessment, discriminator areas of evaluation values and the clock input of the counter time intervals, the output of the current time interval Ntech" which is connected to the same inputs of the processing unit of the truncation threshold and register search strategy, outputs the Value of the upper threshold classification - PCLVand the Value of the lower threshold classification - PKLN" which is connected to the same inputs of the classifier, the second output of the pulse distributor is connected to the clock input of the switch, the third output of the pulse distributor connected to the inputs of the synchronization of the first and second memory blocks for storing increments posteriori integral function is s probability distribution respectively normal and rejected States of the input information stream on the N-th observation interval, the outputs of the first and second memory blocks are connected to information inputs respectively of the first and second summing counters, the fourth output of the pulse distributor is connected to the clock input of the classifier, the output Time of the timer of the current day are connected to the same inputs of the driver signals of the current assessment, discriminator areas of evaluation values, the pulse distributor and unit changes the threshold signal, outputs the "Upper threshold value search - Pinand the Lower threshold value of search - Pn" which is connected to the same inputs of the register search strategy and block the formation of the truncation threshold, the input "start" and "Threshold" unit changes the threshold signals are connected to the same inputs of the processing unit of the truncation threshold and are respectively the inputs "start" and "Threshold" of the device, the inputs Maximum number of the time interval - Nmax", "Numeric value of units - 1" and "sample interval analysis - VSEL" block the formation of the truncation threshold are the same input device inputs "Area" of the first and second shapers search variable are respectively inputs "Area 1" and "Zone 2" device, inputs the display unit and write data, structural analyzer, third, fourth and fifth blocks of memory.

In ormational output structural analyzer connected to information inputs of the driver signals of the current assessment and discriminator areas of evaluation values. The inputs "a Deterministic combination", "Unknown tag", "Desired feature" and "Address unknown characteristic Address NP imaging unit and writing data are connected to the same outputs of the structural analyzer. Exit "Address" structural analyzer connected to the same inputs of the third, fourth and fifth blocks of memory. The output Data "1" of the third memory block used for storing pre-programmed values of the number of known deterministic combinations stored in the cells of the fourth memory block connected to the same inputs of the display unit and write data and the structural analyzer. Outputs "Data 2" and "Data 3", respectively, the fourth and fifth blocks of memory for storing pre-programmed accordingly known and deterministic search combinations, connected to the same inputs of the structural analyzer. The release of "heartbeats" structural analyzer connected to the same inputs of the fourth and fifth blocks of memory. Outputs Data 1 write Data 2 write Data 3 write unit display and recording of data connected to the same inputs, respectively, of the third, fourth and fifth blocks of memory. Exit Address 3 - write imaging unit and writing data are connected to the same input p is the block of memory. Output Address 1, 2 - write imaging unit and writing data are connected to the same inputs of the third and fourth memory blocks. Enter "Time" unit display and recording of data connected to the same output of the timer of the current day. The inputs change of state of the environment - P" and "Lack of state changes of the situation - On" imaging unit and writing data are connected to the same outputs of the classifier. Information and clock inputs of the structural analyzer are respectively the information and clock inputs of the device.

The structural analyzer consists of an input register, a decoder, the first, second and third parallel registers, counter, first, second and third Comparators, the first and second elements And element, the first and second elements OR evaluator hash function, RS-trigger pulse generator. Information and the clock input of the input register are respectively the information and clock inputs of the structural analyzer. The output of the input register is connected to information inputs of the decoder, the first parallel register and transmitter hash function. The output of the transmitter hash function is connected to the input of the third parallel register and is output Address structural analyzer. The output of the third parallel is part of the register is the output of "Address unknown sign - Address NP" structural analyzer. The output of the first parallel register is connected to the information input of the second parallel register and the first information input of the second and third Comparators. The second information input of the second comparator is the input "Data 2" structural analyzer. The release of "Equality a=b" of the second comparator is connected to the second input of the second element OR input element. The output element is NOT connected to the second input of the first element And. the Second information input of the first comparator is input Data "1" structural analyzer. The release of "Equality " And=" first comparator connected to the first input of the first element And. the Output of the first element And connected to the first inputs of the first and second elements OR control input of the third parallel register and is output "Unknown tag" structural analyzer. The output of the counter is connected to the first information input of the first comparator. The output of the first element OR is connected to the control input of the second parallel register. The output of the second parallel register is output Deterministic combination of the structural analyzer. The second information input of the third comparator is the input "Data C" structural analyzer. The release of "Equality " And=" the third comparator on what is connected to the second input of the first element OR the third input of the second element OR is the output of "Desired feature" structural analyzer. The output of the second element OR is connected to the input of a "zero - OST" RS-flip-direct the output of which is connected to the first input of the second element And. the Second input of the second element And is connected to the output of the pulse generator. The output of the second element And is connected to the third control inputs of the first, second and third Comparators, information counter input and is the output of "heartbeats" structural analyzer. The output of the decoder is connected to the control input of the first parallel register, the input "Reset" counter input "Start" evaluator hash function, input "Setting units - OST" RS-flip-flop and an information output structural analyzer.

Thanks to the new essential features by introducing a block display and recording of data, the structural analyzer and additional memory blocks that are hashing and recognition searched and unknown deterministic combinations, increases the information content of the indicators of the graph describing the structure of the information arrays.

The analysis of the level of technology has allowed to establish that the analogues of characterizing the set of characteristics is identical for all features of the declared t is khnichenkova solutions no, that indicates compliance of the device to the condition of patentability "novelty". Search results known solutions in this and related areas of technology in order to identify characteristics that match the distinctive features of the prototype of the features of the declared object, showed that they do not follow explicitly from the prior art. The prior art also revealed no known effect provided the essential features of the claimed invention transformations on the achievement of the technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

The claimed device is illustrated by drawings:

figure 1 is a General diagram of the device monitoring information traffic;

figure 2 - structural analyzer;

figure 3 - algorithm of operation of the imaging unit and the data record.

The device monitoring information of the graph shown in figure 1, contains the driver signals of the current evaluation 1, the discriminator areas of evaluation values 2, the pulse distributor 3, the count of time intervals 4, switch 5, the first 6 and second 7 shapers variable search, the first 8 and second 9 totalizers, first 10 and second 11 memory blocks, the block division 12, the classifier 13, the register search strategy 14, formirovanie the signals reset 15, the display unit and write data 16, the unit changes the threshold signal 17, the timer current day 18, block the formation of the truncation threshold 19, the structural analyzer 20, 21 third, fourth, 22 and 23 fifth memory blocks.

The shaper's output signals of the current estimate 1 is connected to the control input of the switch 5. Outputs the status of the situation - ISM" and "No change of state of the environment - UTS switch 5 is connected to the inputs respectively of the first 6 and second 7 shapers variable search. The output of the second shaper variable search 7 is connected to the information input of the second sum counter 9. The output of the second sum counter 9 is connected to the information input of the second memory block 11 and the second information input unit 12. The output unit 12 is connected to the information input of the classifier 13. Outputs the status of the situation - P" and "Lack of state changes of the situation Of the ' classifier 13 is connected to the same inputs of the former (the reset signal 15. The output of the Reset generator the reset signal 15 is connected to the input "Reset" of the first 10 and second 11 memory blocks, counter time intervals 4 and block the formation of the truncation threshold 19. Output "Maximum number of temporary interval - Nmax" block the formation of the truncation threshold 19 is connected to agnomen the th inputs of the register search strategy 14, the first 6 and second 7 shapers variable search. The output of the first driver search variable 6 is connected to the information input of the first summing counter 8. The output of the first sum counter 8 is connected to the first information input unit 12. Outputs the status of the situation - ISM" and "No change of state of the environment - UTS discriminator areas of evaluation values 2 are connected to the same inputs of the switch 5. The first output of the pulse distributor 3 is connected to the input synchronization driver signal current estimate 1, discriminator areas of evaluation values 2 and clock input of the counter time intervals 4. The output of the current time interval - Ntech" the count of time intervals 4 is connected to the same inputs of the processing unit of the truncation threshold 19 and register search strategy 14. Outputs the Value of the upper threshold classification - PCLVand the Value of the lower threshold classification - PKLN" case sensitive search strategies 14 is connected to the same inputs of the classifier 13. The second output of the pulse distributor 3 is connected to the clock input of the switch 5. The third output of the pulse distributor 3 is connected to the inputs of the synchronization of the first 10 and second 11 memory blocks. The outputs of the first 10 and second 11 memory blocks connected to the information the inputs respectively of the first 8 and second 9 summing counters. The fourth output of the pulse distributor 3 is connected to the clock input of the classifier 13. The output Time of the timer of the current day 18 connected to the same inputs of the driver signals the current assessment 1, discriminator areas of evaluation values 2, the pulse distributor 3 and unit changes the threshold signal 17. The outputs of the Upper threshold value of search - Pinand the Lower threshold value of search - Pn" unit changes the threshold signal 17 is connected to the same inputs of the register search strategy 14 and block the formation of the truncation threshold 19. Inputs "start" and "Threshold" unit changes the threshold signal 17 is connected to the same inputs of the processing unit of the truncation threshold 19 and are respectively the inputs "start" and "Threshold" of the device. Inputs Maximum number of the time interval - Nmax", "Numeric value of units - 1" and "sample interval analysis - VSEL" block the formation of the truncation threshold 19 are of the same input device. Inputs "Area" of the first 6 and second 7 shapers search variable are respectively inputs "Area 1" and "Zone 2" of the device.

Information output structural analyzer 20 is connected to information inputs of the driver signals the current assessment 1 and discriminator areas of evaluation values 2. The inputs "a Deterministic combination", "Unknown attribute is to", "Search feature" and "Address unknown characteristic Address NP imaging unit and write data 16 is connected to the same outputs of the structural analyzer 20. Exit "Address" structural analyzer 20 is connected to the same third inputs 21, 22 fourth and fifth 23 blocks of memory. The output Data "1" of the third memory block 21 is connected to the same inputs of the display unit and write data 16 and the structural analyzer 20. Outputs "Data 2" and "Data 3", respectively, the fourth 22 and 23 fifth memory blocks connected to the same inputs of the structural analyzer 20. The release of "heartbeats" structural analyzer 20 is connected to the same inputs 22 fourth and fifth 23 blocks of memory. Outputs Data 1 write Data 2 write Data 3 write block display and write data 16 are connected respectively to the eponymous third inputs 21, 22 fourth and fifth 23 blocks of memory. Exit Address 3 - write imaging unit and write data 16 is connected to the same input of the fifth memory block 23. Output Address 1, 2 - write imaging unit and write data 16 is connected to the same inputs of the third 21 and 22 fourth memory blocks. Enter "Time" unit display and recording data 16 is connected to the same output timer current day 18. The inputs change of state of the environment - P" and "No change of state, h is ovci - About the" block display and write data 16 is connected to the same outputs of the classifier 13. Information and clock inputs of the structural analyzer 20 are respectively information and clock inputs of the device.

The structural analyzer 20 is designed to generate a signal of start of operation of the entire device, hashing, and recognition searched and unknown deterministic combinations and can be implemented in various ways, in particular, as shown in figure 2.

The structural analyzer 20 comprises an input register 20.1, decoder 20.2, first 20.3, second 20.5 and third 20.15 parallel registers, counter 20.4, first 20.6, second 20.8 and third 20.12 Comparators, the first and 20.7 second 20.17 elements And element 20.9, first 20.10 and second 20.11 elements OR evaluator hash function 20.13, RS-flip-flop 20.14, pulse generator 20.16. Information and the clock input of the input register 20.1 are respectively the information and clock inputs of the structural analyzer. The output of the input register 20.1 connected to information inputs of the decoder 20.2, the first parallel register 20.3 and evaluator hash function 20.13. The output of the transmitter hash function 20.13 connected to the input of the third parallel register 20.15 and is output Address structural analyzer 20. You are the od of the third parallel register 20.15 is the output of "Address unknown sign - Address NP" structural analyzer 20. The output of the first parallel register 20.3 connected to the information input of the second parallel register 20.5 and the first information input of the second 20.6 and third 20.12 Comparators, the second information input of the second comparator is 20.8 input "Data 2" structural analyzer 20. The release of "Equality " And=" second comparator 20.8 connected to the second input of the second element OR 20.11 and the input element 20.9. The output of 20.9 element is NOT connected to the second input of the first element And 20.7. The second information input of the first comparator is 20.6 input "Data 1" structural analyzer 20. The release of "Equality " And=" first 20.6 comparator connected to the first input of the first element And 20.7. The output of the first element And 20.7 connected to the first inputs of the first 20.10 and second 20.11 elements OR control input of the third parallel register 20.15 and is output "Unknown tag" structural analyzer 20. The output of the counter 20.4 connected to the first information input of the first comparator 20.6. The output of the first element OR 20.10 connected to the control input of the second parallel register 20.5. The output of the second parallel register 20.5 is the output of "Deterministic combination of structural analyzer 20. The second information input of the third comparator 20.12 is the input Data is" structural analyzer 20. The release of "Equality " And=" the third comparator 20.12 connected to the second input of the first element OR 20.10, the third input of the second element OR 20.11 and is the output of "Desired feature" structural analyzer 20. The output of the second element OR 20.11 connected to the input of "zero - OST" RS-flip-flop 20.14. Direct RS-flip-flop 20.14 connected to the first input of the second element And 20.17. The second input of the second element And 20.17 connected to the output of the pulse generator 20.16. The output of the second element And 20.17 connected to the third control input of the first 20.6, second 20.8 and third 20.12 Comparators, information input counter 20.4 and is the output of "heartbeats" structural analyzer 20. The output of the decoder 20.2 is connected to the control input of the first parallel register 20.5, input Reset counter 20.4, input "Start" evaluator hash function 20.13, input "Setting units - OST" RS-flip-flop 20.14 and an information output structural analyzer 20.

The assignment of blocks and elements of the claimed device the following.

The driver signals the current estimate 1 is designed to generate at the end of the current interval analysis binary signal showing the state of the environment and takes values of "ISM" or "OTS". Diagram of the shaper signal current estimate 1 is known, described in the patent of the Russian Federation No. 2116670 and see nafig.

The discriminator zones values assessment 2 is designed to generate a signal of the zone number of the state in which the input information stream corresponding intensity. Schema discriminator areas of evaluation values 2 known, described in the patent of the Russian Federation No. 2116670 and is shown in figure 3.

Pulse distributor 3 is designed to synchronize the operation of the entire device by forming four pulse sequences, shifted relative to each other by a certain amount Δt. Diagram of the pulse distributor 3 is known, described in the patent of the Russian Federation No. 2116670 and is shown in figure 4.

The count of time intervals 4 is designed to count the number of observed time intervals and outputting a combination of the number of the time interval "Ntech". The count of time intervals 4 is a summing counter, whose schema is known and is described in [Batashev VA, Veniaminov V.N., Kovalev, V.G. and other Circuits and their application. - M.: Energy, 1978. - 248 S.] on str-187, RES.

The switch 5 is designed for switching a signal of the zone number at the input of the corresponding shaper variable search control signal coming from the shaper signal current assessment 1 and takes values of "ISM" and "OTS". Diagram of the switch 5, is described in the patent of Russian Federation № 2116670 and is shown in figure 5.

The first 6 and second 7 shapers variable search designed to build increments posteriori integral functions of the probability distribution normal FAbout(N) (the first shaper variable search 6) and rejected (FP(N) (the second shaper variable search 7) state of the input information stream on the N-th observation interval. Scheme of the first 6 and second 7 shapers variable search identical. The first shaper variable search 6 known, described in the patent of the Russian Federation No. 2116670 and is shown in Fig.6.

The first 8 and second 9 totalizers are for adding the values of the increments FAbout(N) and FP(N) with the corresponding values of the empirical cumulative distribution functions calculated for N-1 time interval FAbout(N-1) and FP(N-1). The first 8 and second 9 totalizers are arithmetic adders, schemes are known and described in [fundamentals of pulse and digital techniques. Textbook for high schools. - M.: Soviet radio, 1975. - 440 S.] on str, RES.

The first 10 and second 11 memory blocks are used to store the increments of FAbout(N) and FP(N) within one interval analysis. The first 10 and second 11 memory blocks are registers parallel actions, schemes are known and described in [Schlapobersky Century is. Basic techniques of transmission of discrete messages. - M.: Communication, 1973. - 480 S.] on p.106, fig.3.1.

The unit 12 is designed to divide the increment of FP(N) increment FAbout(N) distribution and likelihood ratios. The unit 12 is a unit of the division of two n-bit binary numbers without restoring balance, the scheme of which is known and described in [Bocharov C.P., Nemchinov N.N., Petrov H., Sulin LI Computational systems of automated control systems. - L.: YOU, 1984. - 368 S.] on p.88-90, RES.

The classifier 13 is designed to generate signals "ISM" or "OTS" by comparing the input information with the threshold values. Diagram of the classifier 13 is known, described in the patent of the Russian Federation No. 2116670 and shown in Fig.7.

Register search strategy 14 is designed to generate an interval or a point thresholds classification depending on whether the number of search interval limit or not. The scheme register search strategy 14 known, described in the patent of the Russian Federation No. 2116670 and shown in Fig.

The driver of the reset signal 15 is designed to combine signals "ISM" and "OTS", intensification, and coordination with subsequent blocks. The driver of the reset signal 15 may be made in the form of two-input scheme OR whose schema is known and is described in [Schlapobersky V.I. basic techniques n the passing of discrete messages. - M.: Communication, 1973. - 480 S.] on p.48-49, RES.

The display unit and write data 16 is designed to display information about the presence of the desired and unknown deterministic combinations and changes in the intensity of the input information stream, the record is not certain previously known deterministic combinations in the fourth memory block 22 with a simultaneous change in the third memory block 21 values of the number of known deterministic combinations stored in the cells of the fourth memory block 22, the record is not defined previously searched deterministic combinations in the fifth memory block 23. The entry in the third 21, 22 fourth and fifth 23 blocks of memory at the address specified by the evaluator hash function 20.13. The display unit and the recording data can be implemented in various ways, in particular in the form of a microprocessor operating in accordance with the algorithm shown in figure 3.

The unit changes the threshold signal 17 is designed to change the threshold values of the signals depending on the time of day. Block circuit changes the threshold signal 17 is known, described in the patent of the Russian Federation No. 2116670 and is shown in Fig.9.

Timer current day 18 is designed for installation on the time of day of the entire device. Diagram of the timer of the current day 18 known and described in [Batashev VA, Veniaminov V.N., Kovalev, V.G. and other Micro is Hemi and their application. - M.: Energy, 1978. - 248 S.] on str-199, RES.

The block forming the truncation threshold 19 is designed to adjust the maximum number of time interval "Nmax" adequate input information flow throughout the analysis interval. Block circuit 19 is known, described in the patent of the Russian Federation No. 2149446 and is shown in figure 2.

Input register 20.1 is designed to convert input deterministic combination of sequential code in parallel. The schema of the input register 20.1 known and described in [Batashev VA, Veniaminov V.N., Kovalev, V.G. and other Circuits and their application. - M.: Energy, 1978. - 248 S.] on str-184.

The decoder 20.2 designed to highlight the combination of the beginning of the message at the output of the input register 20.1 and start the operation of the entire device. The decoder circuit 20.2 known and described in [Schlapobersky V.I. basic techniques of transmission of discrete messages. - M.: Communication, 1973. - 480 S.] on str-153, RES.

First 20.3 and second 20.5 parallel registers are used to store a deterministic combination within one interval analysis. Schema first 20.3 and second 20.5 parallel registers known and described in [Schlapobersky V.I. basic techniques of transmission of discrete messages. - M.: Communication, 1973. - 480 S.] on p.106, fig.3.1.

Counter 20.4 designed to count the number of clock impul the owls, coming from the output of the second element And 20.17 and issuance of combinations in the first comparator 20.6. The number of clock pulses corresponds to the number of received known deterministic combinations from the fourth memory block 22 in the structural analyzer 20 for one interval analysis. Meter scheme 20.4 known and described in [Batashev VA, Veniaminov V.N., Kovalev, V.G. and other Circuits and their application. - M.: Energy, 1978. - 248 S.] on p.120, RES.

First 20.6 comparator is designed to compare two m-bit numbers, the first of which comes from the output of the counter 20.4 at the first input and the second output Data "1" of the third memory block 21, and upon coincidence of the issue on the release of "Equality " And=" signal "1". Scheme of the first comparator 20.6 known and described in [Lebedev O., Sidorov A.M. Pulse and digital devices. Digital nodes and their design on the chip. - L.: YOU, 1980. - 128 S.] on p.52-54, RIS, table 2.11.

The first item 20.7 is designed to generate a signal of the presence of the unknown characteristic in the input data stream at the output of the structural analyzer 20 when receiving on its inputs the signal "1" outputs "Equality " And=" first comparator 20.6 and 20.9 element is NOT. The scheme of the first element And 20.7 known and described in [Schlapobersky V.I. basic techniques of transmission of discrete messages. - M.: Communication, 1973. - 80 S.] on p.44, 2.4).

The second comparator 20.8 designed for comparing two n-bit numbers, the first of which comes from the output of the first parallel register 20.3, and the second output Data "2" of the fourth memory block 22, and upon coincidence of the issue on the release of "Equality " And=" signal "1". The scheme of the second comparator 20.8 known and described in [Lebedev O., Sidorov A.M. Pulse and digital devices. Digital nodes and their design on the chip. - L.: YOU, 1980. - 128 S.] on p.52-54, RIS, table 2.11.

Item NO 20.9 inverts the signal received at its input from the output of the second comparator 20.8, on the opposite. The schema element is NOT 20.9 known and described in [Batashev VA, Veniaminov V.N., Kovalev, V.G. and other Circuits and their application. - M.: Energy, 1978. - 248 S.] on str, table 4.2.

The first element OR 20.10 is designed to generate the signal on the control input of the second parallel register 20.5 in the presence of unknown or desired characteristic in the input data stream. The scheme of the first element OR 20.10 known and described in [Schlapobersky V.I. basic techniques of transmission of discrete messages. - M.: Communication, 1973. - 480 S.] on p.48-49, RES.

The second element OR 20.11 is designed to generate a signal at the input of "0" RS-flip-flop 20.14, in the presence of known, unknown or desired prize is aka in the input data stream. The scheme of the second element OR 20.11 known and described in [Schlapobersky V.I. basic techniques of transmission of discrete messages. - M.: Communication, 1973. - 480 S.] on p.48-49, RES.

The third comparator 20.12 designed for comparing two n-bit numbers, the first of which comes from the output of the first parallel register 20.3, and the second output Data "H" of the fifth memory unit 23, and upon coincidence of the issue on the release of "Equality " And=" signal "1". The scheme of the third comparator 20.12 known and described in [Lebedev O., Sidorov A.M. Pulse and digital devices. Digital nodes and their design on the chip. - L.: YOU, 1980. - 128 S.] on p.52-54, RIS, table 2.11.

The transmitter hash function 20.13 designed for dividing the input device deterministic combinations representing n-bit binary number by a predetermined n-bit binary number with a remainder and delivery addresses deterministic combination in the third 21, 22 fourth, fifth 23 blocks of memory and information input of the third parallel register 20.15. The transmitter hash function 20.13 is a unit of the division of two n-bit binary numbers method to restore balance, the scheme of which is known and described in [Horsetail ST, Verlinsky N.N., Popov E.A. Microprocessors and microcomputers in automatic control systems. The Handbook. - L.: Mashinostroenie is e, 1987. - 640 S.] on str-575, table 18.6.

RS-trigger 20.14 designed to control the operation of the second element And 20.17, performing the function key. Diagram of the RS-flip-flop 20.14 known and described in [Katushev, VA, Veniaminov V.N., Kovalev, V.G. and other Circuits and their application. - M.: Energy, 1978. - 248 S.] on str-159, is(a).

The third parallel register 20.15 designed for storing addresses deterministic combination coming from the output Address of the computer the hash function 20.13 within one interval analysis. The scheme of the third parallel register 20.15 known and described in [Schlapobersky V.I. basic techniques of transmission of discrete messages. - M.: Communication, 1973. - 480 S.] on p.106, fig.3.1.

The pulse generator 20.16 is designed to generate clock pulses. Diagram of the pulse generator 20.16 known and described in [Batashev VA, Veniaminov V.N., Kovalev, V.G. and other Circuits and their application. - M.: Energy, 1978. - 248 S.] on SCR-194, figure 5.19(d).

The second element, And 20.17 designed to supply clock pulses to the counter 20.4, first 20.6, second 20.8, third 20.12 Comparators, 22 fourth and fifth 23 blocks of memory. The scheme of the second element And 20.17 known and described in [Schlapobersky V.I. basic techniques of transmission of discrete messages. - M.: Communication, 1973. - 480 S.] on p.43-48 2.4).

The third memory block 21 is designed to store the pre-programmed values of Koli is este known deterministic combinations stored in the cells of the fourth memory block 22. The third memory block 21 is an electrically programmable permanent memory, which is known and described in [Horsetail ST, Verlinsky N.N., Popov E.A. Microprocessors and microcomputers in automatic control systems. The Handbook. - Leningrad: Mashinostroenie, 1987. - 640 S.] on str-474.

The fourth memory block 22 is designed to store pre-programmed known deterministic combinations. The fourth memory block 22 is an electrically programmable permanent memory, which is known and described in [Horsetail ST, Verlinsky N.N., Popov E.A. Microprocessors and microcomputers in automatic control systems. The Handbook. - Leningrad: Mashinostroenie, 1987. - 640 S.] on str-474.

The fifth memory unit 23 is designed to store pre-programmed desired deterministic combinations. The fifth memory block 23 is an electrically programmable permanent memory, which is known and described in [Horsetail ST, Verlinsky N.N., Popov E.A. Microprocessors and microcomputers in automatic control systems. The Handbook. - Leningrad: Mashinostroenie, 1987. - 640 S.] on str-474.

The device monitoring information of the graph is as follows.

Input information the pot is to, synchronized with a clock pulse is supplied to the information input of the structural analyzer 20 (Fig 1).

The structural analyzer 20 (figure 2) produces a signal to start the operation of the entire device when the combination of the beginning of the message in the input data stream and searches for the unknown and the predetermined desired deterministic combinations and if any issues accordingly, the signal at the input "Unknown tag" or "Desired feature", and input "a Deterministic combination of the imaging unit and write data 16. Object recognition are desired and unknown deterministic combinations in the input data stream. Every deterministic combination representing an n-bit binary number is divided into a predetermined n-bit binary number with a remainder. The remainder is the value of the hash function. On the detected value of the hash function, which is the address in the fourth memory block 22 are pre-programmed known deterministic combination, compare them with the received determined by a combination of the presence of the match. In case of discrepancy between any of the data stored in the fourth memory block 22 deterministic combination with the received signal is output Unknown indication display unit displays the I and write data 16. Also found the value of the hash function, which is the address, in the fifth memory unit 23 are pre-programmed desired deterministic combinations and compare them with the received determined by a combination of the presence of the match. If it matches one of the stored in the fifth memory block 23 deterministic combination with the received signal is given "Desired feature"displayed by the display unit and write data 16.

In the input register 20.1 deterministic combination under the action of pulses converted from the sequential code in parallel and fed to the information inputs of the decoder 20.2, the first parallel register 20.3 and evaluator hash function 20.13.

In the decoder 20.2 in the event of a combination of the beginning of the message at specific output bits of the input register 20.1 the signal of the start of operation of the entire device, which is supplied to the control input of the first parallel register 20.3, the input "Reset" the counter 20.4, triggering input of the transmitter hash function 20.13, enter "1" RS-flip-flop 20.14 and information on the inputs of the driver signals the current assessment 1 and discriminator areas of evaluation values 2. On this signal the deterministic combination with the output of the input register 20.1 recorded in the first parallel register and 20.3 registers obseg the destination computer, the hash function 20.13, at the output of RS flip-flop 20.14 level is set to a logical unit, and the driver signals the current assessment 1 and discriminator areas of evaluation values 2 analyze the intensity of the input stream.

In the first parallel register 20.3 deterministic combination is stored within one interval analysis. With the release of the first parallel register 20.3 deterministic combination is supplied to the information input of the second parallel register 20.5 and the first inputs of the second 20.8 and third 20.12 Comparators.

Counter 20.4 counts the number of clock pulses received at its input from the output of the second element And 20.17, and outputs a combination of the first comparator 20.6 about received known deterministic combinations from the fourth memory block 22 in the structural analyzer 20 for one analysis interval.

In the first comparator 20.6 under the action of clock pulses received at a control input from the second element And 20.17, the operation is the comparison of two combinations of two m-bit binary numbers, the first of which comes from the output of the counter 20.4 at the first input and the second output Data "1" of the third memory unit 21 to the second input, and when there is a match, the output of "Equality " And=" the signal "1"which is supplied to the first input of the first element And 20.7.

In the second comparator 20.8 under the action of clock pulses received at a control input from the second element And 20.17, the operation is the comparison of two deterministic combinations of two n-bit binary numbers, the first of which comes from the output of the first parallel register 20.3 at the first input and the second output Data "2" of the fourth memory block 22 to the second input, and when there is a match, the output of "Equality " And=" second comparator 20.8 produces a signal "1"which is supplied to the second input of the second element OR 20.11 and input item NO 20.9.

When no signal "1" at the output of "Equality " And=" second comparator 20.8 output element 20.9 produces a signal "1"supplied to the second input of the first element And 20.7. When the signal "1" at the first input of the first element And 20.7 coming with the release of "Equality " And=" first 20.6 comparator, the output of the first element And 20.7 produces a signal "1"is received at the first inputs of the first 20.10 and second 20.11 elements OR the control input of the third parallel register 20.15 and enter "Unknown feature" block display and write data 16.

When a signal "1" on any input of the first element OR 20.10 with outputs of the first element And 20.7 or "Equality " And=" the third comparator 20.12, at its output vyrabatyvaete the signal "1", arriving at the control input of the second parallel register 20.5. On this signal the deterministic combination is recorded in the second parallel register 20.5 and is fed to the input "a Deterministic combination of the imaging unit and write data 16.

When a signal "1" on any of the three inputs of the second element OR 20.11 with outputs of the first element And 20.7, "Equality " And=" second 20.8 or third 20.12 Comparators, at its output the signal "1"at the input "0" RS-flip-flop 20.14. This signal RS-trigger 20.14 ceases to generate the signal "1" at the input of the second element And 20.17, with the output of the second element And 20.17 cease to receive the clock pulses, the work of the structural analyzer 20 in the interval analysis ends.

In the third comparator 20.12 under the action of clock pulses received at a control input from the second element And 20.17, the operation is the comparison of two deterministic combinations of two n-bit binary numbers, the first of which comes from the output of the first parallel register 20.3 at the first input and the second output Data "3" of the fifth memory block 23 to the second input, and when there is a match, the output of "Equality " And=" the third comparator 20.12 produces a signal "1"which is supplied to the second input of the first element And The And 20.10, the third input of the second element OR 20.11 and input "Desired feature" block display and write data 16.

The transmitter hash function 20.13 produces division received information input deterministic combinations representing n-bit binary number by a predetermined n-bit binary number method to restore balance, which is the hash function and representing an n-bit binary number, which is fed to the input "Address" 21 third, fourth, 22, 23 fifth memory blocks and on the information input of the third parallel register 20.15.

RS-trigger 20.14 controls the operation of the second element And 20.17, performing the function key. RS-trigger 20.14 unlocks the key (the second element And 20.17) when the signal "1" at the input "1" and closes it when the signal "1" at the input "0".

When a signal "1" to the control input of the third parallel register 20.15 address generated by the transmitter hash function 20.13, is written in the third parallel register 20.15 and is fed to the input Address NP imaging unit and write data 16.

The pulse generator 20.16 generates pulses which are fed to the second input of the second element And 20.17.

With the release of the second element And 20.17 when the first input signal "1" output from the RS flip-flop 20.14 heartbeats post is up on the information input counter 20.4, the inputs "heartbeats" 22 fourth, fifth, 23 memory blocks and the control inputs of the first 20.6, second 20.8 and third 20.12 Comparators.

With an output of the third memory block 21 pre-programmed values of the number of known deterministic combinations found in the cells of the fourth memory block 22 to the address received from the output of the transmitter hash function 20.13, read to the second input of the first comparator 20.6.

From the output of the fourth memory block 22 pre-programmed known deterministic combination located at the address supplied from the output of the transmitter hash function 20.13 sequentially read out under the action of the clock pulses coming from the output of the second element And 20.17, to the second input of the second comparator 20.8.

From the output of the fifth memory block 23 pre-programmed desired deterministic combination located at the address supplied from the output of the transmitter hash function 20.13 sequentially read out under the action of the clock pulses coming from the output of the second element And 20.17, to the second input of the third comparator 20.12.

While many well-known and sought-deterministic combinations stored respectively in the fourth 22 and 23 fifth memory blocks, the same deterministic combinations have not.

In the shaper signal current is her assessment 1 at the end of the current interval analysis produces a binary signal, characterizing the state of the environment. When exceeding the deviation of the number of combinations of start messages from the average value at the top or bottom side more than the threshold at the output of the shaper signal current estimate 1, a signal is generated ISM, in other cases, the signal "OTS". With the shaper's output signals of the current evaluation 1 signal "ISM" or "OTS" then flows to the control input of the switch 5.

In the discriminator areas of evaluation values 2 the signal about the zone number of the state in which the input information stream corresponding intensity. This zone number corresponds to a more accurate assessment of the situation compared to the estimate obtained in the shaper signal current valuation 1. Outputs of "ISM" or "OTS" discriminator areas of evaluation values 2 signal respectively "ISM" or "OTS" comes on the same switch input 5.

Pulse distributor 3 synchronizes the operation of the entire device by forming four pulse sequences, shifted relative to each other by a certain amount Δt.

The count of time intervals 4 counting the number of observed time intervals and outputs a combination of the number of the time interval to the input "Ntech" case sensitive search strategies 14 and block forms the work truncation threshold 19.

The switch 5 in accordance with entering the control signal from the shaper signal current assessment 1 connects a signal on the zone status "ISM" or "OTS" respectively, to the input of the first 6 or 7 second shaper variable search, where the signal based on the zone number Km(1<j<m), the highest zone numbermand the maximum number of observations Nmaxyou build the increments of FP(N) and FAbout(N) an empirical cumulative distribution functions of probability rejected and the normal state of the graph on the N-th observation interval:

In summarizing the counters 8 and 9 compares the values of the increments FP(N) and FAbout(N) with the corresponding values of the empirical cumulative distribution functions calculated for N-1 time interval FP(N-1) and FAbout(N-1), which are received from the outputs of the memory blocks 10 and 11:

FP(N)=FP(N-1)+FP(N),

FAbout(N)=F0(N-1)+FAbout(N).

The values of FP(N) and FAbout(N) are fed to the inputs of unit 12 and write the first 10 and second 11 memory blocks. The unit 12 performs an arithmetic division operation

and the issue of likelihood ratio information on the progress of the classifier 13.

The classifier 13 produces a decision about the state of the environment by comparing the input information with a threshold value and outputs a signal "P" or "O" on the unit display and recording data 16 and the driver signals reset 15.

Register search strategy 14 generates an interval or a point thresholds classification depending on whether the number of search interval limit or not. The signal from one of the outputs "PCLV" or "PKLN" case sensitive search strategies 14 is supplied to the corresponding input of the classifier 13.

Shaper signals reset 15 produces a signal "Reset", and supplies it to the inputs of the counter 4, the first 10 and second 11 memory blocks and block the formation of the truncation threshold 19 for transfer to their original state.

The display unit and write data 16 displays information about the presence of the desired and unknown deterministic combinations in the input data stream and changes in the intensity of the input information stream when signals respectively from the structural analyzer 20 and the classifier 13. If necessary, records not previously made known deterministic combinations in the fourth memory block 22 and changes in the third memory block 21 value N of the number of known deterministic combinations of N+1, Christmas is in the cells of the fourth memory block 22, records not previously entered search deterministic combinations in the fifth memory block 23. The algorithm of operation of the imaging unit and write data (hereinafter simply the algorithm is shown in figure 3.

In block 1 of the algorithm on the data received from the ports P5 ("state Change of scenery - P"), P6 ("Without changing the state of the environment - On") and P8 ("Time"), the display and recording information about the changes in the intensity of the input information stream.

In unit 2 of the algorithm on the data received from the ports A11 (Determ. comb."), A12 ("Unknown. the characteristic") and A13 ("Claim. the sign"), is displaying information about the presence of the desired or unknown characteristic in the input data stream.

In block 3 of the algorithm on the basis of information obtained from block 2 of the algorithm, the operator decides whether a deterministic combination of unknown sign. If Yes, then the transition in block 5 of the algorithm. If not, then the transition in block 4 of the algorithm.

In unit 4 of the algorithm on the basis of information obtained from block 2 of the algorithm and data port P8 ("Time"), is a deterministic combination, which is known by the sign in time.

In block 5 of the algorithm on the basis of information obtained from block 2 of the algorithm and data ports P1 ("Data 1"), P8 ("Time"), a10 ("the Address of the NP"), is a deterministic whom is inali, which is the unknown sign, address, specified by the evaluator hash function 20.13 and data ("Data 1") in time.

In block 6 of the algorithm, the operator decides to write an unknown characteristic in the region of the desired traits. If Yes, go to block 8 of the algorithm. If not, go to block 7 of the algorithm.

In block 7 of the algorithm, the operator decides to write an unknown characteristic in a region of known characteristics. If Yes, go to block 9 of the algorithm. If not, the end.

In block 8 of the algorithm deterministic combination is determined as desired, and the Address of the NP as the address of this combination.

In block 10 of the algorithm is issuing commands to ports P4 ("Data 3 - write) and P9 ("Address 3 - record"), in which the combination received from unit 8 of the algorithm, written in the fifth memory unit 23 to the address received from unit 8 of the algorithm.

In block 9 of the algorithm deterministic combination is determined as is known, is changing the value of N stored in the third memory unit 21, the number of known deterministic combinations stored in the fourth memory block 22, N+1, "Address NP" is defined as the address of this combination and this value.

In block 11 of the algorithm is issuing commands to the ports P2 ("Data 1 record"), P3 ("Data 2 - record") and A7 ("Address 1, 2 - entry"), in which the combination and the value is the received from block 9 of the algorithm, written in the third 21 and 22 fourth memory blocks to the address received from block 9 of the algorithm.

The adaptation of the threshold values of the search to the time of day is in the block 17, the outputs of which form the upper and lower thresholds, depending on the time of day. Code current time arrives at its input with timer current day 18 setting the time of day of the entire device.

The block forming the truncation threshold 19 produces a new value "Nmax" at the end of the current interval analysis, which is adequate to the characteristics of the input information stream, and outputs it to the inputs of Nmax" case sensitive search strategy 14, the first 6 and second 7 driver search variable.

All units, devices and elements, signal processing, and a line connecting them, must have a width corresponding to the width of the input operands and the accuracy of the transformation.

Assessment increase the informativeness of the performance graph, the proposed device is presented in Appendix.

Thus, the obtained results allow to conclude that the proposed device increases the informativeness of traffic metrics, which characterize the structure of the information array.

APPLICATION

Evaluation of increasing the information content of pokazatel the th traffic monitoring device data traffic

Evaluation of increasing the explanatory power of the indicators for the information traffic in the proposed device monitoring information traffic carried out according to [Taraskin MM Theoretical problems of support of decision-making in recognition of the situation in automated information systems.: The monograph. - SPb.: MAS, 2002. - 332 S.].

Informative about changes in the intensity of the input information stream can be estimated coefficient value, equal to the ratio of the number of deterministic combinations rejected intensity to the total number of received deterministic combinations:

where N is the total number of received deterministic combinations,

δi,1- the ratio of the intensity of the i-th deterministic combination which takes the value 1 if there is a deviation of the intensity of receipt of the i-th deterministic combination, and 0, otherwise.

Informative about the presence of unknown and deterministic search combinations in the input data stream can be estimated by the ratio of information content, defined by the formula:

K2=1-K3,

where

where N is the total number of received deterministic combinations,

δi,3the similarity factor of the i-th deterministic combination which takes the value 1 if the i-th deterministic combination is known and neokoroi, and 0, otherwise.

The device is a prototype allows you to find only the first coefficient value, which characterizes changes in the intensity of the input traffic. Thus, the amount of knowledge about the input data stream is determined by the formula:

where X is the total number of traffic performance.

The proposed device allows you to find two factor information. Thus, the amount of knowledge about the input data stream is determined by the formula:

where X is the total number of traffic performance.

Win R (at times) the proposed unit amount of knowledge about the input information flow is shown in figure 4 and is determined by the formula:

1. The device monitoring information traffic that contains the driver signals of the current assessment, the discriminator areas of evaluation values, the pulse distributor counter time intervals, the switch, the first and second shapers variable search, the first and second totalizers, the first and second memory blocks, the block division, KLA is sification, register search strategy shaper signals reset, the unit changes the threshold signal, the timer of the current day, the shaping unit of the truncation threshold, the output of the shaper signal current assessment is connected to the control input of the switch outputs the status of the situation - ISM" and "No change of state of the environment - UTS which are connected to the inputs respectively of the first and second shapers search variable, the output of the second shaper search variable is connected to the information input of the second summing counter, the output of which is connected to the information input of the second memory block and the second information input unit, the output of which is connected to the information input of the classifier outputs "Changing the state of the environment - P" and "Lack of state changes of the situation - which is connected to the same inputs of the driver signal from the reset output the Reset button which is connected to the input "Reset" of the first and second memory blocks, the count of time intervals and block the formation of the truncation threshold, the output "Maximum number of temporary interval - Nmax" which is connected to the same inputs of the register search strategy, the first and second shapers search variable, the output of the first driver search variable is connected to the information I shall do the first sum counter, the output of which is connected to the first information input unit that outputs the status of the situation - ISM" and "No change of state of the environment - UTS discriminator areas of evaluation values connected to the same inputs of the switch, the first output of the pulse distributor is connected to the input synchronization driver signals of the current assessment, discriminator areas of evaluation values and the clock input of the counter time intervals, the output of the current time interval - Ntech" which is connected to the same inputs of the processing unit of the truncation threshold and register search strategy, outputs the Value of the upper threshold classification - PCLVand the Value of the lower threshold classification - PKLN" which is connected to the same inputs of the classifier, the second output of the pulse distributor is connected to the clock input of the switch, the third output of the pulse distributor connected to the inputs of the synchronization of the first and second memory blocks for storing increments posteriori integral distribution functions of probability, respectively normal and rejected States of the input information stream on the N-th observation interval, the outputs of the first and second memory blocks are connected to information inputs respectively of the first and the WTO the CSOs summing counter, the fourth output of the pulse distributor is connected to the clock input of the classifier, the output Time of the timer of the current day are connected to the same inputs of the driver signals of the current assessment, discriminator areas of evaluation values, the pulse distributor and unit changes the threshold signal, outputs the "Upper threshold value search - Pinand the Lower threshold value of search - Pn" which is connected to the same inputs of the register search strategy and block the formation of the truncation threshold, the input "start" and "Threshold" unit changes the threshold signals are connected to the same inputs of the processing unit of the truncation threshold and are respectively the inputs "start" and "Threshold" of the device, the inputs Maximum number of the time interval - Nmax", "Numeric value of units - 1" and "sample interval analysis - VSEL" block the formation of the truncation threshold are the same input device inputs "Area" of the first and second shapers search variable are respectively inputs "Area 1" and "Zone 2" device, characterized in that it further introduced the display unit and write data, structural analyzer, third, fourth and fifth memory blocks, the information output structural analyzer connected to information inputs of the driver signals of the current assessment and discrim is the General areas of evaluation values, the inputs "a Deterministic combination", "Unknown tag", "Desired feature" and "Address unknown characteristic Address NP imaging unit and writing data are connected to the same outputs of the structural analyzer, the output Address of which is connected to the same inputs of the third, fourth and fifth blocks of memory, the output Data "1" of the third memory block used for storing pre-programmed values of the number of known deterministic combinations stored in the cells of the fourth memory block connected to the same inputs of the block display and record data and structural analyzer outputs Data "2" and "Data 3", respectively, the fourth and fifth blocks of memory for storing pre-programmed accordingly known and deterministic search combinations, connected to the same inputs of the structural analyzer, the output of "Heartbeat," which is connected to the same inputs of the fourth and fifth blocks of memory that outputs Data 1 write Data 2 write Data 3 write unit display and recording of data connected to the same inputs, respectively, of the third, fourth and fifth blocks of memory, the output Address 3 - write imaging unit and writing data are connected to the same the entrance of the fifth memory block output Address 1, 2 - write a block of the display and writing data are connected to the same inputs of the third and fourth memory blocks, enter "Time" unit display and recording of data connected to the same output of the timer of the current day, the inputs change of state of the environment - P" and "Lack of state changes of the situation - On" imaging unit and writing data are connected to the same outputs of the classifier, information and clock inputs of the structural analyzer are respectively the information and clock inputs of the device.

2. The device according to claim 1, characterized in that the structural analyzer consists of an input register, a decoder, the first, second and third parallel registers, counter, first, second and third Comparators, the first and second elements And element, the first and second elements OR evaluator hash function, RS-trigger pulse generator, the information and the clock input of the input register are respectively the information and clock inputs of the structural analyzer, the output of the input register is connected to information inputs of the decoder, the first parallel register and transmitter hash function whose output is connected to the input of the third parallel register and is output Address structural analyzer, the output of the third parallel register is the output of "Address unknown characteristic Address NP" structural analyzer, o is d first parallel register is connected to the information input of the second parallel register and the first information input of the second and third Comparators, the second information input of the second comparator is the input "Data 2" structural analyzer, the output of the Equality a=b" of the second comparator is connected to the second input of the second element OR input element, the output of which is connected to the second input of the first element And the second information input of the first comparator is input Data "1" structural analyzer, the output of "Equality " And=" first comparator connected to the first input of the first element And whose output is connected to the first inputs of the first and second elements OR control input of the third parallel register and is output "Unknown the characteristic structural analyzer, the output of the counter is connected to the first information input of the first comparator, the output of the first element OR is connected to the control input of the second parallel register whose output is the output of "Deterministic combination of structural analyzer, the second information input of the third comparator is the input "Data 3" structural analyzer, the output of "Equality " And=" the third comparator is connected to the second input of the first element OR to a third input of the second element OR is the output of "Desired feature" structural analyzer, the output of the second element OR is connected to the input of a "zero - OST" RS-trigger, direct access which the CSO is connected to the first input of the second element, And the second input is connected to the output of the pulse generator, the output of the second element And is connected to the third control inputs of the first, second and third Comparators, information counter input and is the output of "heartbeats" structural analyzer, the output of the decoder is connected to the control input of the first parallel register, the input "Reset" counter input "Start" evaluator hash function, input "Setting units - OST" RS-flip-flop and an information output structural analyzer.



 

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FIELD: computer engineering, possible use in devices for controlling informational streams to monitor informational traffic.

SUBSTANCE: method includes preliminarily forming a base of standard informational signs, receiving informational stream, serially selecting and recording fragments of informational stream, selecting identification signs from these, comparing them to standard ones. Base of standard informational signs is formed by computing morphological coefficient d of identification sign and its address A with utilization of hash-function. For identification signs received from informational stream, morphological coefficients d and identification addresses A are additionally computed, after that on basis of computed address, identification sign selected from informational stream is compared to standard one.

EFFECT: increased information processing speed due to shorter time needed for identification of addresses of signs in base of standard informational signs.

4 cl, 2 dwg, 2 tbl

FIELD: computer engineering, in particular, informational-reference system of industrial-economical characteristics of airlifts.

SUBSTANCE: system contains two registers, data commutation block, block for selecting automated workplace of user, block for identification of type of data being requested, block for selection of viewing direction of reference data, block for commutation of synchronization signals, reverse counter, block for receiving database update files, block for identification of type of data being updated, two blocks for comparing codes.

EFFECT: increased speed of system operation due to no need for searching information across whole volume of server database.

10 dwg, 1 app

FIELD: computer science, in particular, engineering of automatic system for controlling routing of text documents in data processing network.

SUBSTANCE: system contains first, second, third, fourth, fifth and sixth registers, first and second blocks for identification of text documents, block for integration of control signals, two counters, adder, block for forming base address for recording finished documents and commutator.

EFFECT: increased speed of system operation by localizing range of data search addresses in server database by means of identifiers of text documents.

6 dwg

FIELD: computer engineering, possible use as device for structural-statistical analysis of information arrays.

SUBSTANCE: device contains generator of signals of current estimate, discriminator of zones of estimate values, distributor of impulses, counter of temporal intervals, commutator, first and second generators of search variable, first and second adding counters, first and second memory blocks, division block, classification device, register of search strategy, signals generator, timer of current day, block for generation of cutting threshold, structural analyzer and third memory block.

EFFECT: possible recognition of target determined combinations, representing n-digit binary numbers.

2 cl, 2 dwg

FIELD: computer engineering; evaluation of reliability and quality of functioning of complex automated and flexible industrial and telecommunicational systems of arbitrary structure, which use cyclical production, telecommunication services and time reservation.

SUBSTANCE: device contains control unit, system model unit, system parts condition imitators unit, failure signal generation unit, registration unit, failure signals control unit, failure signals transformation unit, failure signals recognition unit, failure signals comparator unit.

EFFECT: increased reliability of identification of condition of industrial or telecommunication system in environment of ambiguity of modeled signals parameters, which define the membership of specific condition signal of either no-failure operation state space or failure state space.

7 cl, 12 dwg

FIELD: statistical data manipulation methods.

SUBSTANCE: initial approximation of useful signal evaluation is received with iterative refining. Further useful signal approximations in every sliding interval position are formed in consequent approximation unit as a result of iterative application of least squares method to received evaluations. Method is realized in procedure of variation-weighted quadratic approximations with vector weight function of least modules method until the difference between consequent approximations, which come to evaluation storage register, is less than defined threshold level.

EFFECT: reduced influence of measurement dispersion.

4 dwg

FIELD: computer engineering; system for optimizing passenger traffic of transport companies.

SUBSTANCE: system consist of analyzed time period identification unit, data reception and distribution unit, three registers, counter, income index value current write address forming unit, address signals integration unit, three adders, three multipliers.

EFFECT: optimization indexes improvement by excluding expert evaluation and including of statistical sampling of analyzed data for analysis.

10 dwg

FIELD: radio engineering, computer engineering.

SUBSTANCE: device for parametric estimation of message streams partition law contains input amplifier, parameters calculation block, block for calculation of average arithmetic values, block for determining type of partition, calculator of partition, control block, intensiveness analysis block, packet sign analysis block, block for transformation of type of packet sign, thus making it possible to estimate parameters of partition of homogeneous and non-homogeneous (mixed) streams of multi-packet messages with high trustworthiness, distinguishing marks of which packets (signs of beginning and end of information part of packets) may be identified both quantitatively and qualitatively - ambiguously, in uncertain manner, with utilization of linguistic variable, due to comparing analysis in block of incoming bit series for matching with signs of packets, appropriate for implemented exchange protocol and taking a decision about logic-mathematical nature of their identification attributes, which is mathematically correct, on basis of methods of theory of fuzzy sets, transformation in block of source data, characterizing signs of packets and identified in fuzzy form as type, useable for parametric estimation of message streams partition law.

EFFECT: increased trustworthiness of parametric estimate of partition law of message streams.

3 cl, 10 dwg

FIELD: radio engineering, computer science.

SUBSTANCE: device for parametric estimation of message streams distribution law contains: input amplifier, parameters computation block, average arithmetic values computation block, block for determining distribution type, distribution computing device, control block, intensiveness analysis block, block for analyzing trustworthiness of messages. Thus, it is possible to estimate parameters of distribution of homogeneous and heterogeneous streams of multi-packet messages with high trustworthiness, specific signs of pauses for which may be identified both quantitatively and qualitatively - untrustworthily, due to comparative analysis in block of bit series received in binary code from position of their match to signs of pauses and mathematically correct transformation, on basis of neuron networks theory, of untrustworthily identified signs of pauses to form, useable for performing procedure of parametric estimation of message streams distribution law.

EFFECT: increased trustworthiness if estimating under conditions, appropriate for real functioning process of multi-channel radio-communication networks and local area networks under conditions of untrustworthy identification of signs of pauses between multi-packet messages, circulating in given networks.

4 cl, 8 dwg

Probability device // 2276402

FIELD: radio engineering and computer science, possible use in complexes of automated systems for controlling multichannel radio communication networks and in devices for processing and transferring data of local computing networks.

SUBSTANCE: probability device contains indicator of random series 1, block for forming non-integer indicator values 2, correction block 3, block for forming values of matrix 4, control block 5, threshold devices block 6, block for forming indicator values 7, clock pulses generator 8, DENY element 9, AND elements block 10, memory block 11, decoder 12, time setting block 13, OR element 14, block 15 for increasing trustworthiness. Device makes it possible to model controllable semi-markov circuits with high trustworthiness with consideration of controlling effects, and dynamically changes threshold values of states, set both numerically and qualitatively, and untrustworthily, due to serial comparison of source data, received as binary code; taking of decision is possible about their mathematical nature and also transformation of source data in block 15, given in incorrect manner, to form, useable for parametric modeling procedure realization.

EFFECT: increased trustworthiness of parameters modeling of real functioning process of multichannel radiocommunication networks and local area networks under conditions of untrustworthy (not full) given data, of probability device, capable of highly trustworthy modeling of controllable semi-markov circuits, formed with consideration of both quantity and quality of given data, describing threshold values and probability-time mechanism (elements of transfer probability matrices) of status changes in modeled random processes.

3 cl, 6 dwg

FIELD: computer science, possible use for determining random values distribution law and can be used for engineering of digital signals processing devices for classification of series of digital data on basis of available standard series.

SUBSTANCE: device has analog-digital converter, two memory block, n comparators, decoder, n counters.

EFFECT: simplified construction, maintenance and manufacture of device, increased speed of operation.

6 dwg

FIELD: computer science.

SUBSTANCE: device has current input clamp and mating input clamp, current counter with inbuilt pulse sensor, converter of alternating voltage to direct voltage, analog=digital converter, register, digital memory block, pulse counter, selection pulse generator, second and first D-triggers, first, second and third and fourth AND elements, SR-trigger, OR element, clock pulse generator, pulse distributor.

EFFECT: simplified construction, higher reliability, higher efficiency.

1 dwg

FIELD: computer science.

SUBSTANCE: device has physical value measurements results storage block, delay block, averaging-out block, control block, clock pulse generation block, block for approximation using method of least squares, block for storing trend estimates.

EFFECT: lesser error, higher efficiency.

9 dwg

FIELD: cybernetics.

SUBSTANCE: on basis of discontinuous measurements of input x(t) and output y(t) signals of object with discretization step Δt ranges are determined according to formula: [x(nΔt)-εx,x(nΔt)+εx],[y(nΔt)-εy,y(Δt)+εy], where n=0, 1, 2,..., and εx, εy - values of limit allowed errors of used measurement means, interval values of input and output signals are sent to continuous division identifier, on which continuous division is produced with several interval coefficients, on basis of which interval discontinuous transfer function is restored and also predicting model, and interval model values of output object signal are determined.

EFFECT: higher efficiency, higher precision, higher trustworthiness, broader functional capabilities.

4 dwg

FIELD: computers.

SUBSTANCE: device has ADC, address multiplexer, memory block, combination adder, division block, counts number counter, control block, quality control block, indication block.

EFFECT: higher efficiency.

2 cl, 2 dwg

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