Sixteen-position quadrature amplitude keyed signal receiver

FIELD: radio engineering; demodulation of sixteen-position quadrature amplitude keyed signals.

SUBSTANCE: newly introduced in prior-art sixteen-position quadrature amplitude keyed (KAM-16) signal demodulator are fifth and sixths counters and phase error correction unit; there units make it possible to execute following new operations with signal: counting of signal points within count interval, their quantity enabling evaluation of phase error due to unwanted lock-on; correction of calculated phase error in phase error correction unit.

EFFECT: enlarged functional capabilities.

2 cl, 5 dwg, 1 tbl

 

The invention relates to electrical engineering and can be used at the reception and demodulation of signals shestnadtsetirichnoe quadrature amplitude-shift keying (QAM-16).

Known demodulator shestnadtsetirichnoe quadrature amplitude manipulation, containing the first and second phase detectors, filter, generator, first and second limiters (see RF patent №2013018, IPC 5 H 04 L 27/22, publ. BI No. 9, 15.05.94 g) [1].

The disadvantage of this demodulator is its low immunity, associated with the presence of point a false capture phase of its discriminatory characteristic in the neighborhood of ϕ≈23° (see [1, 2]). The operation of the demodulator in a state of false capture phase, which in the known device cannot be detected and corrected, leads to a complete loss of information at the output of the demodulator.

It is also known a device for the recovery of the carrier frequency signals shestnadtsetirichnoe quadrature amplitude manipulation, containing the first and second phase detectors, the first and second low pass filters, Phaser and four adder (see RF patent №2019054, IPC 5 H 04 L 27/34, publ. in BI No. 16, 30.08.94,) [2].

A disadvantage of the known device consists in its low noise immunity associated with possible loss of information due to the presence of false capture the phase when the ϕ ≈23° (see [2, 3]). In General, the presence of false grabs phase is the principal feature of receivers and demodulators signals with amplitude and phase shift keying, which is explained by multimodality, i.e. the presence of multiple maxima of the likelihood function in the evaluation phase of carrier recovery of such signals (see, for example, N. Parkhomenko, Botashev BM, Shelepin Y.S. Research schemes recovery of the carrier frequency signals quadrature amplitude manipulation // Questions radioelektronniki. Ser. IDW. - M.: NIEIR. - 1991. - VIP, p.65-76) [3].

To eliminate the possibility of false seizures in the demodulator signals, QAM-16, in some cases empirically synthesize such schemes recovery of the carrier frequency, which do not have points of false grips phase discriminatory characteristic.

A common shortcoming of this approach is that because such devices do not correspond to the optimum, that is, the structure of which follows from theory estimates the initial phase ϕ signal, such devices have a high dispersion of the recovered carrier in the vicinity of the working point ϕ=0°. This leads to low noise immunity of such devices.

Known demodulator shestnadtsetirichnoe quadrature amplitude manipulation, containing the VA phase detector, Phaser, six adders and a voltage controlled oscillator (VCO) (see RF patent №2020767, IPC 5 H 04 L 27/22, publ. in BI No. 18, 30.09.94,) [4].

A disadvantage of the known device is its low immunity, associated with high variance of the control voltage at the output of the VCO when the ϕ=0°despite the fact that the known device has a discriminatory feature in phase, no false points of seizures.

The optimal combination of high noise immunity when ϕ=0° and minimum loss of information in case of any false grabs is the use of optimal devices have, however, undesirable points false grips, special units, detecting and remediating these false attacks.

This device is a receiver of signals quadrature amplitude manipulation, containing the first and second low pass filters, generator, item OR Phaser (see RF patent №2019053, IPC 5 H 04 L 27/34, publ. in BI No. 16, 30.08.94,) [5], which has special parts and components for the detection and elimination of false grips.

A disadvantage of the known device is the low reliability of the detection is a false grip and, as a consequence, low immunity. This is due to the fact that the principle of false detection of seizures and in the known device is based on the assumption that that for certain values of the angle of phase mismatch ϕ in some selection decision on the transmitted symbol does not fit one signal point.

This assumption is true only at unrealistically high signal to noise at the input device.

When the actual signal to noise at the input device, of the order of 20÷25 dB, this assumption is not always correct. In this regard, in the known device in a real working relationship signal/noise ratio, the stress values corresponding to the presence or absence of a false capture in the known device, differ slightly. Thus, the effects of noise in the known device is a high probability of not detecting a false grip or mistaken identity and address, when in fact the capture was true.

Known technical solutions closest to the technical nature of the claimed device is a receiver of signals shestnadtsetirichnoe quadrature amplitude manipulation, containing the first and second filters are low pass, ten Comparators, the first and second elements And the phase shifter 90°, the carrier recovery block, the six elements, OR four counter, the first and second blocks of the comparison register and the first and second phase detectors, the input of which is uedineny and are input devices, the second input of the first phase detector connected to the input of the phase shifter 90°, the output of which is connected to a second input of the second phase detector, the outputs of the first and second phase detectors are connected respectively to the inputs of the first and second low-pass filters, the outputs of the first and second low-pass filters connected respectively to the inputs of the first and the fourth comparator, the inputs of the first, second, third, seventh and eighth Comparators are connected, and the outputs of the seventh and eighth Comparators are connected to the inputs of the first element OR the output of which is connected to the input of the first counter and the first input of the second element OR the output and the second input of which is connected respectively with the input of the second counter and the input of the third counter, the input of the third counter connected to the output of the third element OR, the inputs of which are connected to the outputs of the ninth and tenth comparator whose inputs are connected to inputs of the fourth, fifth and sixth Comparators, the outputs of the second and fifth Comparators are respectively the first and second outputs, the outputs of the first and third Comparators are connected respectively to the first input of the fourth element OR direct input of the first element And the inverse of the input and output of which are connected respectively with the output of the second comparator vtorym entrance of the fourth element OR the output of which is the third output, the fourth output which is the output of the fifth element OR, the inputs of which are connected respectively to the outputs of the sixth comparator and the second element And to direct and inverse inputs of which are connected respectively to the outputs of the fourth and fifth Comparators, the second inputs of the first and second units of comparison is connected to the output of the register, the outputs of the first and second units of comparison are connected with the inputs of the sixth element OR the output of the fourth counter connected to the reset inputs of the first, second and third counters (see RF patent №2235440, IPC 7 H 04 L 27/22, publ. in BI No. 24, 27.08.04,) [6] is a prototype.

In the known device is reliable detection of false seizures through the use of the properties of the fundamental differences in the States of the third counter when the true and false takeover phase.

In this case elimination of detected false capture phase is to start the sweep generator signal, which displays the carrier recovery block of the state a false capture by the impact of the sawtooth voltage.

Because when a new block reference carrier recovery in synchronism in the known device does not use such operations on the signal, which would be guaranteed to be delivered from repeated false grip, the known device is that as there is a high probability of repeated false grip (and third, the fourth and so on) even after the discovery and elimination of initial false capture phase.

When quick communication sessions such a long cycle search of the true state capture is invalid, because the mode of operation of the sweep generator signal is lost all information on the receiver output.

Thus, a disadvantage of the known device is its low immunity due to low reliability eliminate false takeovers or, equivalently, a great time to eliminate the false grips.

The technical result - increasing the noise immunity of the receiver signals QAM-16 by increasing reliability and reducing the time to eliminate the false grips phase is achieved by performing the following operations on the signal:

- restore coherent carrier signal frequency QAM-16;

for each demodulated signal point signal QAM-16 define the projections of this point on the quadrature axis, educated restored coherent carrier frequency;

depending on the values of the projections of each signal point on the quadrature axis decide adopted the tetrad of information symbols {ABCD} and pass it to the output of the demodulator;

for each signal point determined, out there, beyond the limit value, the values of the projections of each signal is Inoi point for each signal axis;

- install the cyclical interval of account m clock cycles;

- if the value of the projection of the signal point is beyond the limit value (i.e. U<-2 or U>2), separately for each of the quadrature axes count the number of such signal points for a period of account of m clock cycles;

- calculate the total for the two quadrature axes number of such signal points for a period of account of m clock cycles;

- separately and combined two axes estimated numbers of signal points, the projection of which on the quadrature axis is outside the limit value (U<-2 or U>2)evaluate the error probability at the output of the demodulator;

- determine the sign on the in-phase (quadrature) axis projections of those signal points that are outside of the limit values (U<-2 or U>2) I / q (in-phase) axis and count the number of Nand N;

- compare separately calculated for each of the quadrature axes the number of signal points of the Nand Nwith the limiting value of NAve;

- in case of exceeding any of the calculated values of Nand Nlimit values of NAvemake a conclusion about the incident a false grip and the angle of phase error (-23° or +23°);

on the basis of the calculated values of the phase angle error (ϕLZ =+23° or ϕLZ=-23°) in block compensation of phase errors commute such a phase shifter in the circuit of the recovered carrier (-23° or +23°), which compensates for the phase error, a false capture, i.e. eliminates false grip.

This is achieved by the signal receiver shestnadtsetirichnoe quadrature amplitude manipulation includes first and second filters are low pass, ten Comparators, the first and second elements And the phase shifter 90°, the carrier recovery block, the six elements, OR four counter, the first and second blocks of the comparison register and the first and second phase detectors, the first inputs of which are connected and are the input devices. The second input of the first phase detector connected to the input of the phase shifter 90°, the output of which is connected to a second input of the second phase detector, the outputs of the first and second phase detectors are connected respectively to the inputs of the first and second low-pass filters, the outputs of the first and second low-pass filters connected respectively to the inputs of the first and fourth Comparators. The inputs of the first, second, third, seventh and eighth Comparators are connected, and the outputs of the seventh and eighth Comparators are connected to the inputs of the first element OR the output of which is connected to the input of the first counter and the first input of the second e is ment OR the output and second input of which is connected respectively with the input of the second counter and the input of the third counter. The input of the third counter connected to the output of the third element OR, the inputs of which are connected to the outputs of the ninth and tenth comparator whose inputs are connected to inputs of the fourth, fifth and sixth Comparators, the outputs of the second and fifth Comparators are respectively the first and second outputs of the device. The outputs of the first and third Comparators are connected respectively to the first input of the fourth element OR direct input of the first element And the inverse of the input and output of which are connected respectively with the output of the second comparator and a second input of the fourth element, OR whose output is the third output, the fourth output which is the output of the fifth element OR, the inputs of which are connected respectively to the outputs of the sixth comparator and the second element And to direct and inverse inputs of which are connected respectively to the outputs of the fourth and fifth Comparators. The second inputs of the first and second units of comparison is connected to the output of the register, the outputs of the first and second units of comparison are connected with the inputs of the sixth element OR the output of the fourth counter connected to the reset inputs of the first, second and third counters.

According to the invention in not is entered on the third, the fourth, fifth and sixth elements And, seventh and eighth elements OR, fifth and sixth counters and compensation unit phase error, and outputs the seventh, eighth, ninth and tenth Comparators respectively connected with the first inputs of the third, fourth, fifth, and sixth elements And the second inputs of the third and fourth elements And is connected to the output of the fifth comparator, the second input of the fifth and sixth elements And is connected to the output of the second comparator. The first and second inputs of the fourth and sixth elements are inverted outputs of the third and fourth elements And are connected respectively with the first and second inputs of the seventh element OR the output of which is connected to the fifth input of the counter, the output of which is connected to the first input of the first unit of comparison. The outputs of the fifth and sixth elements And are connected respectively with the first and second inputs of the eighth element OR the output of which is connected to the sixth input of the counter, the output of which is connected to the first input of the second block of comparison, the fifth input of the compensation of the phase error is a control input device. The first, second, third and fourth inputs of the block compensation of phase errors respectively connected with the output of the first unit of comparison, the output of the second unit of comparison, the output of the sixth element OR output unit for restoring the Oia carrier, an input connected to the input of the device. The output of the fourth counter connected to the reset inputs of the fifth and sixth counters.

Another difference is that the compensation unit phase error contains three trigger, two Phaser, three switches, the inverter and adder whose output is the output of the compensation unit phase error, the first inputs of the first, second and third triggers are connected respectively with the first, second and third inputs of the block compensation of phase errors, a fourth input connected to the inputs of the first and second phase and a second input of the third switch, the outputs of the first and second phase respectively connected with the second inputs of the first and second switches, the first inputs of which are connected respectively to the outputs of the first and second triggers, exit the third trigger through the inverter connected to the first input of the third switch, the outputs of the first, second and third switches are connected respectively with the first, second and third inputs of the adder, the second inputs of the first, second and third triggers are the fifth input of the compensation of the phase error.

New nodes and blocks allow you to perform new operations on signals: to count for a period of account of m clock cycles the number of those signal points, which allow you to define were the inu phase mismatch in the case of the incident a false grip (+23° or -23°).

In that case, if the device identified by the false grip, depending on the type of false capture (i.e. the magnitude of the phase mismatch in the block compensation of phase error (BCPO) is connected to (communicated by) such a phase shifter in the circuit of the recovered carrier, which eliminates this false grip.

However, unlike the prototype, in the inventive device uses a preset algorithm to eliminate false grip, not based on the failure of synchronization of the carrier recovery block, and upon payment of the calculated phase angle errors.

This increases the robustness of the claimed device, because it allows to reliably remove a false grip, and in the minimum possible time.

Figure 1 shows a functional diagram of the demodulator QAM-16.

Figure 2 shows a functional diagram of BCFA.

Figure 3 shows the signal points of the ensemble QAM-16, and the corresponding optimal areas of decision making, where the symbols U3and U4marked quadrature signal axis, educated restored coherent carrier frequency.

Figure 4 illustrates the principle of measurement error probability at the output of the demodulator, where the symbols S1-S16designated signaling points of the ensemble QAM-16.

Figure 5 illustrates when the citu detection and elimination of false grips where the white dots correspond to true engagement, and black is false for the case ϕLZ=+23°.

Table 1 presents the thresholds of the Comparators.

The signal receiver QAM-16 contains the first, second phase detectors 1, 2, first, second filters 3, 4 lower frequencies, the first-tenth Comparators 5-14, the first, second elements 15, 16, the phase shifter 17 90°, block 18 recovery of the carrier, the first five elements OR 19-23, first, second, third counters 24-26, the first comparison block 27, the second block 28 comparison register 29, the sixth element OR 30, the side 31 of the compensation of the phase error, the fourth counter 32, the third to sixth elements And 33-36, seventh and eighth elements 37, 38.

The block 31 compensation of phase errors includes first through third triggers 39-41, the first and second phasers 42, 43, the first through third switches 44-46, the inverter 47 and the adder 48.

The device comprises fifth and sixth counters 49, 50.

The first inputs of the first and second phase detectors 1 and 2 are connected and are the input of the second input of the first phase detector 1 is connected to the input of the phase shifter 17 90°, the output of which is connected to a second input of the second phase detector 2, the outputs of the first and second phase detectors 1 and 2 are connected respectively to the inputs of the first and second low-pass filters 3 and 4. The outputs of the first and second low-pass filters 3 is 4 are connected respectively to the inputs of the first and fourth Comparators 5 and 8, the inputs of the first, second, third, seventh and eighth Comparators 5, 6, 7, 11, 12 are connected, and the outputs of the seventh and eighth Comparators 11 and 12 are connected to the inputs of the first element OR 19, the output of which is connected to the input of the first counter 24 and the first input of the second element OR 20, the output and second input of which is connected respectively with the input of the second counter 25 and the input of the third counter 26. The third input of the counter 26 is connected to the output of the third element OR 21, the inputs of which are connected to the outputs of the ninth and tenth Comparators 5 and 6, the inputs of which are connected to inputs of the fourth, fifth and sixth Comparators 8, 9, 10, and the outputs of the second and fifth Comparators 6 and 9 are, respectively, the first and second outputs, the outputs of the first and third Comparators 5 and 7 are connected respectively to the first input of the fourth element OR 22 and the direct input of the first element And 15, an inverse input and output of which are connected respectively with the output of the second comparator 6 and a second input the fourth element OR 22, the output of which is the third output, the fourth output which is the output of the fifth element OR 23, the inputs of which are connected respectively to the outputs of the sixth comparator 10 and the second element And 16, to direct and inverse inputs of which are connected respectively to the outputs of the fourth and Pato what about the Comparators 8 and 9, the second inputs of the first and second blocks comparison 27 and 28 connected to the output of the register 29. The outputs of the first and second units of comparison, 27 and 28 are connected to inputs of the sixth element OR 30, the output of the fourth counter 32 is connected to the reset inputs of the first, second, third, fifth, and sixth counters 24, 25, 26, 49, 50. The outputs of the seventh, eighth, ninth and tenth Comparators 11, 12, 13 and 14 are connected respectively to the first inputs of the third, fourth, fifth, and sixth elements 33, 34, 35, 36, the second inputs of the third and fourth elements 33, 34 is connected to the output of the fifth comparator 9, the second inputs of the fifth and sixth elements 35, 36 connected to the output of the second comparator 6, the first and second inputs of the fourth and sixth elements And 34, 36 are inverted. The outputs of the third and fourth elements 33, 34 are connected respectively with the first and second inputs of the seventh element OR 37, the output of which is connected to the fifth input of the counter 49, the output of which is connected to the first input of the first unit of comparison 27, the outputs of the fifth and sixth elements 35, 36 are connected respectively with the first and second inputs of the eighth element OR 38, the output of which is connected to the sixth input of the counter 50, the output of which is connected to the first input of the second unit 28 comparison. The fifth input of the compensation of the phase error 31 is a control input of the first, second the third the third and fourth inputs of the compensation unit phase error 31 are connected respectively with the output of the first Comparer 27, the output of the second Comparer 28, the output of the sixth element OR 30 and the output of the carrier recovery block 18, the inlet of which is connected to the input device.

The compensation unit phase error 31 the output of the adder 48 is the output of the compensation unit phase error 31, the first inputs of the first, second and third trigger 39, 40, 41 are connected respectively with the first, second and third inputs of the compensation unit phase error 31, a fourth input connected to the inputs of the first and second phase 42, 43 and a second input of the third switch 46, the outputs of the first and second phase 42, 43 are connected respectively with the second inputs of the first and second switches 44, 45, the first inputs of which are connected respectively to the outputs of the first and second triggers, 39, 40 the output of the third trigger 41 through the inverter 47 is connected to the first input of the third switch 46, the outputs of the first, second and third switches 44, 45, 46 are connected respectively to the first, second and third inputs of the adder 48, the second inputs of the first, second and third trigger 39, 40, 41 are the fifth input of the compensation of the phase error 31.

Triggers 39-40 in BKFO 31 are RS-triggers, and the emergence of logical units and the first inputs leads to its latching (latching) on their outputs. The second inputs trigger inputs are reset to the zero state.

The first and second phasers 42 and 43 perform the rotation angle respectively +23° -23°.

The switches 44, 45 and 46 are performed as managed keys: if there are units on their first (control) input they transmit a signal on its second input to output (switch closed), otherwise (zero on the first control input) to the output signal does not arrive (switch closed).

The device operates as follows. In the initial time by the fifth input unit 31 (see Fig 1) is the impulse that pushes the trigger 39-41 (see figure 2) to the zero position. In accordance with this, the switch 46 connects the output of block 18 through the adder 48 with the second inputs of the FD 1 and 2. Let the demodulator input signal QAM-16 in the form:

where a, b, C, D - choose from a variety of /-1; +1/ information symbols:

w0- carrier frequency signal.

The signal representation QAM-16 in the form of (1) is in good agreement with the superposition principle signal QAM-16.

Between transmitted information symbols /-1; +1/ each discharge quadruplet ABCD and bits of Fallot bits in each signal point of the ensemble QAM-16 there is a simple line: symbol -1 corresponds to bit 0, and the symbol of +1 corresponds to bit 1.

From this is follows, in the tetrad bits assigned to each signal point of the ensemble QAM-16 in figure 3, the first bit corresponds to the symbol a, second -, third - and fourth - D. Thus, the tetrad 0101 means the transfer of the following symbols: A=-1, B=+1, C=-1, D=+1.

Let us denote the voltage at the output of the filter 3 as U3the voltage at the output of the filter 4 as U4(figure 3). The data voltage U3and U4represent the projection of the signal points respectively in-phase and quadrature axis.

The output of any of the Comparators is formed logical 1, if the level at its input exceeds the threshold (and Vice versa).

The thresholds of the Comparators are shown in table 1.

From the map the location of the signal points of the ensemble QAM-16, and areas of decision-making figure 3 it follows that the output of the comparator 6 is formed character And, at the output of the comparator 9 is the symbol of the Century

Education character follows the rule:

where E and F are the binary data at the output of the Comparators 5 and 7, respectively;

+ - the symbol of the Boolean operations of addition (OR).

The formation of D follows a similar rule.

When this blocks 15, 22 and 16, 23 form an equation of the form (2) for definitions of symbols C and D, respectively.

Consider how data recovery when receiving, for example, the signal is Noah points S 8(see figure 4). When the reception signal point S8the outputs of the LPF LPF 3 and 4 voltage will be such that the trigger Comparators 6 and 9 with zero thresholds and the first output of the demodulator will appear bit 1 (=+1), on the second output will appear bit 1 (=+1). Since the comparator 5 also works (because the voltage U3exceeds the threshold for comparator 5 value +1), then through the element OR 22 on the third output of the demodulator will appear bit 1 (=+1).

The comparator 10 does not work for U4does not exceed the threshold for comparator value 1. The comparator 8 is triggered, because the threshold is 1, but the element And 16 will be closed by the inverted input signal from the output of the comparator 9 and the result at the output of the OR element 23 will be formed bit 0 (D=-1). This set of bits 1110 completely match the code in figure 2 for a point S8(figure 4).

When the transmission of any signal point S1-S16logic Comparators 5-14, items, And 15, 16 and elements OR 22, 23 is such that the first output device to generate a symbol And, on the second output symbol, the third symbol, the fourth - D (see figure 1) in accordance with the selected manipulation code (see figure 3).

Consider how the measurement error probability at the output device.

Because the inventive receiver decides on the ideal criterion on which ludites, errors when receiving signals ensemble QAM-16 occur only when the transmitted signal point under the influence of noise hits on the signal plane in the area of decision making, the respective other signal point. So, when the reception symbol(see figure 4), the receiver decides in favor of the nearest authorized signal point S4and the error does not occur. If under the influence of noise transmitted point takes the placei.e. is the solution of another signaling point, the decision is made in favor of the point S3(see figure 4), and the output device error occurs in the symbol.

The fact that this error when receiving a completely random information signal (no correlation between characters) in no way can be found. However, if we assume that the probability of intersection of the vector of noise more than one border at a crucial network (figure 4) can be neglected, which is always carried out in practice, then, in this case, watching the hit points in the secondary zone, it is possible to measure the likelihood of errors.

Indeed, the stay pointthe shaded area does not cause an error, because the decision is made in favor of a true pointthat one is to you an idea about the current input vector noise that when passing any of the points of S1-S3, S5-S7, S9-S11, S13-S15would result in an error.

Measurement of the probability of error in the inventive device is as follows.

The probability PGUstay points in the left half-plane bounded by a straight line (GU), is determined by the formula:

where PS1=PS5=PS9=PS13- a priori probability of transmitting signal points S1, S5, S9, S13;

PWthe probability that the noise will lead the transmitted point left abroad GU.

Since all of the signal points of the ensemble QAM-16 is transmitted with the same probability equal to 1/16, formula 3 can be converted to the form:

Because noise "leads" signal point from their true position in the neighbouring area of decision-making with the same probability (channel symmetric), then

where POsh- the probability of error at the output of the demodulator.

Substituting the expression (5) in expression (4), we have:

Similarly, the probability of stay points in the right half-plane bounded by a straight KQ,

Since the event consisting in noorden the signal and point to the left from the straight GU or right from straight KQ, incompatible, then the probability of what will happen to any of these events, is the sum of the probabilities defined by the formulas (4) and (7)

The fact of appearance of the signal points to the left from the straight GU is determined by the triggering of the comparator 12 with the threshold-2. The fact of appearance of the signal point to the right from a direct KQ is determined by the triggering of the comparator 11 with a threshold of +2. Direct GU and KQ cross the x-axis in figure 3 is exactly at the points -2 and +2. Hence, integrating over the element OR 19, the outputs of the Comparators 11 and 12, it is possible to measure the probability of error in the character at the given quadrature channel (axis U3figure 3).

The stream of pulses from the output of the OR element 19 is supplied to the counter 24. Multiplying by a factor equal to 8, the counter 24 in accordance with the formula (8), we can determine the probability of error in the symbols a and C at the output of the demodulator.

Similarly, the probability of error in the symbols b and D can be determined from the counter 26 via factor of 8).

Final probability for all symbols a, b, C, D errors can be identified by the counter 25, multiplying them by 4.

The probability of error is defined as:

where ROsh- the probability of error at the output of the demodulator;

N25counter 25;

m duration interval accounts in the measure.

Interval account m clock cycles defined by the fourth counter 32, is chosen for various reasons, is equal to m=(103÷1012)·16. At the end of each interval account counter 32 resets (clears) the state counters 24-26 through their reset inputs.

Consider how the false grip in the inventive receiver. The false grip in the inventive device is based on the premise that the counters 24 and 26, and 49 and 50, in a state of true and false seizures, differ fundamentally:

- capture the true reading, for example, the third counter 26, proportional to the value of

- in a state of false capture readings of the same counter 26 is proportional to the value of.

From this it follows that when properly selected interval account m and the real signal-to-noise ratio at the input deviceanddiffer dramatically (by several orders of magnitude).

For example, the signal-to-noise ratio at the input of the device is about 16 dB, respectively, POsh≈10-5. Let m=16·105.

Then in condition true capture

In a state of false capture

Let us show that for any signal-to-noise ratio in a state of true and false grabs third readings of the counter 26 (as of the first counter 24) differ by several orders of magnitude, which allows for values of N26(and N24) accurately judge the incident a false grip.

When false the capture phase error ϕLZ=23°all points of the ensemble QAM-16 in quadrature axes U3and U4occupy the new position (see figure 5). Thus, for example, pointgoes to the point. Consider how reduced when the projection of the point S4axle U4.

Able capture the true projection of the pointaxle U4is U4=1,5.

In a state of false capture the projection of the pointaxle U4can be found from the following geometric considerations:

Hence we obtain that U4=1,95.

Thus, in a state of true capture the distance from the pointto the boundary of U=2 is the value of 2-1,5=0,5; in a state of false capture the distance from the pointto the boundary of U=2 decreases to a value of 2-1,95=0,05. That the reduction of the distance to the boundary of the operation of the Comparators is equivalent to the deterioration of the signal-to-noise ratio (when the probability of errors) on the value of .

The same dependence of error probability on the signal-to-noise ratio for signal QAM-16 (see, for example, Peer K. Wireless digital communication. - M.: Radio and communication, 2000. - S. 237. - RES) [7], is that in a real working relationship signal-to-noise ratio (20 dB) POshis the value less than 10-5; deterioration of the signal-to-noise ratio of 20 dB gives the value of POshmore than 10-1. Accordingly, and third readings of the counter N26in two cases also differ by several orders of magnitude, and that gives the ability to reliably identify the type of seizure (true or false).

All of the above provisions of the fair to the other extreme diagonal points (S1; S13; S16),and for the first counter 24.

The same considerations apply to counters 49 and 50, the status of which is compared with a threshold value of NAve. Use in the inventive device special signals, i.e. States of the counters, the values of which are in sharp contrast to the type of the capture phase (true or false)allows to reliably identify false grips.

Consider how in the inventive device is determined by the value of the phase angle error ϕLZonce installed, the actual fact false grip.

From figure 5 it is seen that if the signal is through the plane to form a zone, designated as Zand Z, then the probability of signal points in these zones you can judge the value of the phase error in the mode false grip.

Really abnormal (above the threshold), the probability of signal points in zone Zindicates the incident a false capture phase error ϕLZ=+23° (for zone Zrespectively ϕLZ=-23°).

In accordance with the logic blocks 33-38 counting signal points falling in the zone Zoccurs in the counter 50, and falling within the zone Zin the counter 49.

The output of the first Comparer 27 logical unit is formed when N49〉NCR. Same is true for the second unit 28 comparison.

In line with this, the presence of a one at the output of the sixth element OR 30 indicates the incident a false grip, and the levels of the signals at the outputs of the blocks 27 and 28 allow you to specify (set) the value of the phase error in the case of a false grip.

Unit output unit 27 (28) indicates the presence of a false grip with phase error ϕLZ=-23° (ϕLZ=+23°).

Let, as shown in figure 5, has been a false grip with ϕLZ=+23°.

Then in zone Zfor the interval count to get the number of the creation points excess of NPRthe second and third inputs of BKFO 31, there will be a logical unit.

It will be clicked triggers 41 and 40. The switch 46 is closed and the switch 45 is closed and, thus, the circuit is restored, the carrier frequency will include additional phase shifter 43 with phase shift ϕ=-23°that to compensate for the angle of false capture, i.e. to its elimination.

Used in the inventive device preset procedure to eliminate the false seizures that do not result in forced disruption of synchronization and re-entry into synchronism, improves the reliability of eliminating false seizures and reduces solution time compared to the prototype.

Sources of information

1. RF patent №2013018, IPC 5 H 04 L 27/22, publ. BI No. 9, 15.05.94,

2. RF patent №2019054, IPC 5 H 04 L 27/34, publ. in BI No. 16, 30.08.94,

3. Parkhomenko, N., Botashev BM, Shelepin Y.S. Research schemes recovery of the carrier frequency signals quadrature amplitude manipulation // Problems of Radioelectronics. Ser. IDW. - M.: NIEIR. - 1991. - VIP, p.65-76.

4. RF patent №2020767, IPC 5 H 04 L 27/22, publ. in BI No. 18, 30.09.94,

5. RF patent №2019053, IPC 5 H 04 L 27/34, publ. in BI No. 16, 30.08.94,

6. RF patent №2235440, IPC 7 H 04 L 27/22, publ. in BI No. 24, 27.08.04, prototype.

7. Peer K. Wireless digital communication. - M.: Radio and communication, 2000. - s. - is.

Table 1

The signal receiver shestnadtsetirichnoe quadrature amplitude manipulation
ComparatorLevel (threshold) trigger
The first 5+1
The second 60
The third 7-1
Fourth 8-1
Fifth 90
Sixth 10+1
Seventh 11+2
Eighth 12-2
The ninth 13+2
Tenth 14-2

1. The signal receiver shestnadtsetirichnoe quadrature amplitude manipulation, containing the first and second filters are low pass, ten Comparators, the first and second elements And the phase shifter 90°, the carrier recovery block, the six elements, OR four counter, the first and second blocks of the comparison register and the first and second phase detectors, the first inputs of which are connected and are the input of the second input of the first phase detector connected to the input of the phase shifter 90°, the output of which is connected to a second input of the second phase detector, the outputs of the first and second phase detectors connected respectively with the inputs of the first and the which low-pass filters, the outputs of the first and second low-pass filters connected respectively to the inputs of the first and the fourth comparator, the inputs of the first, second, third, seventh and eighth Comparators are connected, and the outputs of the seventh and eighth Comparators are connected to the inputs of the first element OR the output of which is connected to the input of the first counter and the first input of the second element OR the output and second input of which is connected respectively with the input of the second counter and the input of the third counter, the input of the third counter connected to the output of the third element OR, the inputs of which are connected to the outputs of the ninth and tenth comparator whose inputs are connected to inputs of the fourth, fifth and sixth Comparators, the outputs of the second and fifth Comparators are respectively the first and second outputs of the demodulator, the outputs of the first and third Comparators are connected respectively to the first input of the fourth element OR direct input of the first element And the inverse of the input and output of which are connected respectively with the output of the second comparator and a second input of the fourth element, OR whose output is the third output of the demodulator, the fourth output which is the output of the fifth element OR, the inputs of which are connected respectively to the outputs of the sixth comparator and the second element And to direct and INVERS the th inputs of which are connected respectively to the outputs of the fourth and fifth Comparators, the second inputs of the first and second units of comparison is connected to the output of the register, the outputs of the first and second units of comparison are connected with the inputs of the sixth element OR the output of the fourth counter connected to the reset inputs of the first, second and third counters, characterized in that it introduced the third, fourth, fifth and sixth elements And, seventh and eighth elements OR, fifth and sixth counters and compensation unit phase error, and outputs the seventh, eighth, ninth and tenth Comparators respectively connected with the first inputs of the third, fourth, fifth, and sixth elements And the second inputs of the third and fourth elements And is connected to the output of the fifth comparator, the second input of the fifth and sixth elements And is connected to the output of the second comparator, the first and second inputs of the fourth and sixth elements are inverted outputs of the third and fourth elements And are connected respectively with the first and second inputs of the seventh element OR the output of which is connected to the fifth input of the counter, the output of which is connected to the first input of the first unit of comparison, the outputs of the fifth and sixth elements And are connected respectively with the first and second inputs of the eighth element OR the output of which is connected to the sixth input of the counter, the output of which is connected to the first the input of the second block of comparison, the fifth shotbloks compensation of phase error is a control input device, the first, second, third and fourth inputs of the block compensation of phase errors respectively connected with the output of the first unit of comparison, the output of the sixth element OR the output of the carrier recovery block, the inlet of which is connected to the input device, the output of the fourth counter connected to the reset inputs of the fifth and sixth counters.

2. The device according to claim 1, wherein the compensation unit phase error contains three trigger, two Phaser, three switches, the inverter and adder whose output is the output of the compensation unit phase error, the first inputs of the first, second and third triggers are connected respectively with the first, second and third inputs of the block compensation of phase errors, a fourth input connected to the inputs of the first and second phase and a second input of the third switch, the outputs of the first and second phase respectively connected with the second inputs of the first and second switches, the first inputs of which are connected respectively to the outputs of the first and second triggers, exit the third trigger through the inverter connected to the first input of the third switch, the outputs of the first, second and third switches are connected respectively with the first, second and third inputs of the adder, the second inputs of the first and second and third triggers are the fifth input BL is ka compensation of phase error.



 

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