Method for transmitting and receiving signals of quadrature amplitude modulation, system for realization of method, machine-readable carrier and method for using method for synchronization of receipt of signals of quadrature amplitude modulation

FIELD: signals transmission equipment engineering.

SUBSTANCE: use of given method in systems for transmitting and receiving signals of quadrature amplitude modulation with low bearing frequency synchronization threshold makes it possible to decrease demodulation threshold due to provision of low synchronization threshold by bearing frequency. Result is achieved by adding to pack of M m-level quadrature amplitude modulation symbols of previously given symbols, part of which does not change from pack to pack, and another part is periodically inverted in some of packs. Due to that at receiving side components of quadrature amplitude modulation signals are singled out, appropriate for additional previously given symbols (frequency of which are known). On basis of these components, inversion frequency is determined, which provides for removal of ambiguousness in adjustment of receipt synchronization frequency, thus making it possible to approach Shannon threshold closely.

EFFECT: decreased demodulation threshold.

4 cl, 1 tbl, 9 dwg

 

The technical field to which the invention relates.

This invention relates to techniques for transmitting signals. Specifically this invention relates to a method and system for transmitting and receiving signals, quadrature amplitude modulation with a low threshold sync carrier frequency.

The level of technology

During transmission and reception of signals, modulated in one way or another, very important characteristic is the threshold demodulation, i.e. the ratio of signal power to noise power (C/W), in which the stops to stand out bearing fluctuation of the received signal, which leads to disruption of reception. The threshold demodulation significantly depends on the type of modulation used on the transmission side, and the type of error-correcting coding.

From theory it is known that the effectiveness of any communication system is determined by its frequency and energy resource, i.e. the frequency band occupied by the signal, and its capacity to provide the required transmission and reception of information. In the General case this dependence of the rate of transmission and reception of the information on the width of the frequency spectrum and energy of the signal is determined by the Shannon formula:

where C is the speed of sending and receiving information, In - the width of the frequency spectrum of the signal being transmitted in the communication channel, RWith- power of the input signal is the receiver, PW- noise power given to the receiver input, in-band In frequency.

Modern communication systems are modem technology, built for a specific speed of information transmission. The most commonly used are the following modulation types:

in satellite communications: QPSK, 8PSK, 16QAM, 32QAM;

- in microwave communication lines: BPSK, QPSK, 8PSK, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM;

- in cable communication lines: QPSK, 16QAM, 64QAM, 256QAM;

- telephony: from 16QAM to 16384QAM.

The most commonly used types of error-correcting coding used in modern modems are coding Viterbi (convolutional)coding codes reed-Solomon, trellis coding (TCM - Trellis Code Modulation), turbomotive [1] and LDPC (Low Density Parity Check Codes - codes with parity low density) [3, 4]. The last is the most effective form of error-correcting coding with a loss of only 0.8-1.5 dB to attain a maximum speed of information transmission, defined by the formula (1). Table 1 shows the characteristics of the LDPC encoding for different speeds of coding and modulation types.

Obstacle to the implementation of the achieved performance of the LDPC encoding in modern communication systems are too high demodulation thresholds (thresholds carrier recovery) in existing demodulators. So for demodu is acii species existing QPSK demodulator begin to synchronize at a carrier frequency when the ratio s/n of 0 dB, and for modulation type CAM (16QAM) - when the ratio s/n of about +8,9 dB for modulation CAM (32QAM) - at +12,7 dB [2].

From Table 1 it is evident that in order to realize the full capabilities of the LDPC encoding of the signal is QPSK with coding rate 1/4 demodulator must operate with a ratio of

when he breaks down already at 0 dB. For 16QAM signal with the same coding rate 1/4 demodulator must operate consistently with a ratio of

and he breaks down already at +8,9 dB etc.

The main reason for this is the fact that the recovery of the carrier frequency in modern QPSK demodulators (FM) and QAM (QAM) is nonlinear. In the spectra of signals using such modulation schemes like QPSK (PM), 8PSK (FM), 16QAM (CAM) and the like, does not contain a residue of the carrier frequency, so her coherent oscillation is recovered from the received signal through a nonlinear transformation and subsequent filtration. But any nonlinearity limits the threshold the carrier recovery. If the allocation system carrier was linear, then the threshold demodulation would be less than -3 dB, which would allow the demodulator to maintain their characteristics until the ratio

So, currently known systems SIP is housoukyoku encoding, for example, the LDPC encoding, turbomotive allow quite close to the threshold Shannon. However, his achievement is hampered by lack of demodulators capable of operating at such low relationship s/n due to the lack of synchronization, which requires the separation of the carrier oscillation of the signals using such modulation, as FM, FM, CAM, etc. using non-linear transformation followed by filtration. This transformation is the method of frequency multiplication, which can realize erection in the M-th power of the input signal (a fourth - FM, eighth - FM etc). But in the same degree erected and noise, which limits the recovery of the carrier. In addition, there is another phase ambiguity, the elimination of which requires the introduction of the transmitted signal relative encoding, contributing additional energy losses.

Difficulties associated with the use of modulation type FM, FM and FFM, demonstrate U.S. patent No. 6697440 (24.02.2004) and lined with Japan's bid No. 2000-032072 (28.01.2000).

As already noted, in modern communication systems, among other modulation techniques used and quadrature amplitude modulation (QAM or QAM).

So, paved the application of Japan No. 2001-237908 (31.08.2001) describes the allocation system clock from the signal of the CAM, both the providing quasisynchronous detection. In U.S. patent No. 6717462 (06.04.2004) and 6727772 (27.04.2204) describes methods and systems for transmitting and receiving QAM signals with tunable carrier frequency. However, both of these patents provide only simple processing of conventional QAM signal. The disadvantage of these analogues is the inability to lower the threshold demodulation for approaching the threshold Shannon.

The invention

The purpose of this invention is to provide such a method and system for transmitting and receiving QAM signals, which would reduce the threshold demodulation by providing low threshold sync carrier frequency.

To achieve this, the proposed method and implements his system for transmitting and receiving QAM signals according to the present invention. The basic principle of this invention is the addition of a pack of M m-level QAM symbols predefined symbols, some of which does not change from batch to batch, and the other part is periodically inverted in some of the packs. Due to this, at the receiving side are allocated to components of the QAM signal corresponding to the additional pre-defined characters (whose frequencies are known). On these points is determined by the frequency of inversion, which ensures the elimination of ambiguity in the tuning frequency synchronization reception. This allows close p is ablitites to the threshold Shannon.

Detail objects and features of the present invention shown in the accompanying claims. For a better understanding of the claimed group of inventions is a detailed description.

Brief description of drawings

The following detailed description is illustrated in the accompanying drawings, in which identical or similar elements have the same reference position.

Figure 1 is a notional diagram illustrating possible signal used in the system of the present invention.

Figure 2 is a block diagram of a transmitting system for transmitting and receiving QAM signals according to the present invention.

Figure 3 is a block diagram of a reception system for transmitting and receiving QAM signals according to the present invention.

Figure 4 illustrates the implementation of a digital quadrature demodulator in block quadrature conversion of the reception side system of the present invention.

5 to 7 illustrate the implementation of, respectively, the first and third blocks, phase-locked loop frequency selector clock frequency of the receiving side of the system of the present invention.

Fig illustrates the execution of the block of formation of frequency components in the selector clock frequency of the receiving side of the system of the present invention.

Detailed description of the invention

Type of signal, the use of which has been created in the system transmitting and receiving QAM signals according to the present invention, shown in figure 1. The spectrum of this signal in channel I is a set of frequency components spaced at a predetermined frequency, alternating with pilot signals (figa). Considering the signal in the Q channel possible signal constellations for different types of modulation have the form shown figb.

System for transmitting and receiving QAM signals according to the present invention in General consists of a transmitting side and a receiving side, connected by a communication channel.

Figure 2 presents the block diagram of the transmitting system transmitting and receiving QAM signals according to the present invention.

The transferor contains shaper 1 m-level symbols, designed to convert the original information bit sequence of characters, with the following frequency kf1in the sequence of m-level symbols, where m=2k, k=2, 3, ..., with the following first clock frequency f1. This first clock frequency is generated in the imaging unit 2 clock frequency of the transmitting side to the first output included in it block 3 dividing the frequency of arriving at its input signal clock frequency kf1which accompanied the original bit sequence of characters.

The separator 4 channels is intended for dividing the information sequence m-level symbols, the shaper 1 on channel I of the transferor with an even m-level symbols and the Q channel of the transmitting side with odd m-level symbols. The repetition rate m-level symbols in each of the channels I and Q of the transmitting side is equal to f1/2, is formed on the second output unit 3 frequency division.

The first and second formers 5 and 6 packs are designed each for storing packs of M m-level symbols in the interval

where 2L-1<M<2L, L=5, 6, 7, ..., in an appropriate channel I and Q transferor and to complement each pack of M m-level symbols n predetermined symbols to the total number M+n=2L. On the formers 5, 6 signal with a frequency of 1/GS of the third output unit 3 frequency division.

In each of the channels I and Q transferor has two multiplier. First and second multiplier products 7 and 8 are each for inverting values of m-level symbols in odd pairs of packets in the channels I and Q of the transmitting side, respectively. The third and fourth multiplier products 9 and 10 are each to invert half of the added values in each odd couple packs of pre-defined symbols in the channels I and Q of the transmitting side, respectively. The signal, ensuring the inverting and served with the fourth output unit 3 frequency division, is

ie is a meander meant with the s +1 and -1 and with a frequency of 1/4T.

The third and fourth formers 11 and 12 packs are designed each to separate each pack of M+n symbols in half in an appropriate channel I and Q transferor.

The first to fourth blocks 13-16 inverse fast Fourier transform (BPA) are used to replace each pack ofcharacter set of M+n time samples using BPA.

First-fourth parallel-to-serial converters 17-20 are used to convert each of the channels I and Q of the transmitting side of each of the sets of M+n time samples obtained from blocks 13-16 BPA, respectively, in the corresponding sequence of M+n time samples with the second clock frequency

This frequency is obtained in the imaging unit 2 clock frequency from the first output unit 21 frequency multiplication, the input of which is applied a clock frequency kf1the initial sequence of bit characters.

The first and second blocks 22, 23 of the Hilbert transform are designed for each rotation phase π/2 for all frequencies of the spectrum of the corresponding sequence of M+n time samples in the channel I or Q of the transmitting side, respectively. The first and second blocks 24, 25 delays are each for delaying the other of the sequences of M+n temporary the samples in an appropriate channel I or Q transferor at the time of processing in the corresponding block 22, 23 the Hilbert transform.

The first and second pouchetii adders 26 and 27 are each to join in an appropriate channel I and Q transferor both received sequence of M+n time samples from the same block 22, 23 of the Hilbert transform and the eponymous block 24, 25 delay in one sequence of the same length.

The first and second blocks 28 and 29 of the filter are designed each for filtering a merged sequence with the same petschenig adders 26 and 27, respectively. This filtering is carried out with the second clock frequency f2block 21 multiplying the frequency range from 0 to f2/2 in an appropriate channel I and Q transferor.

Shaper 30 signal transmission is designed for signal transmission from the filtered sequence of the blocks 28, 29 in the channels I and Q of the transmitting side. In the imaging unit 30 in the first and second multiplier products 31, 32 is the multiplication of the filtered sequences with cosine and sine signals of the carrier frequency and adding results of the multiplication unit 33 adds. The output of block 33 in addition, the imaging unit 30 is supplied to the communication channel (not shown).

Figure 3 presents the block diagram of the receiving side of the system transmitting and receiving QAM signals on n the present invention.

Reception side, the entrance of which is connected to the communication channel, contains the usual for any receiver means of amplification, filtering, and conversion to an intermediate frequency, which is not shown in figure 3, but are assumed to be available. Further, the reception side contains the block 41 of the quadrature conversion, designed to separate the received signal into a sequence of digital samples of the channel I of the receiving side and the Q channel of the receiving side. In the receiving side includes a selector 42 clock frequency that is used to select the clock frequency by using the signals in the channels I and Q reception side. The implementation of the selector 42 clock frequency will be given below.

The first and second buffer units 43 and 44 are each for dividing a sequence of digital samples in an appropriate channel I and Q reception side in packs of M+n times, and to remember these packages.

The first and second blocks 45 and 46 of the direct Fourier transform (PPF) is designed for each implementation in an appropriate channel I and Q reception side PPF over bundles on M+n samples and to obtain pairs ofm-level samples.

The first and second highlighters 47 and 48 samples are used for each allocation of M m-level samples from each pairm-urovnevy the samples in an appropriate channel I and Q reception side. These M samples correspond to samples that arrived at the input of the transmitting side.

The first and second blocks 49 and 50 of the resolve phase ambiguities are designed each to resolve the phase ambiguity in the signal of the corresponding channel of the channels I and Q reception side. The first and second converters 51 and 52 in the m-level sequence are each to construct a sequence of m-level samples in the corresponding channel of the channels I and Q reception side from the output signal of the same unit 49 and 50 resolve the phase ambiguity. Block 53 combine sequences designed to combine sequences of m-level samples from the same converters 51 and 52 of the channels I and Q reception side in a single sequence of m-level samples, following from the first clock frequency f1.

The Converter 54 into a binary sequence is designed to convert the combined sequence of m-level samples from the block 53 combine sequences in the information bit sequence of characters with a clock frequency of kf1.

The selector 42 clock frequencies contains (3) the first through third blocks 55-57 phase-locked loop (PLL), the first and second inputs which are designed to receive signals matched with the public channel I and channel Q of the receiving side, the output of the first block 55 PLL is designed to signal the tuning intermediate frequency supplied to the block 41 of the quadrature conversion. The first and second outputs of the second block 56 PLL are designed, respectively, to signal frequencysupplied to the first and third blocks 55, 57 PLL, the first and second buffer units 43, 44 and first and second blocks 45, 46 PPF, and meander signal interval frequency supplied to the first and second blocks 49 and 50 resolve the phase ambiguity. The output of the third block 57 PLL is designed to signal to adjust the clock frequency in block 58 the formation of frequency components, the outputs of the first group of outputs of which are connected to corresponding inputs of the group of inputs of the first and third blocks 55-57 PLL, and outputs the second group of outputs connected to corresponding inputs of the group of inputs of the second block 56 PLL. The first output unit 58 of the formation of frequency components is designed to generate signals with a frequencyat block 41 the quadrature conversion, the second output unit 58 of the formation of frequency components is used for delivery of signals from the second clock frequencythe first and second buffer units 43, 44, the third output unit 58 of the formation of frequency components intended to signal with a frequency kf 1the Converter 54 into a binary sequence, the fourth output unit 58 of the formation of frequency components is used for delivery of signals from the first clock frequency f1at block 53 combine sequences and Converter 54 into a binary sequence, the fifth output of block 58 of formation of frequency components is designed to generate signals with a frequency f1/2 on the first and second converters 51 and 52 in the m-level sequence and the block 53 combine sequences.

The block 41 of the quadrature conversion at the receiving side includes (figure 3): the seventh and eighth multiplier products 61 and 62, each designed to multiply the input signal with a corresponding quadrature component of the frequencywhereis the approximate frequency detuning from the intermediate frequency; first and second filters 63 and 64, each designed to highlight respectively the sine and cosine component of the received signal; first and second analog-to-digital converters (ADC) 65 and 66, each designed to convert the corresponding components of the received signal into digital samples with a frequency of; digital quadrature demodulator 67, dedicated to superior quality products is obtained for demodulation of the in-phase and quadrature channels using signal tuning intermediate frequency from the first block 55 PLL in the selector 42 clock frequency; the first and second optimal digital filters 68 and 69 that are designed for optimal digital filtering with frequencythe demodulated signals respectively in-phase and quadrature channels. The outputs of the first and second digital filters 68 and 69 are respectively the outputs of channel I and channel Q of the receiving side.

Included in block 41 of the quadrature conversion at the receiving side of the digital quadrature demodulator contains 67 (figure 4): the ninth and tenth multiplier products 71 and 72, each designed to multiply the sine components of the input signal with a corresponding quadrature component of the frequency; the eleventh and twelfth multiplier products 74 and 74, each designed to multiply the cosine components of the input signal with a corresponding quadrature component of the frequency; the first controlled synthesizer 75 frequency shaping of the signal tuning intermediate frequency (output of the first block 55 PLL) sine component of the frequency signalfor submission to the ninth and eleventh multiplier products 71, 73 and cosine component of the signal frequencyfor submission to the tenth and twelfth multiplier products 72 and 74; the first myCitadel 76 intended is to find the difference of the signals of the tenth and eleventh multiplier products 72, 73; the first adder 77, designed to sum the signals from the ninth and twelfth multiplier products 71, 74. The outputs of the first vicites 76 and the first adder 77 are respectively the outputs of channel I and channel Q block 41 of the quadrature conversion.

Figure 5-7 shows a possible execution of respectively the first and third blocks, phase-locked loop (PLL)included in the selector 42 clock frequency of the receiving side.

The first block 55 PLL contains (Fig. 5): the second myCitadel 101, designed for finding the difference of the signals in-phase and quadrature channels with respective outputs of the block 41 of the quadrature conversion; the first group multiplier products 102-104 intended for multiplying the difference signal with the second vicites 101 with the corresponding cosine components of cos Ω1t, cos Ω2t, ...cos Ωn/2t, described later; a second adder 105, intended for summing the results of multiplying outputs of multiplier products 102-104; the first filter 106 low pass (LPF)that is used to select the low-frequency components of the total signal of the second adder 105; thirteenth multiplier 107, designed to multiply the filtered in LPF 106 signal with a signal frequency; the first loop filter 108, p is rednaznachenie to filter the output signal of the thirteenth multiplier 107 and the selection signal of the tuning intermediate frequency. (The name "loop" emphasizes the fact that this filter is set in the PLL). The output of the first loop filter 108 is the output of the first block 55 PLL.

The second block 56 PLL contains (6): the third adder 111, intended for finding the sum of the signals in-phase and quadrature channels with respective outputs of the block 41 of the quadrature conversion; a second group of multiplier products 112-114, designed to multiply the total signal from the third adder 111 with the corresponding sine components sin Ω1t, sin Ω2t, sin ...Ωn/2t, described later; a fourth adder 115, intended for summing the results of multiplying outputs of multiplier products 112-114 of the second group; a second low-pass filter 116 that is used to select the low-frequency components of the total signal from the fourth adder 115; fourteenth multiplier 117, designed to multiply the filtered second LPF 116 signal with the signal, described later; a second loop filter 118 that is designed to filter the output signal of the fourteenth multiplier 117; second controlled synthesizer 119 frequencies intended for forming at its first output signal at the fourteenth multiplier 117 and at its second output - meander signal of the form

the first driver 120 frequency used for signal frequenciesof these meander signal with the second output of the second controlled synthesizer 119 frequencies. The output of the first driver 120 frequency and the second output of the second controlled synthesizer 119 frequencies are, respectively, the first and second outputs of the second block 56 PLL.

The third block 57 PLL contains (Fig. 7): the fifth adder 121, intended for finding the sum of the signals in-phase and quadrature channels with respective outputs of the block 41 of the quadrature conversion; the third multiplier products 122-124, designed to multiply the total signal from the fifth adder 121 with the corresponding cosine components of cos Ω1t, cos Ω2t, ...cos Ωn/2t, described later; a sixth adder 125, intended for summing the results of multiplying outputs of multiplier products 122-124 of the third group; and the third low-pass filter 126 that is used to select the low-frequency components of the total signal from the sixth adder 125; fifteenth multiplier 127, designed to multiply filtered in the third LPF 126 signal with a signal frequency; the third loop filter 128 that is designed to filter the output signal of the fifteenth lane the multiplier 127 and the selection signal to adjust the clock frequency. The output of the third loop filter 128 is the output of the third block 56 PLL.

Block 58 the formation of frequency components contains (Fig): third controlled synthesizer 131 frequencies intended for receiving from the third block 57 PLL signal to adjust the clock frequency and the signal clock frequency of the receiving side; a second imaging unit 132 frequency that is designed to generate a signal with a frequencyfrom the third signal controlled synthesizer 131 frequencies; a group of shapers 133-135 cosine components, each designed for the generation of the corresponding cosine of the components of cos Ω1t, cos Ω2t, ...cos Ωn/2t, described later; a group of shapers 136-138 sine components, each designed for the generation of the corresponding of the sine components of the sin Ω1t, sin Ω2t, sin ...Ωn/2t, described later; a chain 139 phase-locked loop (PLL)designed for frequency control the following signal on a signal from the second imaging unit 132 frequency; a fourth controlled synthesizer 140 frequency that is designed to generate a signal with a frequency adjust circuit 139 PLL; a third driver 141 frequency that is designed to generate a signal with a frequency from the second signal shaper 132 frequencies; the fourth shaper 142 frequency that is designed to generate a signal with a frequency kf1from the fourth signal controlled synthesizer 140 frequencies; the fifth imaging unit 143 frequency that is designed to generate a signal with frequency f1from the fourth signal controlled synthesizer 140 frequency; sixth shaper 144 frequency that is designed to generate a signal with frequency f1/2 from the signal of the fourth controlled synthesizer 140 frequency. The outputs of the group of shapers 133-135 cosine components and outputs of the group of shapers 136-138 sine components are, respectively, the first group of outputs and the second group of outputs of the fourth block 58 the formation of frequency components. The outputs of the second to sixth formers 132, 141-144 frequencies are, respectively, the first-fifth outputs of block 58 of formation of frequency components.

The method for transmitting and receiving QAM signals according to the present invention is implemented is shown in the system as follows.

The original bit sequence with a frequency kf1is supplied to the information input of the shaper 1 m-level symbols (figure 2), which converts this bit (i.e. binary sequence into a sequence of m-level symbols, where m=2k, k=2, 3, ..., following the x with the first clock frequency f 1. In principle, the imaging unit 1 is not required if the source sequence is exactly the sequence of m-level symbols. The first clock frequency is generated in the imaging unit 2 clock frequency of the transmitting side to the first output included in it block 3 dividing the frequency of arriving at its input signal clock frequency kf1. In the case when the source is a sequence of m-level symbols, the first clock frequency f1comes directly from the entrance. Then, in the imaging unit 2 clock frequencies will need to provide additional frequency multiplication unit 21 frequency multiplication, or add the appropriate frequency multiplier in front of the unit 21.

The received sequence of m-level symbols from the imaging unit 1 is fed to the separator 4 channels, where this sequence is divided into the channel I of the disclosing party with even m-level symbols and the Q channel of the transmitting side with odd m-level symbols. The repetition rate m-level symbols in each of the channels I and Q of the transmitting side is equal to f1/2. The corresponding clock signal is generated on the second output unit 3 dividing the frequency of the imaging unit 2 clock frequency.

In channel I the transferor even m-level symbols come in the first shaper 5 packs, where even m-benevia characters from one output of the separator 4 are stored in the form of packs of M m-level symbols in the interval

where 2L-1<M<2L, L=5, 6, 7.... Similarly, in the Q channel of the transmitting side is an odd m-level symbols received in the second shaper 6 packs, where odd m-level symbols from another output of the separator 4 are stored in the form of similar packs of M m-level symbols in the same interval T. in Addition, in each of the formers 5 and 6 packs each generated packet of M m-level symbols supplemented with n predetermined symbols to the total number M+n=2L. Note that the formers 5, 6 packs signal with a frequency of 1/T, i.ewith the third output unit 3 dividing the frequency of the imaging unit 2 clock frequency.

In each of the channels I and Q transferor all values of m-level symbols in odd pairs of packs are inverted, respectively, in the first and second multiplier products 7 and 8. One half of the values predefined symbols added to each odd couple of packs in each of the formers 5 and 6 packs in channels I and Q of the transmitting side, inverted, respectively, in the third and fourth multiplier products 9 and 10. This inversion is achieved by multiplying all incoming multiplier products 7-10 values on the meander signal

with values +1 and -1 and with a frequency of 1/4T, Davey from the fourth output unit 3 dividing the frequency of the imaging unit 2 clock frequencies. Note that the second half of the values predefined symbols added to each stack in each of the formers 5 and 6 packs in channels I and Q of the transmitting side, the inversion is not exposed.

Each pack of M m-level symbols, inverted or not, together with all n added to it predetermined values, one half of whichcan be inverted, and the other halfwithout inverting, enters the appropriate channel I and Q transferor on the third or fourth formers 11 and 12 packs. Each of these shapers 11 and 12 is designed to separate each pack of M+n symbols in half and parallel issue both halves at its respective output.

Each "Polypack" fromm-level symbols supplied to one of the first to fourth blocks 13-16 inverse fast Fourier transform (BPA), where with the help of BPA is replaced each pack ofcharacter set of M+n time samples.

Sets of M+n time samples from the outputs of the first to fourth blocks 13-16 BPA proceed in parallel on the same inputs parallel-to-serial converters 17-20. Each of these converters 17-20 is designed to convert each and the channels I and Q transferor parallel set of M+n time samples to a corresponding sequence of M+n time samples with the second clock frequency

This frequency is given from the fifth output of the shaper 2 clock frequencies, where the signal obtained from the first output unit 21 frequency multiplication, the input of which is applied a clock frequency kf1the initial sequence of bit characters.

Next is provided a rotation phase π/2 for all frequencies of the spectrum of one of the two sequences of M+n time samples in each of the channels I and Q transferor (which represents the Hilbert transform in this case). This surgery is performed in channels I and Q of the transmitting side of the first and second blocks 22, 23 of the Hilbert transform, respectively. Another sequence of M+n time samples in each of the channels I and Q of the transmitting side is delayed, respectively, the first or the second block 24, 25 delay in processing time in the corresponding block 22, 23 of the Hilbert transform.

Both received after these transformations, the sequence of M+n time samples from the rotated phases and detained in each of the channels I and Q of the transmitting side is received on the corresponding inputs of the first (channel I) and second (Q channel) petschenig adder 26 and 27, which produces bootstate combining these sequences of M+n time samples from the same block 22, 23 conversion is Alberta and same block 24, 25 delay in one sequence of the same length.

The resulting merged sequence in each of the channels I and Q transferor filtered, respectively, the first and second blocks 28 and 29 of the filter. This filtering is carried out with the second clock frequency f2supplied from the sixth output of the shaper 2 clock frequency (from the second output unit 21 frequency multiplication) in the range from 0 to f2/2 in an appropriate channel I and Q transferor.

Finally, the filtered signal in each of the channels I and Q of the transmitting side is fed to the imaging unit 30 of the signal transmission. In the imaging unit 30 in the fifth and sixth multiplier products 31, 32 is the multiplication of the filtered sequences on cosine and sine signals of the carrier frequency and adding results of the multiplication unit 33 adds. The output of block 33 in addition, the imaging unit 30 is supplied to the communication channel (not shown in Fig.2).

After passing through the communication channel, the transmitted signal arrives at the receiving side (Fig 3). After passing the usual for any receiver means of amplification, filtering, and conversion to an intermediate frequency (not shown in figure 3) the received signal is passed to the block 41 of the quadrature conversion. In this block 41 received signal intermediate frequency gets to the inputs of the seventh and eighth multiplier products 61 and 62, each of which the input signal is multiplied by with cosine or sine component of the frequencywhereis the approximate frequency detuning from the intermediate frequency. Obtained by this multiplication of the signals are filtered, respectively, in the first and second filters 63 and 64, allocating each respectively the sine and cosine components of the received signal.

These selected components are analog signals, respectively, first and second analog-to-digital converters (ADC) 65 and 66, which converts the corresponding components of the received signal into digital samples with a frequency ofcoming from the first output of the selector 42 clock frequencies. The digitized samples from both ADC 65 and 66 serves to corresponding inputs of a digital quadrature demodulator 67, which also receives the signal of the tuning intermediate frequency from the first block 55 PLL in the selector 42 clock frequency.

In the digital quadrature demodulator 67 (see figure 4) each of the sequences of digital samples fed to the combined inputs of the ninth (71), tenth (72) and eleven (73), twelfth 74) multiplier products. The signal tuning intermediate frequency is fed to a controlled synthesizer 75 frequencies, forming at their outputs sine and cosine components of the frequency. The signals from the ninth and twelfth multiplier products 71, 74 are served on a first adder 77, and the signals from the tenth and eleventh multiplier products 72, 73 are served on the first myCitadel 76. As a result, the outputs of the first vicites and the first adder output signals are formed quadrature demodulator 67. These signals (see figure 3) are passed through, respectively, the first and second optimal digital filters 68 and 69, which provide optimal digital filtering with frequencyreceived from the first output unit 58 of the formation of frequency components in the selector 42 clock frequencies. The outputs of the first and second digital filters 68 and 69 are formed, respectively, the output signals of the digital quadrature demodulator 67, respectively, for channel I and channel Q of the receiving side.

Obtained at the outputs of the digital quadrature demodulator 67 signals are fed into the selector 42 clock frequency, which is explained next, and to the inputs of the first (in channel I of the receiving side) and the second (in the Q channel of the receiving side) of the buffer blocks 43 and 44. Each of these two buffer blocks 43, 44 divides the post is surrounding him the sequence of digital samples in his channel (I or Q) to the receiving side in packs of M+n times, and remembers these packs of samples. Necessary for the operation of the buffer blocks frequency

and

served, respectively, with the second output of block 58 of formation of frequency components and the first output of the second block 56 PLL in the selector 42 clock frequency.

With buffer blocks 43, 44 signals are, respectively, the first and second blocks 45 and 46 of the direct Fourier transform (PPF), where over bundles on M+n times is performed, the Fourier transform, resulting in an appropriate channel I and Q reception side out of two packsm-level samples. The signal frequencyserved with the first output of the second block 56 PLL in the selector 42 clock frequency.

In the first and second highlighters 47 and 48 counts of each pair of packs fromm-level samples in an appropriate channel I and Q reception side is converted into a bundle of M m-level samples. These M samples correspond to samples that arrived at the input of the transmitting side.

The resulting bundle of M m-level samples in each of the channels I and Q reception side receives, respectively, the first and second blocks 49 and 50 resolve the phase ambiguity. Each of these blocks 49, 50 performs the elimination phase neodnoznachnost is in the signal of the channels I and Q reception side. It is the elimination of ambiguity is accomplished by multiplication of packs in a meander signal

received from the second output of the second block 56 PLL in the selector 42 clock frequency.

Bundle of M m-level samples with fixed phase ambiguity in each of the channels I and Q reception side served in parallel, respectively, first and second converters 51 and 52 in the m-level sequence, where the sequence of m-level samples in an appropriate channel I and Q reception side by using signals of frequency f1/2 from the fifth output of block 58 of formation of frequency components.

Thus obtained sequence of m-level samples are combined in a block 53 of Association sequences. The received sequence of m-level samples should first clock frequency f1supplied from the fourth output of block 58 of formation of frequency components in the selector 42 clock frequency.

The Converter 54 into a binary sequence is designed to convert the combined sequence of m-level samples from the block 53 combine sequences in the information bit sequence of characters with a clock frequency of kf1in the selector 42 clock frequencies. It is possible, however, that not is which the application output will be a sequence with unit 53 combine sequences. Then in the block circuit 58 formation of frequency components in the selector 42 clock frequency of the receiving side (Fig. 8) you can omit the fourth shaper 142 frequency.

Let us now turn to the selector 42 clock frequencies (Fig. 3). As already mentioned, the output signals of block 41 of the quadrature conversion arrive at the corresponding inputs of the first and third blocks 55-57 PLL, where these signals are signals required for normal reception.

In the first block 55 PLL (figure 5) signals from the outputs of the block 41 of the quadrature conversion signals of channels I and Q reception side) are fed to the inputs of the second vicites 101. With its differential output signal is fed to the group of multiplier products 102-104, to another input of each of which is served from the corresponding cosine components of the cos Ω1t, cos Ω2t, ...cos Ωn/2t, which is described next. All the results of this multiplication are served on the second adder 105, the output of which is filtered in low-pass filter 106 and is supplied to the thirteenth multiplier 107, the other input of which comes a signal with a frequencyfrom the first output of the second block 56 PLL. The result of the multiplication in the thirteenth multiplier 107 through the loop filter 108 is fed from the output of the first block 55 PLL to the input of the first controlled synthesizer 75 chastoty digital quadrature demodulator 67.

On the same principle works and the third block 57 PLL (7), except that the signals from the outputs of the block 41 of the quadrature conversion signals of channels I and Q reception side) are fed to the inputs of the fifth adder 121 (not vicites 101, as in the first block 55 PLL). The output signal of the third block 57 PLL is input to a block 58 of formation of frequency components, which is discussed later.

In the second block 56 PLL (6) units 111-118 operate similarly to the corresponding blocks 121-128 third block 57 PLL, except that the group of multiplier products 112-114 (similar to multiplier products 122-124 third block 57 PLL), serves not cosine and sine components of the sin Ω1t, sin Ω2t, sin ... Ωn/2t, which is described next. However, the outputs of the loop filter 118 is not in the output unit 56, and the second controlled synthesizer 119 frequency signal from the first output of which is fed to the fourteenth multiplier 117 (instead of a signal with a frequencyas in the third block 57 PLL). From the second output of the second controlled synthesizer 119 frequency signal of the form

supplied to the second output of the second block 56 PLL and the first driver 120 frequency, the output of which is frequency the first output of the second block 56 PLL.

The output signal of the third block 57 PLL, as already noted, is input to a block 58 of formation of frequency components, in which this signal is fed to the input of the third controlled synthesizer 131 frequency output signal which is fed to the input of the second driver 132 frequency. From the output of the second shaper 132 frequency signal obtained by frequencyserved on the first output unit 58 of the formation of frequency components to the input circuit 139 PLL and the input of the fourth imaging unit 141 frequency, as well as to the inputs of the group of shapers 133-135 cosine components and the inputs of the group of shapers 136-138 sine components.

Shapers 133-135 one group ensures formation of the cosine components of the cos Ω1t, cos Ω2t, ...cos Ωn/2t, the frequency value Ω1each of which is caused by the position of those of the n additional predefined symbols in each bundle of M+n symbols on the transmission side, the values of which are not inverted from batch to batchShapers 136-138 other groups provide the formation of the sine components of the sin Ω1t, sin Ω2t, sin ...Ωn/2t, the frequency value Ωieach of which is caused by the position of those RPMs for more predetermined symbols in each bundle of M+n symbols on the transmission side, values which are inverted from batch to batchRecall that the frequencies Ω1set in advance and are known as on the transmitting side and the receiving side. Due to this and it is possible to correct the phase ambiguity in the received signal. Received shapers 133-135 frequency of one group signals are in the first and third blocks 55, 57 PLL, the signals from the shaper 136-138 other group served in the second block 56 PLL.

The signal from the second imaging unit 132 frequency is supplied, as noted, also in the third imaging unit 141 frequency, the output of which produces a signal with a frequencyand circuit 139 PLL. Circuit 139 provides continuous adjustment of the frequency of the fourth controlled synthesizer 140 frequency frequencywith the second shaper 132 frequency. The output signal of the fourth controlled synthesizer 140 frequency is used in the fourth-sixth formers 142-144 frequency for generating signals with frequency, respectively, kf1f1(first clock) and f1/2.

Professionals it is clear that almost all the steps of the method for transmitting and receiving QAM signals according to the present invention can be realized not only in hardware but also in programme is m, since the processed signal is already discretized, digitized and transferred in the form of binary samples. These reports will be processed by the computer processor in accordance with the program which algorithm is in fact described above. In this case, the program corresponding to the execution of the above algorithm operation, by means of execution in which the computer can implement the method according to the present invention can be recorded on machine-readable media designed for direct operation in the computer.

In addition, the method according to the present invention can be specifically used to transmit messages using QAM signals, but only for synchronization signals quadrature amplitude modulation on the interval. In this case, the presence of the transmitted signal those components that correspond to the additional n predefined characters entered in the formers 5 and 6 packs.

Therefore, all these features are included as separate objects in the accompanying claims, completely determines the volume of the present invention, including any equivalents of the signs used in this invention. The description is only for illustration and explanation of principles, and not limiting the July volume of the present invention.

1. The method of sending and receiving signals, quadrature amplitude modulation (QAM), namely, that on the transmission side

a) share information sequence of m-level symbols, where m=2k, k=1, 2, 3, ..., with the following first clock frequency fi, on the channel I of the disclosing party with even m-level symbols and the Q channel of the transmitting side with odd m-level symbols, and m-level symbols in each of the channels I and Q transferor follow with frequency f1/2;

b) forming in each of the channels I and Q transferor tutu

of M m-level symbols in the intervalwhere 2L-1<M<2L, L=5, 6, 7..., and invert the values of the m-level symbols in odd pairs of packs;

C) complement each pack of M m-level symbols n predetermined symbols to the total number M+n=2Land invert the values of half of the mentioned pre-defined characters added in packs of each odd pair packs;

g) share in each of the channels I and Q of the transmitting side of each pack of M+n symbols in half and using a conversion from M+n frequency in the time domain replace each bundle fromcharacter set of M+n time samples, simultaneously existing n the time interval G;

d) transforming each of the channels I and Q of the transmitting side of each of these sets of M+n time samples obtained from one of these packs of M+n symbols, a corresponding sequence of M+n time samples with the second clock frequency;

(e) merge into each of the channels I and Q transferor both received sequence of M+n time samples in one sequence of the same length, for which all frequencies of the spectrum of one of the merged sequences turn phase π/2 and perform bootstate addition of both sequences;

g) is filtered in each of the channels I and Q of the transmitting parties of the joint sequence with the second clock frequency f2in the range from 0 to f2/2;

C) forming a signal for transmission using the filtered sequence;

at the receiving side:

and) divide the received signal on the signal of channel I of the receiving side and the signal of the Q channel of the receiving side using the double quadrature conversion and digital filtering;

to allocate by the sum signal of the channels I and Q reception side second clock frequency f2and based on it the first clock frequency, and for selecting the second clock is frequency use the frequency components in the spectra of the signals mentioned channels I and Q reception side, frequency Ω1each of which is caused by the position of those of the corresponding n additional predefined symbols in each of the mentioned bundle of M+n symbols in operations) on the transmission side, the value of which does not vary from batch to batch;

l) allocate meander signal interval frequency 1/T by comparing the phase of the above mentioned total signal channels I and Q reception side with those frequency components in the spectra of the signals mentioned channels I and Q reception side, the frequency value Ω1each of which is caused by the position of those of the corresponding n additional predefined symbols in each of the mentioned bundle of M+n symbols in operations) on the transmission side, the values of which vary from batch to batch;

m) forming stacks of M+n time samples in each of these channels I and Q reception side using the meander signal at intervals of;

n) split each generated a stack of M+n time M+n times in two sets ofcharacters in each of these channels I and Q reception side by using the transformation from time to frequency domain;

(o) form a set of M characters from both of the above sets of characters in each of these channels I and Q reception side by discarding n additional predefined symbols;

p) eliminate the phase ambiguity of the generated set of M symbols in each of these channels I and Q reception side using the meander signal;

R) form a sequence of m-level samples from all sets of M symbols, with the following frequency f1/1, in each of these channels I and Q reception side.

C) generate the output information sequence of m-level symbols from the first clock frequency f1by combining the above-mentioned sequence of m-level samples in both the above-mentioned channels I and Q reception side.

2. The method according to claim 1, in which before the said operation a) referred to the information sequence of m-level samples form by converting the bit sequence of characters, with the following frequency fb=kf1.

3. The method according to claim 1, wherein in said operation C) Peremohy in each of the channels I and Q transferor referred to the filtered sequence of the corresponding quadrature component of the carrier frequency to form the above-mentioned signal transmission by summing the results of the above-mentioned multiplication.

p> 4. The method according to claim 1, in which said operation e) on the transmission side includes the following steps: subjecting the Hilbert transform one of the two merged sequences of M+n time samples; delaying the other of these two sequences at run time mentioned the Hilbert transform; and then carry out the mentioned bootstate addition mentioned converted and detained sequences.

5. The method according to claim 1, in which in the above-mentioned operation W) on the transmission side in the filtration process in the above-mentioned range from 0 to f2/2 spectra in each of the channels I and Q are the first frequency components cos Ω1t, cos Ω2t, ...cos Ω3t, the frequency value Ω1each of which is caused by the position of those of the corresponding n additional predefined symbols in each of the mentioned bundle of M+n symbols in operations) on the transmission side, the value of which does not vary from batch to batch; and second frequency components,,the value of each of which is caused by position in each of the mentioned bundle of M+n symbols those of the corresponding n additional predefined symbols in operations) on the transmission side, the value to the which vary from batch to batch.

6. The method according to p. 1 or 5, in which the value of each of these n additional predefined symbols is equal to +1.

7. The method according to claim 5, in which said operation on the receiving side includes the following steps: transfer the received signal to an intermediate frequency; generate signals of the first and second channels by multiplying the received signal of the intermediate frequency signals, respectively sin(ωIF-Δω)t and cos(ωIF-Δω)t, whereis the approximate frequency detuning from the intermediate frequencythen digitizes the signal with a sample equal to 2f1in each of the aforementioned first and second channels; Peremohy digitized signal mentioned first channel signal cosΔωt, and the digitized signal mentioned second channel signal sinΔωt; expose obtained by the multiplication of the signals of the digital filter, thereby separating the received signal at a sequence of time samples of the channel I of the receiving side and the Q channel of the receiving side.

8. The method according to claim 7, in which said operation) further comprises the following steps: subtract the signal of the above-mentioned Q channel reception side signal from the above-mentioned channel I of the receiving party; comparison is more in phase of the received differential signal with said first frequency components cos Ω 1t, cos Ω2t, ...cos Ω3t; perform tuning frequencyapproximate the detuning of the signal obtained when comparing the mentioned difference signal.

9. The method according to claim 7, in which the said operation C) comprises the following steps: comparing the phase of the above mentioned sum signal of the channels I and Q reception side with said first frequency components cos Ω1t, cos Ω2t, ...cos Ωn/2t; carry out the adjustment mentioned frequency digitizing the signal received at the above-mentioned comparison of the total signal with the first frequency components; separated from the above-mentioned frequency digitizing the second clock frequency f2.

10. The method according to claim 5, in which in the above-mentioned operation l) comparing the phase of the above mentioned sum signal of the channels I and Q reception side with said second frequency components sin Ω1t, sin Ω2t, sin ...Ωn/2t, resulting extracted from signals,that ...a signal of the formand allocate meander signal interval frequency 1/T.

11. The method according to claim 10, in which said operation n)-p) at the receiving side includes the following steps: subjecting each of these packs and the M+n time samples in the interval of duration T direct Fourier transform, in the result, get two sets ofcharacters are formed from each pair received kitscharacters one set of M symbols; Peremohy each set of M symbols on the signal valueresulting in and resolve the phase ambiguity of the generated set of M symbols in each of the channels I and Q reception side.

12. System for transmitting and receiving signals, quadrature amplitude modulation with a low threshold sync carrier frequency, containing on the transmission side:

the separator channels, designed to separate the information sequence m-level symbols, where m=2k, K=2, 3, ..., with the following first clock frequency f1on the channel I of the disclosing party with even m-level symbols and the Q channel of the transmitting side with odd m-level symbols, the repetition rate mentioned m-level symbols in each of the channels I and Q of the transmitting side is equal to f1/2;

the first and second shapers packs, each designed for storing packs of M m-level symbols in the intervalwhere 2L-1<M<2L, L=5, 6, 7, ..., in an appropriate channel I and Q transferor and to complement each pack of M m-UB is nevah characters n predetermined symbols to the total number M+n=2 L;

first and second multiplier products, each designed to invert values of m-level symbols in odd pairs of packets in the channels I and Q of the transmitting side, respectively;

the third and fourth multiplier products, each designed to invert half of the added values in each odd couple packs of pre-defined symbols in the channels I and Q of the transmitting side, respectively;

the third and fourth formers packs, each designed to separate each pack of M+n symbols in half in an appropriate channel I and Q transferor;

the first to fourth blocks of the inverse Fourier transform, designed to replace each pack ofcharacter set of M+n time samples using the inverse Fourier transform;

first - fourth parallel-to-serial converters designed for conversion in each of the channels I and Q of the transmitting side of each of the said sets of M+n time samples obtained from one of these packs of M+n symbols, a corresponding sequence of M+n time samples with the second clock frequency

the first and second blocks of the Hilbert transform, each designed to rotate pafase π /2 for all frequencies of the spectrum of one of the sequences of M+n time samples in each of the channels I and Q of the transmitting side, respectively;

the first and second delay blocks, each designed to delay another sequence of M+n time samples in each of the channels I and Q of the transmitting side, respectively, at the time of processing in the corresponding block of the Hilbert transform;

the first and second pouchetii adders, each designed to combine in an appropriate channel I and Q transferor both received sequence of M+n time samples from the same block of the Hilbert transform and the namesake of the unit delays in one sequence of the same length;

the first and second filter blocks, each designed to filter the combined sequence with the second clock frequency f2in the range from 0 to f2/2 in an appropriate channel I and Q transferor;

shaper signal transmission, designed for signal transmission with filtered sequences in the channels I and Q transferor;

shaper clock frequency used to generate all clock frequencies required for the blocks of the transmitting side from the first cycles the second frequency;

at the receiving side:

block quadrature conversion, designed to separate the received signal into a sequence of digital samples of the channel I of the receiving side and the Q channel of the receiving party;

the selector such frequencies that is used to select the clock frequency by using the signals in the channels I and Q of the receiving party;

the first and second buffer units, each designed to separate a sequence of digital samples in an appropriate channel I and Q reception side in packs of M+n times, and to remember these packs;

the first and second blocks the direct Fourier transform, each designed for implementation in an appropriate channel I and Q reception side, the direct Fourier transform over bundles on M+n times and obtain pairs ofm-level samples;

the first and second highlighters samples, each designed to highlight M m-level samples from each pairlevel of counts in the corresponding channel I and Q of the receiving party;

the first and second blocks resolve the phase ambiguity, each designed to resolve the phase ambiguity in the signal of the channels I and Q of the receiving party;

first and stroypromresource in m-level sequence, intended each to construct a sequence of m-level samples in an appropriate channel I and Q of the receiving party;

the block Association sequences designed to combine sequences of m-level samples of the channels I and Q reception side in a single sequence of m-level samples, following from the first clock frequency f1.

13. System according to clause 12, in which the transmitting side before the said separator channels installed driver m-level samples, designed to convert the original information bit sequence of characters, with the following frequency kf1in the above-mentioned sequence of m-level symbols.

14. System according to clause 12, in which the transmitting side of the said driver signal to the transmission contains the fifth and sixth multiplier products, each designed to multiply each of the channels I and Q transferor filtered sequence of the corresponding quadrature component, and the unit of addition, designed for summing the results of multiplying the fifth and sixth multiplier products.

15. System according to clause 12, in which at the receiving side after the above-mentioned block Association sequences set the Converter to a binary sequence, designed the config for converting the combined sequence of m-level samples from the block combining sequence information in the sequence of bit symbols with a clock frequency of kf 1.

16. System according to clause 12, in which at the receiving side block quadrature conversion contains:

the seventh and eighth multiplier products, each designed to multiply the input signal with a corresponding quadrature component of the frequencywhereis the approximate frequency detuning from the intermediate frequency;

the first and second filters, each designed to highlight respectively the sine and cosine component of the received signal;

the first and second analog-to-digital converters, each designed to convert the corresponding components of the received signal into digital samples with twice the second clock frequency f2;

digital quadrature demodulator used to demodulate the in-phase and quadrature channels;

the first and second optimal digital filters for optimal digital filtering the demodulated signals respectively in-phase and quadrature channels.

17. System according to clause 16, in which at the receiving side of the digital quadrature demodulator contains:

the ninth and tenth multiplier products, each designed to multiply the sine components I the underwater signal with a corresponding quadrature component of the frequency ;

the eleventh and twelfth multiplier products, each designed to multiply the cosine components of the input signal with a corresponding quadrature component of the frequency;

controlled frequency synthesizer that generates from the signal of the tuning intermediate frequency sine component of the frequency signalfor submission to the ninth and eleventh multiplier products and cosine component of the signal frequencyfor submission to the tenth and twelfth multiplier products;

myCitadel designed for subtracting the signals of the tenth and eleventh multiplier products;

the adder, designed to sum the signals from the ninth and twelfth multiplier products.

18. System according to clause 12, in which at the receiving side the selector clock frequencies contains:

the first through third blocks, phase-locked loop (PLL), the first and second inputs which are designed to receive signals, respectively, of channel I and channel Q of the receiving side,

the output of the first PLL block is designed to signal the tuning intermediate frequency supplied to the mentioned block quadrature conversion

the first and second outputs of the second block of the PLL are, respectively, for vyd the Chi signal frequency supplied to the first and third blocks of the PLL, the first and second buffer units and the first and second blocks PPF, and meander signal interval frequencysupplied to the first and second blocks resolve the phase ambiguity,

the output of the third block of the PLL is designed to signal to adjust the clock frequency in the set of frequency components

block the formation of frequency components, the entrance of which is designed to receive signal adjusting the clock frequency of the third block of the PLL,

the outputs of the first group of outputs of the shaping unit frequency components are connected to the corresponding inputs of the group of inputs of the first and third blocks of the PLL, and outputs the second group of outputs connected to corresponding inputs of the group of inputs of the second block PLL,

the first output of the processing unit of frequency components is designed to generate signals with a frequencyat block quadrature conversion

the second output of the processing unit of frequency components is used for delivery of signals from the second clock frequencythe first and second buffer units,

the third output block the formation of frequency components is designed to generate signals with a frequency kf1 on the Converter to a binary sequence,

the fourth output of the shaping unit of frequency components is used for delivery of signals from the first clock frequency f1at block Association sequences and the Converter to a binary sequence,

the fifth output of the shaping unit of frequency components is designed to generate signals with a frequency f1/2 on the first and second converters in m-level sequence and block associations sequences.

19. Machine-readable media designed for direct participation in the work of the computer and contains a program for implementing the method according to claim 1.

20. Application of the method according to claim 1 for synchronizing signals quadrature amplitude modulation (QAM) on the interval.



 

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