Mechanism for processing interrupts in computer systems, supporting simultaneous execution of multiple streams

FIELD: engineering of interrupt processing mechanisms in computer systems.

SUBSTANCE: system contains processor with multiple contexts for execution of commands stored in memory. In response to common interrupt logical processors of processor with multiple contexts compete for receiving access to jointly utilized register. First logical processor gaining access to aforementioned jointly utilized register processes common interrupt. Remaining logical processors return from interrupt.

EFFECT: increased productiveness of system.

4 cl, 5 dwg

 

The scope of the invention

The present invention relates to computer systems, in particular to the mechanisms of interrupt handling in computer systems that support concurrent execution of multiple threads.

Prior art

Modern high-performance processors are designed to execute multiple commands for each time quantum. To do this, they usually include extensive resources of execution, in order to facilitate parallel processing of commands. The effective use of these resources may be limited by the availability of commands that can be executed in parallel. The availability of commands to execute in parallel is called a concurrency level commands (BUNCH) (ILP). Based commands limit the available BUNCH in a single thread of execution. If you can only process one thread of execution, the performance of the teams noticeably worse.

One approach to increase the performance of the teams is to develop processors so that they were able to execute commands simultaneously from two or more streams of commands. As the teams from different threads are independent, simultaneous execution of two or more streams of commands increases the performance of the teams.

Many of the structures implementing the Vano so, to support simultaneous execution of multiple threads in the same set of processors. For example, processors with multiple cores include multiple execution cores in a single processor chip. Each kernel execution can be assigned distinct from the other thread, although different resources can be used to reduce the dead (unused) area or to provide some connection between executable threads. Many of processor chips can also be combined in a module from a variety of chips, which provides a unified interface to the rest of the system.

Multithreaded processors include resources to manage the execution of multiple threads of commands in a single kernel execution. Blocks the flow control provide storage state data for multiple threads directly on the chip and update data, when teams from different streams are processed jointly used by the kernel.

Multithreaded processor coarse-grained structure in the same time executes the commands in just one thread, but storing state data for multiple threads on the chip reduces the amount of overhead (overhead)related commands switch between different threads (context switch is cutely). Thread switching can be executed when the executable at the current point in the stream runs into the event with high latency (the number of threads, switchable event, MPPS, SOEMT).

Multithreaded processor for fine-grained structure can simultaneously execute commands from different streams. For example, the commands may come from many threads in each period of the clocking or commands may come from different flows in different periods clocking. In both cases, the commands from multiple threads can be processed "on the fly" within the kernel execution at the same time.

In General, as a multithreaded processors and processors with multiple cores allow more than one thread context to be active in the processor at the same time. For processors with multiple cores, some or all of the cores can be multithreaded. Here, context refers to the registers that store the architectural state of a thread to a specific processor architecture, and may include General-purpose registers, control registers and registers of applications. Performance benefits of these and other processors that support multithreaded contexts ("processors with multiple contexts") depend, in particular, on the ability of these processors to act as a set is equivalent to the logical processors. This equivalence is much easier to find a balance workloads among logical processors and simplifies operating system management. The goal really is to get a processor with multiple contexts to act as a symmetric multiprocessor system (SMS).

To increase the symmetry among the many threads some resources for each logical processor is duplicated in the processor with a multitude of contexts. For example, block interrupt is typically associated with each logical processor to provide an interface between the logical processor and resources level system or a shared processor resources from a multitude of contexts. Block interrupt determines whether the interrupt is to be processed, and moves the pointer to the code handling routine interrupt, if the interrupt is taken.

One drawback ensure block interrupts for each logical processor is that interruption, particularly related to resources that are shared between the logical processors, often visible to all logical processors. For example, a processor with multiple contexts may provide a single output of interrupt to be compatible at the Assembly level with single-threaded construccionapartment, supplied to this conclusion, visible blocks interrupt all of the logical processors. Such interruption may cause failure of the system fan. Because of their equivalence, each block interrupt registers interrupt and its associated logical processor executes the interrupt service routine. Interrupts generated shared resources on the chip, or received on the system bus or a dedicated bus interrupts, can be seen and handled in the same way. In many cases, the interrupt may be processed by one of the logical processors, but the symmetrical configuration of logical processors causes each of them to perform the abort code.

The present invention is directed to solving these and other problems associated with the handling of interrupts in a processor that supports simultaneous execution of multiple threads.

Brief description of drawings

The present invention may be understood with reference to the accompanying drawings, in which identical elements are denoted by the same positions. These drawings are intended to illustrate selected embodiments of the present invention and not to limit the scope of the invention.

Figure 1 is a block diagram of a computer system, which can be implemented in the present invention.

Figure 2 is the fast block diagram of a processor with multiple cores in accordance with the present invention.

Figure 3 is a block diagram of a multithreaded processor in accordance with the present invention.

Figure 4 is a block diagram of the algorithm that represents one embodiment of the method for managing interrupts in accordance with the present invention.

Figure 5 is a block diagram of the algorithm of another variant implementation of the method of processing interrupts in accordance with the present invention.

Detailed description of the invention

The following description sets forth numerous specific details to provide a thorough understanding of the invention. However, experts on the basis of this description will understand that the invention can be practiced without these specific details. In addition, in order to focus on the characteristics of the present invention, are not described in detail, various known methods, procedures, components and circuits.

Figure 1 is a block diagram of one possible implementation of the computer system 100, which can be implemented in the present invention. Computer system 100 includes processor 110 with a multitude of contexts to execute commands stored in memory 160. Data and commands are transferred between the processor and the memory through the channel 180. The channel 180 may include one or more of the tyres under the control of the chipset or system logic (not shown.

For system 100, the memory 160 stores a subroutine 170 interrupt, which celebrates its resources on the processor 110 with a multitude of contexts in response to the interrupt. The memory 160 can represent patterns volatile memory, such as cache memory and main memory, and the structure of the non-volatile memory such as flash memory, hard and floppy disks, etc. For one possible implementation of the invention part of the routine 170 interrupt can be embodied in hardware and software, while other parts can be stored in main memory.

Logic (logic) processor 110 with a multitude of contexts presents logical processors 120(1)-120(n) (in the General case, the logical processor 120), including associated units 130(1)-130(n) interrupt (in the General case, the block 130 interrupts) and shared resources 140. For example, each logical processor 120 may represent resources that are assigned to a particular thread, and shared resources 140 can represent the resources of the processor 110, which is available threads on all logical processors 120.

For the described implementation of the system 100 of the shared resources 140 includes a register 150 applications for interrupts (WHR) (ICR), which is available for each logical about what essor 120. As will be described in detail below, the register 150 applications for interrupt provides a mechanism by which a single logical processor 120 signals the remaining logical processors that will handle the interrupt. Shared resources 140 can also include a cache higher level or tire logical schema used to communicate with the memory 160 or peripheral devices (not shown).

Block 130 interrupt is a functional block associated with the logical processor 120 for processing interrupts. Some interrupts can be processed by any of the logical processors 120. For example, some interrupts that occur in shared resources 140 at the processor level, or interrupt-level system or platform, which generated resources outside the set of processors that can usually be handled on any logical processor 120. They can communicate through external pin 104 on the housing of the processor via the bus or via a scheme internal to the processor 110. In the following discussion, these interrupts are referred to as interrupts in order to distinguish them from interrupts, which are designed for a specific logical processor.

Blocks 130(1)-130(n) interrupt register overall interrupt for logiteck the x processors 120(1)-120(n), respectively. For example, each unit 130 defines the interrupt priority assigned to interrupt together with any conditions of the mask to determine if it requires immediate interrupt processing, for example, should the event that triggered the interrupt, to obtain priority over the stream, executable at present. If the block 130 interrupt determines that the interrupt has priority, he tells the associated logical processor 120 to process interrupts have the procedure. The present invention provides a mechanism that allows a single logical processor 120 to perform the full procedure of interrupt processing for the interrupt, which registered all logical processors 120. This is done without making any asymmetries in the logical processors 120, that is, arbitrarily assigning interrupts logical processors 120.

For one possible implementation of the system 100 blocks 130(1)-130(n) interrupt register overall interrupt for logical processors 120(1)-120(n). If the interrupt has a higher priority, blocks 130(1)-130(n) interrupt is passed to the logical processors 120(1)-120(n), respectively, the address of the subroutine 170 interrupt. Each of the logical processors 120(1)-120(n) takes the first code segment subroutine 170 interrupt, which is output sends it to gain access to 150 WHR. The first of logical processors that successfully accesses WHR 150, performs the processing of interrupts, and the remaining logical processors 120 continue their threads.

For one possible implementation of the invention WHR 150 is initialized to the first value, and after the interrupt is set to the first value. The initial code segment subroutine 170 interrupt instructs each logical processor 120 to read values that are currently in WHR 150, and record the second value in WHR 150. Provided that the second value is different from the first value, the first logical processor 120 that has received the opportunity to read from WHR 150, sees the first value. All other logical processors 120 see the second value. Logical processor that reads the first value, continues to execute the interrupt service routine. The remaining logical processors read the second value, which signals them to return from the interrupt, for example to continue their interrupted threads.

Logical processor 120 does not necessarily correspond to the total interruption in the operation of the lock. The type of the executable thread when an interrupt occurs, its priority, or even the type of teams operating at the moment, can determine how quickly lo the systematic processor 120 receives the access WHR 150. Depending on execution, the subroutine 170 interrupt processing can be executed only by a single processor, and in this case, the first logical processor to perform routine 170 interrupt will be the first who will have access to 150 WHR.

Various embodiments of the processor 110 with a multitude of contexts implement logical processors 120 in various ways. In an embodiment with multiple cores of the processor 110 from the set of contexts, each logical processor 120 corresponds to the execution engine. The option to perform with many nuclei for the processor 110 with a multitude of contexts described with reference to figure 2. Multi-variant execution processor 110 with a set of contexts, each logical processor 120 corresponds to the resources of a single kernel execution, which is assigned to a particular thread. Multithreaded embodiment of processor 110 with a multitude of contexts described with reference to figure 3. Other embodiments of processor 110 with a multitude of contexts may include, for example, ways to perform with many nuclei, some or all of which are multi-threaded. The present invention does not depend on the specific manner by which the processor-implemented logical processors.

Figure 2 is a BL is a K-scheme, representing an embodiment 210 with multiple processor cores 110 with a multitude of contexts. The processor 210 with multiple cores provides kernel 220(1)-220(n) performance and their corresponding blocks 230(1)-230(n) interrupt processing, respectively, to support the simultaneous execution of up to n threads. Also shows the shared resources 240, which include the register 250 applications for interrupts (WHR). For the described scenarios processor 210 with many cores cores 220(1)-220(n) performance access WHR 250 via bus 254.

In response to the General interrupt each block 230 interrupt determines whether the interrupt priority, and if so, are their respective core 220 execution passes the address of the subroutine interrupt. Running the first part of the subroutine interrupt, the kernel 220 execution vie for access to the WHR 250. The first core of who has access to the WHR 250 completes the interrupt service routine. The remaining kernel execution continue their interrupted threads. For another variant of execution of the processor 210 with multiple cores, one or more cores 220(1)-220(n) performance can also be multi-threaded, and in this case, each thread of each core first tries to access WHR 250.

In one embodiment, the first the second code segment causes the logical processor 220 reads from WHR 250. If the logical processor 220 reads the first value of the WHR 250, it continues to execute the remainder of the subroutine interrupt. If the logical processor 220 reads the second value of the WHR 250, it can continue executing thread, which he sang to interrupt. To ensure that only one logical processor 220 reads the first value, the initial code segment can be used indivisible read-modify-write, such as an operation check and install. For example, if the first value in WHR 250 is zero, the subroutine 170 interrupt can read the value of the WHR 250 and directly burn unit in WHR 250. Thus, the operation of the read-modify-write is executed so as not to leave WHR 250 to another logical processor. For this option, only the first logical processor that will read from WHR 250 reads zero. All other logical processors will read the code that is stored in WHR 250 first logical processor, which gained access to WHR 250.

An implementation option, described above, is an example of a mechanism of "race for the flag to determine which logical processor will process the total interrupt. Flag, i.e., the variable lock or similarly chronaxies the bit(s), can be contained in the register, which can access each logical processor. Rules read/write control this flag allows each logical processor, acting independently, to determine whether he is responsible or not for handling shared interrupts.

Figure 3 is a block diagram representing a multi-threaded embodiment of 310 processor 110 with a multitude of contexts. Multithreaded processor 310 includes a core 304 execution, which allows simultaneous processing of up to n different threads. The core 304 of execution is a conveyor on which the different levels are assigned to one of the n threads (blocks 324(1)-324(n), 326(1)-326(n), 328(1)-328(n), 330(1)-330(n)), or shared among n threads (blocks 340(1)-340(n) and WHR 350). For example, blocks 340(a), 340(b) and 340(C) can represent a shared instruction cache, the shared block rename registers and the shared data cache. Blocks 324(1)-324(n), blocks 326(1)-326(n), blocks 328(1)-328(n) and blocks 330(1)-330(n) may represent part of the block fetch unit decode unit execution unit interrupts, respectively, which are assigned to threads 1-n. Resources assigned to the logical processor, shown on the same line vertically only to simplify figure 3. There is no intention to indicate any uporyadochivanie the resources, assigned to the stream.

For the described scenarios processor 310 logical processor 320(1) presents the assigned resources 324(1), 326(1), 328(1) and 330(1), and logical processor 320(n) is represented by assigned resources 324(n), 326(n), 328(n) and 330(n). This is done for illustrative purposes. Other views may include part of the shared resources 340(a)-340(s)currently in use in each thread.

Blocks 330 interrupts, as well as other assigned resources in the processor 310 need not be physically separate units. For example, they may represent parts of a single block of interrupts which are assigned to individual threads executable in the processor 310. In response to the General interrupt blocks 330(1)-330(n) interrupt register the interrupt and determine if it should be processed. If the interrupt has a higher priority, blocks 330(1)-330(n) interrupt is passed to the logical processors 320(1)-320(n) the address of the interrupt processing, for example, routine 170 interrupt. Each logical processor 320 executes the first code segment procedure interrupt handling which causes it to access WHR 350. The first logical processor 320, which accesses the WHR 350, takes the remainder procedure interrupt processing. The other logical processor is s 320 return to their interrupted threads.

Configuration processor 210 with multiple cores and multi-threaded processor 310 is shown for illustrative purposes only. Other embodiments of processors with multiple contexts, suitable for use with the present invention may use other configurations. For example, the threads of a multithreaded processor can share resources preprocessor and resources performance and only duplicate files of the register. Specialists in the development of processors on the basis of this description will understand that the present invention can be used with other configurations of processors with multiple contexts.

Figure 4 is a block diagram of the algorithm that represents one embodiment of the method 400, the executable each logical processor in the processor from the set of contexts in response to a General interrupt. The total interrupt is detected at step 410, the logical processor at step 420 determines whether the interrupt is to be processed. For example, the processing unit interrupts the logical processor may check the priority and the mask bits to determine whether the detected interrupt to gain an advantage over an executable in the current thread. If the interrupt has priority, the method 400 ends at step 470. If the interrupt has a higher priority, as defined is but at stage 420, then at step 430 the information about a particular state is stored in the corresponding point of the executable in current flow, and the logical processor at step 440 prescribed procedure interrupt at the specified address. Block interrupt usually provides the address of the subroutine interrupt if it detects that the interrupt has a higher priority.

Information about saved state before transferring control to the interrupt service routine, is usually the least amount of state information that can return a Boolean processor in the interrupted thread after handling routine interrupt. This reduces the overhead associated with interrupt service routine.

When entering a procedure interrupt logical processor executes the first code segment that instructs him to step 450 to access the register of applications for interrupts (WHR), at step 460 to compare the value stored with WHR, with the first value. If the read value equals the first value, the logical processor is in operation 470 continues to perform the processing of the interrupt. If the stored value is not equal to the first value, then at step 480 logical processor returns from the interrupt.

To guarantee the funds, that only one processor accesses the WHR at any time, embodiments of the present invention can protect WHR or code segment is used to access WHR. In the first case, the interrupt service routine can use an indivisible read-modify-write, to modify WHR. For this variant execution, if the logical processor is considered the first value of the WHR, he then writes in WHR second value, not stopping control over the WHR between read operations and write. Provided that WHR is set equal to the first value between interrupts, the first logical processor, which should be read from WHR, will read from WHR the first value and replace it with the second value. Any logical processor that reads from WHR after the first logical processor in response to the same interrupt, reads the second value and to return to their actions to interrupt.

In the second case, access to the first code segment subroutine interrupt strobiles bit of a critical region. The first logical processor, which achieves the first code segment executes an indivisible read-modify-write bit critical of the plot by reading the bit value and recording a second value in bits, not Reklama control over the bit between read operations and write. If the read value indicates that the first code segment is unlocked, the logical processor executes the code to read the value of the WHR. The second value written to bit critical section ensures that no other logical processor cannot execute the first code segment at the same time. If the read value indicates that the first code segment is blocked, the logical processor may return to the stream, which he takes. Because only one logical processor can simultaneously execute the first code segment, reading and writing in WHR does not require indivisible operations. The experts on the basis of this description will understand that various other mechanisms to ensure that only one logical processor is said about the possession of a common interrupt.

When the flag (WHR, variable locks and the like) in response to the General interrupt address all logical processors, the flag must be set equal to the first value for the next interrupt. For one variant of execution of the invention the last logical processor, scitebase flag in response to the General interrupt sets this flag is equal to the first value. For example, it may be specified that the flag comprises a bit for each logical processor, supported by the processor with a lot of company is offering. When each logical processor has access to the flag, it sets the corresponding bit flag. The last logical processor sets the corresponding bit of the flag, and then sets all of the bits of the flag to the first value.

For another variant of the initial code segment subroutine interrupt can command the logical processor to increment the value of the account (e.g., a flag) and read added value accounts. If the incremental value of the account is equal to the number of logical processors, active in the processor at the moment, the logical processor sets the value of the account is equal to the first value. If the incremental value of the account is less than the number of logical processors operating in the processor at the moment, the logical processor returns from the interrupt.

These mechanisms flag is set assume that the time between the interrupts are usually greater than the time required by all the logical processors to perform routine interrupt (or part thereof) and gain access to the flag. Specialists in the development of processors on the basis of this description will understand that other mechanisms for setting the flag after it was determined having a shared interrupt.

Figure 5 is a block diagram of the algorithm one possible implementation of the method 500, quenching the TCI interrupt in accordance with the present invention. Method 500 allows you to enable or disable duplicate handle shared interrupts. For example, it may be necessary that all logical processors answered total interrupt, such as checking system or heat. For these and other shared interrupts that require a response from all of the logical processors, the duplication of the interrupt can be enabled by using the links at the bit RSA (resolution total processing). This bit can be set for the selected shared interrupt when the system boots for the first time, or changed later to configure the specific environment of the system.

The method 500 begins at step 510 in response to the detection of shared interrupts. Logical processor at step 520 checks the bit to determine enabled the duplication of interrupt handling. If it is activated, the logical processor continues at step 530 the interrupt service routine, regardless of what other logical processors. If at step 520 bit indicates that the duplication interrupt is disabled, the logical processor at step 540 checks WHR to determine not reported not already in the possession of the interrupt. If at step 550 the possession of interrupt not yet stated, the logical processor continues at step 530 the interrupt service routine. Described is use mechanisms control access to extended and applicable to method 500. If at step 550 the claimed possession of termination, the logical processor at step 560 determines whether it is the last thread to answer a General interrupt. If it is, the logical processor at step 570 sets WHR equal to the first value, and at step 580 is returned from the subroutine interrupt to continue execution of the thread that he was treated in that moment, when there was an interruption. If this is not the last thread to answer a common interrupt, at step 580, the processor returns from the subroutine interrupt without setting WHR. The mechanisms of the method 400 described for determining whether a logical processor by the last thread to answer the General interrupt and accordingly reset WHR (e.g., flag)applies to method 500.

Thus, the mechanism of processing of some interrupts in computer systems that include processors with multiple contexts. Logical processors in a processor with multiple contexts are competing for access to shared register in response to a General interrupt. The first of logical processors that have access to shared register handles the interrupt.

The remaining logical processors find that the alleged possession of abortion is receiving, and return from a subroutine interrupt. For one possible implementation of the invention, the interrupt service routine includes a first code segment that is executed by all logical processors of the module in response to a General interrupt. Shared register initialized to the first value and the first code segment instructs each logical processor to read the shared register. The first logical processor, accessing the shared register, following the General interrupt, reads the first value, writes the second value and continues to execute the interrupt service routine. The other logical processor reads the second value, which requires them to leave the interrupt service routine.

For another variant implementation of the invention provides a bit on/off to indicate whether the shared interrupt to be handled excessively. If the register is in the off state, the possession of termination stating the first logical processor, accessing the shared register by executing the first segment procedure interrupt. If the bit is on, then the first code segment is passed, and all logical% the quarrels perform the processing of the interrupt to complete.

Disclosed embodiments of the provided to illustrate various features of the present invention. The present invention may find application in computers and other computer-based processor systems that use processors with multiple contexts. The experts on the basis of this description will understand that variations and modifications of the described embodiments, which however will be in the nature and scope of the attached claims.

1. A processor containing multiple logical processors, each of which contains a processing unit interrupts to przepisywania corresponding logical processor to execute the interrupt service routine in response to the interrupt, and the register of applications for interrupt connected to the processing unit of each logical processor, for storing a value that indicates whether each logical processor to handle the interrupt.

2. The processor according to claim 1, in which each of the logical processors reads the value from the register application interrupt running routine interrupt.

3. The processor according to claim 2, in which the interrupt is processed by the logical processor first reads the register of applications for the interruption.

4. The processor according to claim 3, in which the remaining logical processors out of the aprogramme interrupt, if the interrupt currently being processed other logical processor.

5. The processor according to claim 4, wherein the logical processor determines that the interrupt currently being processed, by reading values from a register of applications for interrupts, which recorded a logical processor, which first considered the case of applications for the interruption.

6. System for handling interrupts, containing a processor, comprising blocks interrupt connected to the register application interrupt and lots of thread resources for processing instructions corresponding to multiple threads teams, respectively, and a memory connected to the processor, for storing subroutines, interrupt handling, which includes commands that can be executed by each of the many resources flow in response to the interrupt, in order to read the value from the register application interrupt and handle the interrupt or continue the execution of appropriate resources flow in response to the read value.

7. The system according to claim 6, in which many resources flow contains many processor cores execution.

8. The system according to claim 6, in which many resources flow contains many resources kernel execution, which is assigned to multiple threads command.

9. The system according to claim 6, in which the subroutine processing the interrupt includes commands which can also be executed by each of the resource stream to write the second value in the register of applications for termination after reading the value from a register of applications for the interruption.

10. The system according to claim 9, in which the register of applications for the interrupt is initialized to store the first value and the first flow resources, which is considered the first value, replaces it with the second value, and processes the interrupt.

11. The system of claim 10, in which the remaining of the many resources thread execute a return from interrupt in response to reading the second value from the register application interrupt.

12. System for handling interrupts, containing a memory in which is stored the interrupt service routine, and a processor connected to said memory includes a register application interrupt and resources performance to support multiple logical processors in said processor, each of the logical processors compete for access to the register of applications for the interrupt using routine interrupt processing in response to the interrupt signal.

13. System according to clause 12, in which the resources of the execution to support multiple logical processors include multiple cores execution.

14. The system of item 13, in which each execution engine includes block, quenching the TCI interrupt to transfer control to kernel execution to the interrupt service routine in response to the interrupt signal.

15. The system of item 13, in which each of the cores execution processes the command handling routine interrupt to read the register application interrupt and continue the execution of the subroutine interrupt or return from subroutine interrupt in response to the value read from the register application interrupt.

16. The system of clause 15, in which the first one of the execution cores, which reads the register of applications for the interrupt in response to the interrupt signal, terminates the execution of the subroutine interrupt handling, and other engine performance out of the routine of interrupt handling.

17. System according to clause 12, in which the first logical processors that have access to the register of applications for the interrupt that terminates the execution of the subroutine interrupt.

18. System 17, in which the logical processors that have access to the register of applications for termination after the first logical processor, out of the routine of interrupt handling.

19. System according to clause 12, in which the resources of the execution to support multiple logical processors include multiple execution cores, at least one of which supports multiple threads.

20. Method for interrupt processing performed by each thread running in the current moment in one logical% the quarrel processor with multiple contexts containing at least one logical processor in response to the interrupt, containing the following operations: obtaining mentioned logical processor access to the interrupt service routine at the specified memory address, the execution of the mentioned logical processor handling routine interrupt for reading the value from the register application interrupt and the completion of the execution of the subroutine interrupt if the value read from the register application interrupt is the first value.

21. The method according to claim 20, in which the operation execution subroutine interrupt contains the following operations: reading the above-mentioned values of the register application interrupt and write the second value in said register, not stopping control this case.

22. The method according to claim 20, further containing an operation termination of the subroutine interrupt if the value read from the register application interrupt, is the second value.



 

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FIELD: methods for automatic execution of a program, connected to data file, when data file and program being executed are positioned on different computer units.

SUBSTANCE: in methods, program being executed is accessed through graphic image of data file type, realized in the network, which includes client system and a set of server systems. Client system receives the scheme, which determines connection between the set of programs being executed and corresponding set of data file types. Graphic image of data files is displayed, information about selection of graphic image of data file is received from server system, on basis of it program to be executed is selected and executed.

EFFECT: increased productivity of system due to distributed execution of programs.

9 cl, 19 dwg, 3 tbl

FIELD: method and system for providing user interface information to client.

SUBSTANCE: in accordance to the invention, access system contains registration mechanism. Client environment for automatic processing of user interface receives registration information from the client and transmits user interface information after receipt. Server for automatic processing of user interface receives registration information from client environment for automatic processing of user interface and notifies processor of user interface about registration, and also receives user interface information from user interface processor. The server contains filtration device for filtering out information of no interest to client, and notification device for notifying the client about information which is of interest to the client.

EFFECT: ensured capacity for filtration and coordination of excessive and disorienting notifications.

2 cl, 11 dwg

FIELD: telecommunications.

SUBSTANCE: device contains a set of central processor units, which are assigned a common external up address in telecommunication network which allows packet data. IP messages, addressed to a network element, are received, and received IP messages which contain first messages are identified. First value is identified in first message and first message is transmitted to central processor unit on basis of identified first value, if identified first value is not equal to zero.

EFFECT: ensured load balancing for central processor when using several types of traffic.

3 cl, 3 dwg

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