Nand gate depending for its operation on quantum effects

FIELD: computer engineering and integrated electronics; integrated logic gates of very large-scale integrated circuits.

SUBSTANCE: newly introduced in integrated logic gate that has semi-insulating GaAs substrate, first input metal bus, first AlGaAs region of second polarity of conductivity disposed under the latter to form common Schottky barrier junction, first inherent-conductivity AlGaAs spacer region disposed under the latter, first GaAs region of inherent-conductivity channel disposed under the latter, second AlGaAs region of second polarity of conductivity, second AlGaAs spacer region of inherent conductivity, second input metal bus, output region of second polarity of conductivity, output metal bus, power metal bus, zero-potential metal bus, and isolating dielectric regions are inherent-conductivity AlGaAs tunnel-barrier region, InGaAs region of inherent-conductivity channel, AlGaAs region of second inherent-conductivity barrier, L-section power region of second polarity of conductivity, and Г-section zero-potential region of second polarity of conductivity; first GaAs region of inherent-conductivity channel and InGaAs region of inherent-conductivity channel are disposed in relatively vertical position and separated by AlGaAs region of inherent-conductivity tunnel barrier; output region of second polarity of conductivity is ┘-shaped and ┘-section region.

EFFECT: enhanced efficiency of using chip area, enhanced speed and reduced power requirement for integrated logic gate switching.

1 cl, 3 dwg

 

The present invention relates to the field of computational engineering and integrated electronics, and more specifically to integrated logic elements VLSI.

Known integral logical element "OR NOT" on field-effect transistors with control transitions Schottky (see Shur M. Modern devices based on gallium arsenide. - M.: Mir, 1991. - 632 S., figa, s, Fig, p.472)containing politology GaAs substrate, the first metal input bus, the second metal input bus, output metal bus, the metal power bus, and a metal bus zero potential, the area of the separating dielectric GaAs channel region of the first key of the transistor of the second conductivity type located above politology GaAs substrate and forming a transition Schottky first input metal bus, GaAs channel region of the second key of the transistor of the second conductivity type located above politology GaAs substrate and forming a transition with the second Schottky metal input bus, region of the second conductivity type with a rectangular cross-sectional shape, which is the area of the first source of the switching transistors and the area of the second source of the switching transistors connected to the metal bus zero potential, the region of the second conductivity type with rectangular forms the th cross-section, which is the drain region of the first key of the transistor and the drain region of the second key of the transistor connected to the output metal bus, GaAs-channel load resistor of the second conductivity type located above politology GaAs-substrate, the first contact area of the load resistor of the second conductivity type, connected to the output metal bus, the second contact area of the load resistor of the second conductivity type, connected with a metal power bus, and GaAs-area of the key channels of the transistors and the load resistor of the second conductivity type are horizontal relative positioning.

Signs of similar matching essential attributes are polyzoniida GaAs-substrate, the first metal wire, a second metal input bus, output metal wire, metal power bus, the metal wire zero potential, the area of the separating dielectric.

The reasons that impede the achievement of the technical result is inefficient use of chip area due to the horizontal relative location of key transistor and load resistor and the lack of functional integration of semiconductor key areas of the transistors and the load, the loading resistor; the time limit switching element time-of-flight electron channel transistors; limiting time-of-flight electron channel transistors effect of scattering of electrons in the channels on ion dopants; the big energy switch element due to overcharging tanks gate-channel key of the transistors during switching element; reduced immunity and the slope of the transfer characteristic of the element due to the use of a load resistor.

Functional analogue of the claimed object is the integral of the logical element "OR NOT" on field-effect transistors with control p-n-transitions (see Shur M. Modern devices based on gallium arsenide. - M.: Mir, 1991. - 632 S., Fig, s)containing politology GaAs substrate, the first metal input bus, the second metal input bus, output metal bus, the metal power bus, and a metal bus zero potential, the area of the separating dielectric located above politology GaAs substrate GaAs channel region of the first key of the transistor of the second conductivity type, located in her area of the first shutter key of the transistor of the first conductivity type connected to the first input of a metal line located above politology GaAs under what oikoi GaAs channel region of the second key of the transistor of the second conductivity type, located in her area of the second shutter key of the transistor of the first conductivity type that is connected with the second input of the metal line region of the second conductivity type with a rectangular cross-sectional shape, which is the area of the first source of the switching transistors and the area of the second source of the switching transistors connected to the metal bus zero potential, the output region of the second conductivity type with a rectangular cross-sectional shape, which is the drain region of the first key of the transistor, the drain region of the second key of the transistor and the first contact area of the load resistor and connected to the output metal bus, GaAs-channel load resistor of the second conductivity type located above politology GaAs substrate, the second contact area of the load resistor of the second conductivity type, connected with a metal power bus, and GaAs-area of the key channels of the transistors and the load resistor of the second conductivity type are horizontal relative positioning.

Signs of similar matching essential attributes are polyzoniida GaAs-substrate, the first metal wire, a second metal input bus, output metal wire, metal power bus, met licenca bus zero potential, the area of the separating dielectric.

The reasons that impede the achievement of the technical result is inefficient use of chip area due to the horizontal relative location of key transistor and load resistor; time limit switching element time-of-flight electron channel transistors; limiting time-of-flight electron channel transistors effect of scattering of electrons in the channel ions doping impurities; high power switching element due to overcharging capacitance gate-channel of the switching transistors during switching element; reduced immunity and the slope of the transfer characteristic of the element due to the use of a load resistor.

Known the closest to the technical nature of the claimed object is the integral of the logical element "OR NOT" on heterophonic transistors with high mobility of carriers (see Shur M. Modern devices based on gallium arsenide. - M.: Mir, 1991. - 632 S., Fig, s)containing politology GaAs substrate, the first input metal tire located underneath and forming with it the transition Schottky first AlGaAs region of the second conductivity type located beneath the first AlGaAs region of the spacer own is routenote, located underneath the first GaAs channel region of intrinsic conductivity, a second AlGaAs region of the second conductivity type, a second AlGaAs region of the spacer intrinsic conductivity, the second metal input bus, an output region of the second conductivity type adjacent to the first GaAs-channel region of intrinsic conductivity, the output metal bus connected to an output region of the second conductivity type, a metal power bus, and a metal bus zero potential, the area of the separating dielectric located under the second AlGaAs region of the spacer own second conductivity GaAs channel region of intrinsic conductivity, the third AlGaAs region of the second conductivity type located under her third AlGaAs region of the spacer intrinsic conductivity, located underneath the third GaAs channel region of intrinsic conductivity, bordering the output region of the second conductivity type, the region of zero potential of the second conductivity type with a cross-section of rectangular shape, bordering on the first GaAs-channel region of intrinsic conductivity and the second GaAs-channel region of intrinsic conductivity and connected to the metal bus zero potential, a metal gate, which forms the transition Schottky third AlGaAs region of the second conductivity type and coupled with the output metal the standard bus, the scope of supply of the second conductivity type with a cross-section of rectangular shape, bordering the third GaAs-channel region of intrinsic conductivity and connected with metal power bus, and the first, second and third GaAs field of its own channels of conductivity have mutual horizontal position and located above politology GaAs substrate, a second AlGaAs region of the second conductivity type is located above the second AlGaAs region of the spacer intrinsic conductivity and the second metal input bus and forms with it the transition Schottky.

The reasons that impede the achievement of the technical result is inefficient use of chip area due to the horizontal relative location of the first, second and third regions of the channels integrated logic element and a lack of functional integration of the fields of the structure; the time limit of the switching element by the flight time of the electrons of the first and second regions of the channels integrated logic element; the big energy switch element due to overcharging of the input capacitances during switching element.

The task of the invention is to increase the efficient use of chip area, increasing performance and reducing the energy switch is of integral logic element.

To achieve the desired technical effect in the integrated logical element "OR NOT" on quantum effects, containing politology GaAs substrate, the first input metal tire located underneath and forming with it the transition Schottky first AlGaAs region of the second conductivity type located beneath the first AlGaAs region of the spacer intrinsic conductivity, located underneath the first GaAs channel region of intrinsic conductivity, a second AlGaAs region of the second conductivity type, a second AlGaAs region of the spacer intrinsic conductivity, the second metal input bus, an output region of the second conductivity type adjacent to the first GaAs-the channel region of intrinsic conductivity, the output metal bus connected to an output region of the second conductivity type, a metal power bus, and a metal bus zero potential, the area of the separating dielectric entered beneath the first GaAs-channel region of intrinsic conductivity AlGaAs region of the tunnel barrier intrinsic conductivity, which is located underneath and adjacent to the output region of the second conductivity type InGaAs-channel region of intrinsic conductivity above politology GaAs substrate and the second AlGaAs region of the second conductivity type AlGaAs region of the second barrier own PR is Vedemosti, the scope of supply of the second conductivity type with a cross-section in the form of symbol L, connected with metal power bus and bordering InGaAs-channel region of intrinsic conductivity, the region of zero potential of the second conductivity type with a cross-section in the form of the symbol G, connected to the metal bus zero potential and bordering the first GaAs-channel region of intrinsic conductivity, and the first GaAs channel region of intrinsic conductivity and InGaAs-channel region of intrinsic conductivity have a vertical mutual arrangement, separated by AlGaAs region of the tunnel barrier intrinsic conductivity, a second AlGaAs region of the spacer intrinsic conductivity is under InGaAs-area channel intrinsic conductivity, a second AlGaAs region of the second conductivity type located beneath the second AlGaAs region of the spacer intrinsic conductivity, the second input metal wire is located above the first AlGaAs region of the second conductivity type and forms with it the transition Schottky, the output region of the second conductivity type is of the formand the cross-section in the form of symbol

Comparing the proposed device with the prototype, we see that it contains new features, that is, meets the criterion of novelty. Compared to the number who AMI, we conclude that the proposed device complies with the criterion of "substantial differences"as the analogues are not detected shown new signs. Due to the introduction of the design below the first GaAs-channel region of intrinsic conductivity AlGaAs region of the tunnel barrier intrinsic conductivity, which is located underneath and adjacent to the output region of the second conductivity type InGaAs-channel region of intrinsic conductivity above politology GaAs substrate and the second AlGaAs region of the second conductivity type AlGaAs region of the second barrier intrinsic conductivity, nutrition of the second conductivity type with a cross-section in the form of symbol L, connected with metal power bus and bordering InGaAs-channel region of intrinsic conductivity, a region of zero potential of the second conductivity type with a cross-section the symbol G, is connected to the metal bus zero potential and bordering the first GaAs-channel region of intrinsic conductivity, and the first GaAs channel region of intrinsic conductivity and InGaAs-channel region of intrinsic conductivity have a vertical mutual arrangement, separated by AlGaAs region of the tunnel barrier intrinsic conductivity, a second AlGaAs region of the spacer intrinsic conductivity is under InGaAs-wher is th channel has its own conductivity, second AlGaAs region of the second conductivity type located beneath the second AlGaAs region of the spacer intrinsic conductivity, the second input metal wire is located above the first AlGaAs region of the second conductivity type and forms with it the transition Schottky, the output region of the second conductivity type is of the formand the cross-section in the form of symbolthe positive effect, which consists in increasing the efficient use of chip area, increasing performance and reducing power switch integrated logic element.

Figure 1 shows the topology of the proposed integrated logic element "OR NOT" on quantum effects. Figure 2 shows the cross section of the proposed integrated logic element in the region of zero potential and the first input metal bus. Figure 3 shows the cross section of the proposed integrated logic element in the output region and the power of the second conductivity type.

Integral logic element contains politology GaAs substrate 1, the first input metal bus 2, located beneath and forming with it the transition Schottky first AlGaAs region of the second conductivity type 3 located underneath the first AlGaAs region of the spacer own provodimost is 4, located underneath the first GaAs channel region of intrinsic conductivity 5, a second AlGaAs region of the second conductivity type 6, a second AlGaAs region of the spacer own conductivity 7, the second metal input bus 8, the output region of the second conduction type 9, bordering on the first GaAs-channel region of intrinsic conductivity 5, the output of metal bus 10 connected to an output region of the second conduction type 9, the metal power bus 11, a metal zero potential bus 12, the area of the separating dielectric 13 located under the first GaAs-channel region of intrinsic conductivity 5 AlGaAs region of the tunneling barrier of its own conductivity 14 located underneath and adjacent to the output region of the second conduction type 9 InGaAs-channel region of intrinsic conductivity 15 located above politology GaAs substrate 1 and the second AlGaAs region of the second conductivity type 6 AlGaAs region of the second barrier intrinsic conductivity 16, zone of the second conductivity type 17 with a cross-section in the form of symbol L, connected with metal power bus 11 and bordering InGaAs-channel region of intrinsic conductivity 15, the region of zero potential of the second conductivity type 18 with a cross-section in the form of the symbol G, is connected to the metal bus zero potential 12 and faces asuu with the first GaAs-channel region of intrinsic conductivity 5, the first GaAs channel region of intrinsic conductivity 5 and InGaAs-channel region of intrinsic conductivity 15 have vertical mutual arrangement, separated by AlGaAs region of the tunnel barrier intrinsic conductivity 14, a second AlGaAs region of the spacer own conductivity 7 is located under InGaAs-channel region of intrinsic conductivity 15, a second AlGaAs region of the second conductivity type 6 is located below the second AlGaAs region of the spacer own conductivity 7, the second input metal wire 8 is located above the first AlGaAs region of the second conductivity type 3 and forms with it the transition Schottky, the output region of the second conduction type 9 has the form of a symboland the cross-section in the form of symbol

The device operates as follows. When the supply voltage on the metal bus 11 connected to the zone of the second conductivity type 17 with a cross-section in the form of symbol of L, with respect to the metal zero potential bus 12 connected to a region of zero potential of the second conductivity type 18 with a cross-section in the form of the symbol G, and the active low voltage level logic zero at the first input metal bus 2 and the second metal input bus 8, forming transitions Schottky first AlGaAs region in the showing of the conductivity type 3, the electrons that are promoted in the first GaAs channel region of intrinsic conductivity 5 of the first AlGaAs region of the second conductivity type 3 and spatially isolated from ions of an impurity of the first AlGaAs region of the spacer own conductivity 4, and the electrons that are promoted in InGaAs-channel region of intrinsic conductivity 15 of the second AlGaAs region of the second conductivity type 6 due to the AlGaAs region of the second barrier intrinsic conductivity 16, preventing the transition of electrons from the second AlGaAs region of the second conductivity type 6 in politology GaAs substrate 1, and spatially isolated from ions of an impurity of the second AlGaAs region of the spacer own conductivity 7, tunneling through the AlGaAs region of the tunnel barrier intrinsic conductivity 14 of the quantum well formed by the first GaAs-channel region of intrinsic conductivity 5, in a deeper quantum hole formed InGaAs-channel region of intrinsic conductivity 15, resulting in a conductivity of the first GaAs-channel region of intrinsic conductivity 5 bordering region of zero potential of the second conductivity type 18 with a cross-section in the form of the symbol G and the output region of the second conduction type 9 and isolated from the nutrition of the second conductivity type 17 with a cross-section in the form of symbol L area separating dielectric 13, low and spend the awn InGaAs-channel region of intrinsic conductivity 15, bordering the output region of the second conduction type 9 and zone of the second conductivity type 17 with a cross-section in the form of symbol L and isolated from the region of zero potential of the second conductivity type 18 with a cross-section in the form of the symbol G politology GaAs substrate 1, the high and the output metal bus 10 connected to the output region of the second conduction type 9, operates the high voltage level of the logical unit.

When applying a high voltage level of the logic unit at the first input metal bus 2 or the second input metal bus 8, or the first and the second input of the metal wire 2 and 8 simultaneously, the transverse component of the electric field shifts the energy levels are located at the bottom of the quantum well formed by the first GaAs-channel region of intrinsic conductivity 5, lower energy levels, located at the bottom of the quantum well formed by InGaAs-channel region of intrinsic conductivity 15, causing the electrons are tunneling through the AlGaAs region of the tunnel barrier intrinsic conductivity 14 of the quantum well formed by InGaAs-channel region intrinsic conductivity 15, in quantum hole formed in one of the first GaAs-channel region of intrinsic conductivity 5, the first conductivity GaAs-channel region of intrinsic conductivity 5 bordering region of zero potential of the second conductivity type 18 with a cross-section in the form of the symbol G and the output region of the second conduction type 9 and isolated from the nutrition of the second conductivity type 17 with the cross-section in the form of symbol L area separating dielectric 13, is increased, and the conductivity of InGaAs-channel region of intrinsic conductivity 15, bordering the output region of the second conduction type 9 and zone of the second conductivity type 17 with a cross-section in the form of symbol L and isolated from the region of zero potential of the second conductivity type 18 with a cross-section in the form of the symbol G politology GaAs substrate 1 decreases and the output metal bus 10 connected to the output region of the second conduction type 9, a low level voltage logical zero.

Thus, the proposed device is an integrated logical element "OR NOT" on quantum effects.

Vertical reciprocal position of the first GaAs-channel region of intrinsic conductivity and InGaAs-channel region of intrinsic conductivity, the first and second AlGaAs regions of the second conductivity type, the first and second AlGaAs regions of the spacers intrinsic conductivity, AlGaAs regions of barriers intrinsic conductivity, the use of only two control passages Schottky and shapes of the cross sections of the nutrition of the second conductivity type in the symbol L, the region of zero potential of the second conductivity type in the symbol G and the output region Vtorov the type of conductivity in the form of a symbol with a cross section in the form of symbolit ensures reduction of approximately 2 times the space integral of the logical element in the crystal, compared to the prototype.

The effect of electron tunneling between the first GaAs-channel region of intrinsic conductivity and InGaAs-channel region of intrinsic conductivity, separated by AlGaAs region of the tunnel barrier, provides switching integrated logic element of the logic zero state to the state of the logical unit and Vice versa under the influence of control input voltages at practically the same total number of electrons in the regions of the channels, which reduces the energy of the switching element and to improve its performance compared with the prototype and analogues, as in this case, the time delay element is not limited to time-of-flight electron channels (at constant total number of electrons in the channels of possible multiple tunneling electron transitions between the channels, and therefore multiple switch integrated logic element for time-of-flight electron channel).

Integrated logical element "OR NOT" on quantum effects, containing politology GaAs substrate, the first input Metallichesky the bus, underneath her and forming her transition Schottky first AlGaAs region of the second conductivity type located beneath the first AlGaAs region of the spacer intrinsic conductivity, located underneath the first GaAs channel region of intrinsic conductivity, a second AlGaAs region of the second conductivity type, a second AlGaAs region of the spacer intrinsic conductivity, the second metal input bus, an output region of the second conductivity type adjacent to the first GaAs-channel region of intrinsic conductivity, the output metal bus connected to an output region of the second conductivity type, a metal power bus, and a metal bus zero potential, the area of the separating dielectric, characterized in that it introduced beneath the first GaAs-channel region of intrinsic conductivity AlGaAs region of the tunnel barrier intrinsic conductivity, which is located underneath and adjacent to the output region of the second conductivity type InGaAs-channel region of intrinsic conductivity above politology GaAs substrate and the second AlGaAs region of the second conductivity type AlGaAs region of the second barrier intrinsic conductivity, recharge area of the second conductivity type with a cross-section in the form of symbol L, connected with metal power bus and bordering InGaAs-area canadacasino conductivity, the region of zero potential of the second conductivity type with a cross-section in the form of the symbol G, connected to the metal bus zero potential and bordering the first GaAs-channel region of intrinsic conductivity, and the first GaAs channel region of intrinsic conductivity and InGaAs-channel region of intrinsic conductivity have a vertical mutual arrangement, separated by AlGaAs region of the tunnel barrier intrinsic conductivity, a second AlGaAs region of the spacer intrinsic conductivity is under InGaAs-channel region of intrinsic conductivity, a second AlGaAs region of the second conductivity type located beneath the second AlGaAs region of the spacer intrinsic conductivity, the second input metal wire is located above the first AlGaAs region of the second conductivity type and forms with it the transition Schottky, the output region of the second conductivity type is of the formand the cross-section in the form of symbol



 

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EFFECT: enhanced efficiency of using chip area, enhanced speed and reduced power requirement for integrated logic gate switching.

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