Method and device for processing data for preserving recurrent status

FIELD: method and device for processing data for preserving recurrent status in data processing device.

SUBSTANCE: device has data processing block, having multiple functioning modes, for each of which special memory stack is present. Method describes operation of this device. Data carrier contains program, configuring data processing device for performing stages of method.

EFFECT: decreased size of code and decreased interruption processing delay.

3 cl, 16 dwg

 

The technical field

The present invention relates to a method and device data to save the return status, and more specifically to the preservation of the recurrent state in the processing unit containing a processor having multiple modes of operation, each mode of operation has a corresponding stack storing data corresponding to the mode.

Prior art

It is known that in the processing unit of this type is provided by the commands to save the data return condition in the stack corresponding to the current mode of operation. A typical example of the use of such teams is an exceptional condition occurs, in which event leads to the preservation of data return condition in the stack corresponding to the mode of functioning of the exceptional situation. This procedure may be required for various reasons. For example, in the main, such a processing unit can support multitasking, and when it should be performed a context switch to allow another task, you must perform the swapping or paging stack or stacks corresponding to the operation modes of the current task to be able to perform the new tasks. In systems where access to the stacks is carried out with the use of pointers, stacks, such swapping is typically done by moving the stack pointer or pointers stacks in the case of multiple stacks. In the processing unit of this type usually require storing the data return state stack, swapping which will be implemented upon the occurrence of the context switch.

To improve context switch requires swapping all stacks that are not empty at the time of the context switch. On a processor with multiple stacks may require swapping each stack associated with a particular task. Additionally, when using this approach for each task must be supported by separate stacks for (each) operating mode, resulting in increased costs and increased time spent on the exercise of swapping each stack associated with each task. For example, modern processors produced by arm limited (ARM Limited), has six separate stacks, corresponding to the six modes of operation, namely the System/User mode, the mode SBP (request fast interrupt), the Preferred mode, the mode Emergency stop (), mode WIA (interrupt request) and NEAP edenennomu mode, where SBP and WIA are two operation modes, which modes interrupt. Therefore, when using the above approach, a context switch may require swapping six separate stacks, and each task may require the reservation of memory for six separate stacks. A possible variant of this approach will be described below according figa and 2B. On figa and 2B depicts a system, preferably having five instead of six stacks, as these drawings illustrate the possible variation of the standard system, where it is assumed that the mode SBP is reserved for a single interrupt with high priority, which does not cause a context switch.

Alternatively, a more commonly used approach, in which different stacks exceptions are tasks together, and therefore, when you log in exceptional situation any data in the stack of the exception is passed on the stack or in a single process stack privileged mode. In the above-mentioned a possible design with a modern processor, produced by arm LIMITED, this is equivalent to the transfer of data from the stacks SBP, Emergency Stop, WIA or Undefined stack in stack in User or Privileged stack. In this approach, the Garan is associated, all stacks exceptional situation (in a possible variant with arm processor stacks SBP, Emergency Stop, WIA and Uncertain stack) remain empty at all times when you may need a context switch.

The data stored when you log in exceptional situation, usually are the data that is required to continue the task after an exceptional situation. This data is defined as data "return status".

In the second approach, described above, requires that at the entrance to the exception return status was saved in the stack corresponding to the mode of functioning of the exception that was carried out in the privileged mode of the processor or the user mode of the processor and to further (data return condition has been read in the opposite direction from the stack corresponding to the mode of functioning of the exceptional situation and saved in the stack corresponding to the user mode, or privileged mode. After logging in user mode or privileged mode on the basis of these modes, you can't just save the return status as the return condition on the basis of these modes available. This process will be described in more detail below, according to monomo variant implementation, depicted on figa and 3B.

The process of storing data return condition in the stack associated with the mode of functioning of the exceptional situation, changing mode, retrieving data return status from the stack associated with the mode of functioning of the exceptional situation and save the data return state stack user mode or privileged mode requires a significant number of teams that impact adversely on code size and performance characteristics of the device data.

Additionally it should be noted that such processing is required at critical points to interrupt when interrupts are blocked, which, consequently, leads to a significant delay interrupt processing. It should be noted that the interrupt can not be unlocked until the data return status is saved in the stack user mode or privileged mode, with additional interrupts, data re status will be overwritten to save them.

BOB SMITH: "Using integer arithmetic in security mode 3 rings", the message of the conference, [Interactive] July 30, 1997 (1997-07-30), XP002197347 comp.lang.asm.x86 Found on the Internet: 33DF4272.FEA1E1A1%40intrepid.net&output=gp lain> [found on 2002-04-23] refers to the protection mechanisms. Rscr is the CPU, has 4 preferred level (PU) with PU on U and three stack for PU, control Desk 1 incorporates thermal and 2. When ring the transition from PO to PO CPU switches stacks, because the return frame is written to the stack PU.

Accordingly, it is required to provide a more effective method of storing data return status when an exceptional condition occurs.

DISCLOSURE of INVENTIONS

According to the first aspect of the present invention proposed a processing unit containing a processor to execute commands data with multiple modes of operation, each mode of operation has a corresponding stack for storing data corresponding to the mode; depending on the command data return condition, the processor writes the data of the return state of the processor from its current mode of operation in the stack corresponding to the operation mode other than the current mode of operation while remaining in the current operation.

According to the present invention, the proposed command data return status, which is used for call recording processor data return the state of the processor from its current mode of operation in the stack corresponding to the operation mode other than the current what about the operation.

It was found that the present invention allows to reduce code size and improve performance. The invention can be used in several implementations, but most preferably its use in interactive operating systems, and especially in systems that require fast context switching, for example, in a multi-tasking operating systems such as Linux (Linux).

In preferred embodiments, the implementation when an exceptional condition occurs is called the command data return status.

You should take into account that the exception can be any appropriate exceptional situation, for example, any of the standard exceptions that occur inside the unit processing data, including all types of interrupts, all types of emergency stop, exception on undefined command exception error addressing, software interrupts, and any other exceptional situation that may arise. More specifically, in preferred embodiments, an exceptional situation is one or more of the following situations: abort on error Data abort on error prefetch Exceptional Situations is mistakenly Addressing Undefined Command, a Reset, a Software Interrupt, Interrupt Request or a Request for a Fast interrupt.

Therefore, in preferred embodiments, implementation, exceptional situation, leading to a call command data can be any of a predefined set of exceptions, and this is a predefined set of commands may contain one or more interrupts.

It was found that the present invention within the preferred option implementation can reduce code size by reducing the number of commands required for the start of the exception handler. Additionally, the preferred implementation can improve performance by reducing the number of cycles required for the start of the exception handler. The fact that these cycles usually arise at the critical point, where the interrupt is blocked, allows best way to significantly reduce the interrupt latency. The preferred embodiment of the invention can be used in different implementations, but is particularly advantageous in an interactive operating systems, in particular, the low-latency interrupt processing, for example, in operating systems, opravlyaushi the drivers disk drive. In preferred embodiments, the implementation of the processing unit further comprises a set of registers, which includes several registers return the state to save the data to return the state of the processor for each operating mode, and the processor has access to registers return the state that contains the data return the state of the processor only from the current mode of operation. This requires saving the return status in the corresponding stack to change the operating mode, as if the operation mode has been changed, then these registers return status will be available only when you enter in the initial mode of the exception.

You should take into account that the stacks can be implemented in different ways. However, in preferred embodiments, the implementation of each stack has a corresponding stack pointer that identifies the location within the stack, the stack pointer for a particular stack is only available from the corresponding operating mode. Accordingly, in any given mode of operation the processor will usually have access only to the appropriate stack, so as usual he will have access only to the index of this particular stack.

In preferred embodiments, implementation, when the processing unit contains a set of registers, it is preferable that the additional set of registers included several registers stack pointer to save stack pointers for each stack, and that the processor had access only to the stack pointer register containing the stack pointer for the stack corresponding to the current mode of operation. Therefore, the processor in the current operating mode can only access the stack pointer register to get the stack pointer of the corresponding stack.

You should take into account that the command data return status proposed according to the present invention can have various forms. However, in preferred embodiments, the implementation of the command data return status field contains the ID of the stack to identify the stack, in which information will be written to return the state of the processor.

Obviously, in preferred embodiments, the implementation, where each stack has a corresponding stack pointer, the processor must be information relative to the stack pointer to write data to return the status to the appropriate location(s) within the stack and the destination. Accordingly, in preferred embodiments, the implementation identifier field of the stack is intended to define the stack pointer to the stack, in which information will be written to return the state of the processor as a consequence, when writing data return condition in the stack, providing access of the processor to the appropriate location in this stack.

Additionally, in preferred embodiments, the implementation of the command data return status contains the optional field pack, which is set to indicate that, when the entries in the stack data return condition, the stack pointer must be updated. Typically, the stack pointer is updated, but there may be conditions under which it is impractical to update the stack pointer and accordingly the optional field upgrade provides flexibility, allowing you to leave the stack pointer in the current value or to update it to account recorded in the stack data return status.

In preferred embodiments, the implementation can be used in different types of stacks that use different addressing modes determine how to update the stack pointer.

Possible variants in four different types of stack are :

Increasing the filled - stack in memory is growing up,and the stack pointer points to the last word, recorded in the stack.

Increasing empty - stack in memory is growing up, and the stack pointer points to one word above the last words, written to the stack.

Descending filled - stack in memory grows downwards, and the stack pointer points to the last word written to the stack.

Descending empty - stack in memory grows downwards, and the stack pointer points to one word following the last word written to the stack.

Consequently, in preferred embodiments, the implementation of the command data return status field contains addressing mode to identify the addressing mode stack, in which the data will be written return status; this field is used by the processor to determine the addressing mode, the corresponding stack of the destination.

When an exceptional condition occurs and other system status command data return condition may be called always, or only when the existence of certain conditions. Accordingly, in preferred embodiments, the implementation of the command data return status field contains conditions to determine the conditions for execution of the command data return condition so that the processor has executed the command data return status only is when the condition is met.

In preferred embodiments, the implementation when an exceptional condition occurs, the processor is entered in the appropriate mode of operation of the exception, therefore, if, for example, an interrupt occurs, the processor will be put into operation interrupt if there is an emergency termination, the processor will be put into operation emergency stop, etc. Respectively, the current operation mode at the time of execution of the command data return status is the mode of functioning of the exceptional situation. In a preferred embodiment, different (other) mode of operation, the stack is used to save the data return status is the preferred mode of operation, such as the preferred mode of operation in a broad sense. In an alternative embodiment, excellent operation mode may be a mode of operation of the processor prior to entering mode exceptions.

You should take into account that the data return status can have different forms. However, in preferred embodiments, the implementation of data return status contain the saved program counter and the stored state of the processor, which is schetchik the commands and status of CPU operating mode, which is the output for input in the current mode of operation, i.e. the operation of the exception.

According to the second aspect of the present invention, a method of operation of the processing unit containing a processor to execute commands data with multiple modes of operation, each of which has a corresponding stack for storing data corresponding to the mode, the method includes the step according to which, depending on the command data return condition, perform a call record processor data return the state of the processor from its current mode of operation in the stack corresponding to the operation mode other than the current mode of operation while remaining in the current operation.

According to a third aspect, the present invention proposed a computer program that operates to configure the processing unit to perform a method corresponding to the second aspect of the present invention. The invention also relates to programmetically containing such a computer program. Programmeusualiy can be any appropriate device, for example, a persistent storage device on a computer the t-drive (PSYD, CD-ROM), floppy disk, etc. or the data transfer medium such as an optical fiber, radio, etc

BRIEF DESCRIPTION of DRAWINGS

The invention is further explained in the description of the preferred variants of its implementation, with reference to the drawings figures, in which:

Figa depicts a flow diagram illustrating a possible configuration of the system that contains multiple stacks, each of which corresponds to one or more modes of operation.

Figv registers corresponding to each operation mode, in the system configuration depicted in figa.

Figa - known possible system configuration that includes three tasks, and each task has five separate stacks.

Figw - part blocks task management, similar to the system depicted in figa.

Figa - known possible system configuration that includes three tasks, and each task has two separate stack, but with three stack exception are shared between the three tasks.

Figw - part blocks task management, similar to the system depicted in figa.

Figs 4A through 4E illustrate the sequence of commands to be invoked when an exceptional condition occurs according to the known approach.

Figs 5A through 5D Illus is their sequence of commands, executed when an exceptional condition occurs according to preferred variants of implementation of the present invention.

6 depicts a block diagram illustrating a possible structure of the system that contains the processing unit according to the preferred options for implementation of the present invention.

The BEST OPTION of carrying out the INVENTION

On figa and 1B depicts a diagram illustrating a possible system having the six modes of operation and six corresponding stacks. However, the mode SBP reserved for interrupt with high priority, which does not cause a context switch, and accordingly only five modes of operation and corresponding five stacks described below and shown on the drawings. According figa, therefore, depicts five stacks 100, 110, 120, 130 and 140. Each stack has an associated stack pointer register 105, 115, 125, 135 and 145, each register stack pointer accessible only from the operation mode corresponding to this stack. It can be seen from FIGU illustrating the registers that are available in each of the five modes of operation, namely user (non-privileged) mode, privileged mode, interrupt mode, emergency stop and indeterminate mode. According figv, some is that the registers are accessible from any mode. In this possible embodiment, the stack pointers SP (RD) for the five modes have the following names: SP (CA), SP_SVC (_SVC), SP_IRQ (USSR), SP_ABT (USAWC) and SP_UND (USAWC), it is clear that in any particular mode of operation of the processor can only access the register containing the stack pointer to the stack, corresponding to a given mode of operation. Accordingly, the processor can access only to the stack associated with this mode of operation.

Privileged mode and each mode exceptions (interrupts, emergency stop and uncertain) has the appropriate data return status, which is available only from the operation mode corresponding to this return. According figv, the return status is the name LR_SVC (RSPV), LR_IRQ (RSSP), LR_ABT (RSAP), LR_UND (RNPR)and SPRV_SVC (RSPP), SPRV_IRQ (RSPP), SPSR_ABT (RSPP) and SPSR_UND (RSPP), where RS is short for "Link Register", and RSP is short for "Register Saved Processor Status". The user also has the link register, but it is not used for storing return status, so as for the user mode, there is a recurrent state, because it is not the regime of exceptions. That is, there is an exceptional situation, which will cause the log in user mode and, therefore, for a user-mode there is no need to save any data return condition. On figa chart shows the first known system configuration, in this possible embodiment, the system includes three tasks, each of which has five stacks, corresponding to the five modes of operation. Accordingly, task 1 has a stack 200 of the process, the system stack 210, stack 220 interrupts, stack 230 emergency stop and uncertain stack 240, task 2 has a stack 202 of the process, the system stack 212, stack 222 interrupt stack 232 emergency stop and uncertain stack 242, and task 3 has a stack 204 of the process, the system stack 214, stack 224 interrupt stack 234 emergency stop and uncertain stack 244.

Data return status is stored in the stack, the corresponding exception. For example, when an interrupt occurs, the task will enter the mode of operation of the interrupt, and information about the return status will be saved in the stack interrupts. As will be clear from figa, it introduces additional overhead memory consumption because of the need to support five stacks for each task.

On FIGU shows part of a control block task for each task control block task is wher is th memory the goal stores all the information needed for context switching. As part of this information must be saved to the stack pointers for each of the five stacks, and therefore, the control unit 250 task 1 will save five stack pointers, block 260 management task 2 will save five stack pointers and block 270 of the control task 3 will save five pointers in the stack. Accordingly, it is evident that the presence of five stacks for each task contributes additional memory consumption due to the need for additional memory in each block of the control task, and additional performance deterioration caused by the additional time spent saving and restoring registers in the control block of the task.

To improve the specified known way more often use the second approach, which implies the existence of a system in which some stacks exceptions are tasks together; possible version of such a system is illustrated in figa. According to a possible variant, depicted in figa, the system has 2 stack for each task, and 3 additional stack allocated by the system between the three tasks. For explanatory purposes it is assumed that the system shown n figa, has the same five modes of execution that the system depicted in figa, although it is clear that other options for implementation may have more or fewer execution modes.

Under exceptional circumstances, all of the data in the corresponding stack of the exception is passed on the stack of the user/process or system stack corresponding task, therefore ensuring that all shared stacks exceptional situation will remain empty at all moments, where you may need a context switch. As a result, in the control unit corresponding task needs to store only pointers to the stack mode of the user process and the system mode, as illustrated figv, which depicts the blocks 360, 370 and 380 control task for tasks 1, 2 and 3, respectively.

From figa and 3B it is clear that by using this approach achieved significant benefits in memory consumption and performance. For the system depicted in figa and 3B, requires SC × 2 + 3 stacks, while for the system depicted in figa and 2B, requires SC × 5 stacks where KS is the number of tasks in the system. Additionally, for the system depicted in figa and 2B, requires SC × 5 words of a data block pin which, incidentally, while for the system depicted in figa and 3B, requires SC × 2 words of a data block context. In respect of performance for the context switch between tasks in the system depicted in figa and 2B, the required loading and saving five words, while for the context switch between tasks in the system depicted in figa and 3B, the required loading and saving of two words.

Below is a code snippet written in arm assembler, representing a possible option code required when starting the interrupt for the implementation depicted in figa and 3B of the system, using the known method:

; First save the return status (registers LR and

; SPSR) in the interrupt stack. Also, in addition to

; return the status register R0 to use

; as a temporary register. It is impossible to reduce pointer

; stack as the return condition and saved R0 will be

; unloaded from the stack interrupt as soon as you change the mode.

; Not to reduce the stack pointer is safe, as it is known,

; that between storing data and read-after -

; change modes cannot be served no

; interrupts because interrupts are blocked.

(D)SU lr, lr, #4Configure LR_IRQ pointer return address
(M)STRlr, [sp, #4]; Save LR_IRQ stack interrupt
(D)MRSlr, spsr; To consider SPSR_IRQ
(M)STRlr, [sp, #-8]; Save SPSR_IRQ stack interrupt
(M)STRrO, [sp, #-12]; Save RO stack interrupt
(D)MOVrO, sp; Extract the stack pointer from RO

; Now change the mode the processor is in system mode (SVC).

(D)MRSlr, cpsr; Count register current state of the processor
(D)BIClr, lr, #0x1f; Remove the mask with bits mode using the operation Bit Clear
(D)ORRlr, lr, #0x13; Or in the correct bit rate mode SVC mode
(D)MSRcpsr_c, lr; Write the new regime in cpsr

; Now to keep the register in the stack SVC, so you can use

; as temporary. Then extract information return status and

; save RO of the interrupt stack and store it in the SVC stack.

(D)SUBsp, sp, #8*4; First create a place in the stack SVC
(M)STRr1, [sp, #2*4]; Save R1 for use as

temporary register
(M)LDRr1, [rO, #-4]; Retrieve the stored LR_IRQ in R1
(M)STRr1, [sp, #7*4]; Save LR_IRQ in the SVC stack
(M)LDRr1, [rO, #-8]; Retrieve stored in SPSR_IRQ R1
(M)STRr1, [sp, #0*4]; Save SPSR_IRQ in the SVC stack
(M)LDRr1, [rO, #-12]; Extract the RO from the stack interrupt

; At this point it is safe to unlock interrupts. It was not

; safe up to this point, as in the stack interrupt was kept

; data that could be overwritten by the assumption of service

; another interrupt to retrieve all data from the stack

; interrupt.

(D)MRSrO, cpsr; To consider CPSR
(D)BIC rO, rO, #0x80; Clear lock bit interrupt
(D)MSRcpsr_c, rO; And write back CPSR

; *** INTERRUPT UNLOCKED ***

; Loop counter before enabling interrupts =11*D+9*M

;

; Now you can continue saving the remainder of the process context

STRr1, [sp, #1*4]; Save R0 extracted from the stack IRQ

STRr2, [sp, #3*4]; Save R2 on the stack SVC
STRr3, [sp, #4*4]; Save R3 in the stack SVC
STRR12, [sp, #5*4]; Save R12 stack SVC
STRlr, [spc, #6*4]; Save LR_SVC stack SVC
......; Now to continue and maintain the interruption

The letter in parentheses, located next to each command specifies the number of memory cycles or data required for each command, where M is equal to one cycle memory access, and D is equal to one cycle of data. The number of cycles is specified, up to a point marked ***INTERRUPT UNLOCKED***, which is the time, g is e interrupt can be unlocked. The number of cycles between the start of the interrupt handler and the specified torque determines the delay interrupt processing, a large number of cycles leads to high latency interrupt processing, while a small number of cycles leads to low latency interrupt processing. In the above code snippet does not show the number of additional cycles required to transfer the hardware control of the first team of the interrupt handler. The number of these cycles is the same when using preferred embodiments of the present invention or without their use, and therefore to simplify the description it is not given.

Described below figa-4E for better illustration of the process performed by different teams, illustrated by the above code fragment.

In this possible embodiment, it is assumed that the exceptional circumstances of the termination, and accordingly, the processor has entered the operation of interrupts, where he has access to the registers 420. Data return the state of the processor mode of operation of the interrupt are stored in registers return the state designated under figa, as registers 430. In particular, the data return status registers LR_IRQ and SPSR_IRQ.

On figa also shows two stack, and the time, the stack 400 interrupts, which is accessible from the operating mode of the interrupt, and the preferred stack 410, which is not available from the operating mode of the interrupt, as in the mode of operation of the interrupt, the processor is unable to access the register containing the pointer to the privileged stack SP_SVC.

The first process that must be performed is the process of storing return status, i.e. the register contents 430 stack 400 interrupts. In addition to saving return state stack 400 interrupt is also saved contents of register R0 to register R0 can be used as a temporary register. This operation is performed four teams indicated on figa reference position 435, and is represented in the code snippet above. The original command SUB, represented in the code snippet above, you just need to configure the link register LR_IRQ to correctly specify the return address as described exemplary embodiment. Accordingly, figv illustrates the moment when the contents of the registers LR_IRQ, SPSR_IRQ and R0 stored in the stack 400 interrupts. Index SP_IRQ the top of the stack 400 interrupts are not reduced, since the return status and data R0, you just saved in the stack, the interrupt will be unloaded from the stack p is ariania, as soon as the process changes the mode. Not decrease the stack pointer is safe, because interrupts at this time is locked, and between storing data and reading them after you change modes may not be served additional interrupts.

According figv, the next step is to save the stack pointer SP_IRQ the top of the stack interrupt in register R0, which is now used as a temporary register. This will ensure that the this pointer when you exit the function mode interrupt.

At this point, the mode of the processor is changed to the system mode, which runs four teams indicated on FIGU reference position 445. Accordingly, pursuant figs, the processor is now in the privileged mode of operation, where it has access to the registers 450. As the register R0 is used modes of functioning together, the register R0 continues to contain the stack pointer for stack 400 interrupts. However, the return status is now return the state of the processor from privileged mode of operation, which is stored in the registers 440.

Now the process retains a privileged stack the contents of one of the registers, so it can be used as a temporary register. In this possible embodiment, in a privileged stack to preserve aetsa the contents of register R1. The process then retrieves information about the return condition and the stored value of R0 from the stack 400 interrupts and saves them in a privileged stack 410. These processes are seven teams indicated on figs reference position 455. In particular, the command SUB is used to reduce the index of a privileged stack eight 4-byte words. Then use the command STR to save the contents of R1 in a specific location in a privileged stack 410. Then use the command LDR and STR to save LR_IRQ in a specific location in a privileged stack with the following command LDR and STR, used to save SPSR_IRQ in a specific location in a privileged stack. It should be noted that this is a temporary register R1. The last team LDR is used to save the temporary register R1 the value R0, which is stored in the stack 400 interrupts. However, a subsequent command STR, required to save this value in a privileged stack is not executed immediately, because at this point there is a possibility to unlock interrupts, and to minimize latency, the interrupt priority is to enable interrupts. It should be noted that in all the previous points it was unsafe to unlock interrupts, t is how to stack 400 interrupts have been saved data which could be overwritten by the resolution service the second interrupt to retrieve these data from the stack 400 interrupts. Accordingly, pursuant fig.4D, unlocking interrupts there are three commands that are marked on fig.4D reference position 465 and included in the code snippet above. In fact, these commands read the CPSR register, clear the lock bit of the interrupt, and then write the appropriate data back to the register CPSR thereby effecting unlocking interrupts.

At this point you can continue saving the remaining context of the process that runs five teams STR, marked on fig.4D reference position 475. In particular, it should be noted that the first command STR saves the contents of the R1 in a specific location in a privileged stack; this register currently contains the initial data R0, the contents of R1 has already been moved to the privileged stack of one of the executed commands, according figs. Then, in the preferred stack 410 also moves the contents of the registers R2, R3, R12 and LR_SVC. It should be noted that the contents of the other registers will automatically be saved to any subsequently called by code that satisfies SITTA (Standard procedure call of compromise AWP (ATPCS)), and consequently at this moment there is no need for explicit with the wound that content in a privileged stack (if the code does not satisfy SITTA).

Then, according fige, illustrates the final state of the privileged stack 410 at this point. It should be noted that fig.4D and 4E depicts a stack 400 interrupts that contains three pieces of data, originally moved to the interrupt stack, as shown in figa. However, it is clear that these data are redundant, as they are stored in the preference stack, and accordingly, in any case, the stack 400 interrupts can be considered blank. Accordingly, at this point it becomes secure the continuation and maintenance of interrupts, which is usually done through a context switch to another task.

As you can see, when using the above-mentioned known method, the interrupt handler uses eleven cycles of the D and nine cycles of the form M before will be able to unlock interrupts, which leads to relatively high latency interrupt processing. Also, before you could unlock interrupts, use a sufficiently large number of teams. As you can see from the above code snippet and figa to 4E, when using this known approach, before you could unlock interrupts, you need to perform twenty-commands.

After describing the process of starting abortion is ment to implement the system, depicted on figa and 3B, according to the method, the following will describe the process used to start the interrupt for the implementation of the same system, according to preferred variants of implementation of the present invention. In particular, for ease of understanding the following is a code snippet that illustrates the code required at start of interruption, for the implementation of the system depicted in figa and 3B according to a preferred variant implementation of the present invention:

; Save return status directly in the stack SVC,

; using SRS.

(D)SUBlr, lr, #4Configure LR_IRQ to specify a return address
(2M)SRSDBsp_svc!; Save return status
; stack SVC

; Now change the mode the processor is in system mode (SVC), at the same

; time in unblocking interrupts. At this point safely

; unlock interrupts, because the return saved state

; stack SVC. Therefore, the interrupt stack is empty, and

; valid context switch without context

; interrupt stack switching (i.e. without heart and soul is on the availability of

; separate interrupt stack for each task).

(D)MRSlr, cpsr; To consider cpsr
(D)BIClr, lr, #0x1f+0x80; Remove the mask with bits mode and clear the interrupt
(D)ORRlr, lr, #0x13; Or in bits mode SVC mode
(D)MSRcpsr_c, lr; Write back the new mode bits and interrupt

*** INTERRUPTION UNLOCKED ***

; Loop counter before enabling interrupts

=5*D+2*M

; Now interrupts unlocked. To continue saving

the rest of the context of a process.

STMDB sp!, {r0-r3, r12, lr}

...; Now to continue and maintain the interruption

To the above well-known piece of code symbols in parentheses denote the number of cycles, and the characters 2M next SRSDB point to two cycles of the memory.

Below is the code snippet will be described according figa - 5D schematically illustrating the processes performed by the various teams of this code.

Under this possible variant likewise possible variant described above with the publicly figa - 4E, it is assumed that the exceptional circumstances of the termination, and accordingly, the processor has entered the operation of interrupts, where he has access to the registers 520. Data return the state of the processor mode of operation of the interrupt are stored in registers return status indicated on figa, as registers 530. On figa also shows the stack 500 interrupts and privileged stack 510.

The code fragment begins with a command SUB is identical to the command included in the above-described known piece of code, and, as mentioned above, this command is required to provide instructions with link register interrupt LR_IRQ the correct return address.

Then run a new command, proposed according to the preferred options for implementation, namely the SRS team, designed to save the data return status directly in the privileged stack 510 when functioning in the mode of operation of the interrupt. The format of this command is described in detail below. However, it should be noted that the symbols DB added to the SRS team to indicate that this possibility exists addressing mode privileged stack is Decreasing. The command also contains a field that identifies the stack, in which the data will be saved return status on the TES field in a possible variant contains a pointer SP_SVC stack for the privileged stack 510. And, finally, the exclamation point at the end of the command indicates that the stack pointer must be updated when saving data return status.

Figv illustrates the contents of the interrupt stack and the contents of the privileged stack after execution of the command SRS. In particular, it should be noted that in the preferred stack 510 was added to the contents of register LR_IRQ and the contents of register SPSR_IRQ, and a pointer SP_SVC privileged stack has been updated. At this stage, it becomes possible to change the operating mode of the CPU in privileged mode because the contents of the data return status of the operation mode interrupt was stored in the preference stack. In addition, because the data return status is stored directly in the preference stack 510, and the stack 500, the interrupt is left blank, then at this point is safe to unlock interrupts. Because the stack 500 interrupt is empty, the valid context switch, without having to context switch interrupt stack, i.e. without the need for a separate interrupt stack for each task, and accordingly the process can be used within the system, such as shown in figa and 3B.

Four commands are used to change the dir is mA operation and unlock interrupts marked on figs reference position 540. Figs additionally depicts registers 550, which is accessed from privileged mode of operation, including registers 560 containing the return status of a privileged mode of operation.

At this point, the process can continue saving the remaining process context. As related registers can be stored in sequential locations of the privileged stack, it is possible to perform this operation through a single command STM marked on figs reference position 570, the process schematically illustrated by the different lines between registers 550, which is available from the privileged Exec mode and privileged stack 510. The characters DB added to the STM team, determines that the preferred stack operates in accordance with a mode of addressing Declining Before the exclamation mark after the identifier of the stack pointer in the command STM means that the stack pointer must be adjusted. Then in the command, specify the registers to be saved.

Fig.5D illustrates the contents of a privileged stack 510 after the command STM. It should be noted that the contents of the privileged stack 510 is identical to the content of a privileged stack 410 illustrated five, although the order of the data several different, and accordingly it is seen that the process according to preferred variants of the implementation illustrated figa - 5D, leads to the same result as the well-known process that is illustrated figa - 4E. However, the above code snippet, it is obvious that the method according to the preferred variant implementation, including a new team SRS provides the use of the interrupt handler only five loops D and two cycles of the form M before you can unlock interrupts. When comparing the number of commands that can be used before it will be possible to unlock interrupts, it is seen that the interrupt handler using the approach according to a preferred variant implementation must perform six teams to unlock interrupt, instead of the twenty teams that were required to do according to well-known approach.

Therefore, in General, when using the approach according to a preferred variant implementation of the present invention, the interrupt handler uses a smaller number of cycles of the form (D, a smaller number of loops M and a smaller number of teams. It should also be noted that in the system with slowly working memory cycles of the form M can be much slower than the cycles of the D, and for each executed command to fetch the command is s can be performed additional sampling in memory.

Accordingly, when considering a possible system in which the cycle of a species M is four times slower than the cycle of the D, for the interrupt handler using the method in accordance with the preferred embodiment, and for the interrupt handler, do not use this method, we obtain the following performance characteristics; however, the following equations (D) denotes the number of cycles of data (M) denotes the number of memory cycles, and (I) denotes the number of commands, each of which may be subject to additional sample memory:

Without the use of a method according to a preferred variant implementation:

Using the method of the preferred option implementation:

After illustrating the advantages of using the approach according to a preferred variant implementation of the present invention are described in detail below new command SRS. In particular, the description of the command SRS preferred embodiments of the present invention, in an abbreviated form PC - Naur form:

SRS{<COND>}<addr_mode> <fully_qualified_stack_pointer>{!}

<COND>::=

EQ | NE | CS | CC | MI | PL | VS | VC | HI | LS | GE |

LT | GT | LE | AL | HS | LO

<addr_mode>::= IA | IB | DA | DB | FD | ED | FA | EA

<fully_qualified_tack_pointer> :: =

SP_USER | SP_FIQ | SP_IRQ | SP_SVC | SP_ABT | SP_UND

!Z & ! (NV)
<COND>DescriptionCondition
EQEqual toZ
NEUnequally!Z
CSThere are transferC
HSUnsigned higher or sameC
CCNo transfer! C
LONo sign below!C
MIMinusN
PLPlus!N
VSThere is an overflowV
VCNo overflow!V
HIUnsignedC & !Z
LSUnsigned lower or same!C | Z
GEGreater than or equal to!(NV)
LTLess thanNV
GTMore than
LELess than or equal toZ | (NV)
ALAlways1
<addr_mode>Description
IAIncreasing after (equivalent EA)
EAIncreasing blank (IA equivalent)
IBGrowing up (equivalent to FA)

FAIncreasing filled (equivalent IB)
DBDecreasing empty (equivalent to FD)
FDDescending filled (equivalent DB)
DADecreasing after (equivalent ED)
EDDescending empty (equivalent to DA)
<fully_qualified_stack_pointer>Description
SP_USERThe stack pointer mode

user
SP_FIQThe stack pointer mode

Zap the wasp on the fast interrupt
SP_IRQThe stack pointer mode

IRQ
SP_SVCPointer privileged stack
SP_ABTThe stack pointer failure
SP_UNDThe pointer is undefined stack

Specialists in the art known short form PC - Naur form. However, here's a brief description. In abbreviated form, the elements in curly brackets "{...}" refers to pfacultyie items, the items in angle brackets (<...>" denotes the substituted symbols that can be replaced with the given extension designation. The "|" character is used to separate symbols list of symbols and can be interpreted as "or", meaning that exactly one of these designations can be used as a substitute symbol.

Consequently, it is possible to notice that the team SRS stores the return status of the processor in the stack, a certain <fully_qualified_stack_pointer>, which defines the stack that is associated with one of the available modes. If <fully_qualified_stack_pointer> is accompanied by the symbol "!", this indicates that <fully_qualified_stack_pointer> will be updated after the operation.

In for the m variant with processor arm provided with six modes of operation, namely user mode, privileged mode, emergency stop, indeterminate mode and two-mode interrupts, WIA and SBP, and accordingly, as shown in the above reduced-form PC - Naur form, <fully_qualified_stack_pointer> can take any of the values SP_USER, SP_FIQ, SP_IRQ, SP_SVC, SP_ABT or SP_UND.

<COND> specifies one of several conditions to perform the operation must be true. The CPSR register, which is accessible to the processor, which has four check box is defined here as N, Z, V, C. the Flag N is set to one if the result of the last arithmetic operation was negative flag Z is set to one if the result of the last arithmetic operation was zero, the flag V is set to one if the result of the last arithmetic operation resulted in an overflow, and the flag C is set to one if the result of the last arithmetic operation resulted in the transfer. In abbreviated form PC - Naur form for the above commands SRS, use the table that shows the different values that can take the field <COND>, together with a description of each value, and determining what they equivalent in terms of flags N, Z, V and C, in the CPSR register. Therefore, this table actually illustrates how the processor on the basis of N, Z, V and C, in the CPSR register, determines whether to execute the command. For example, if the field <COND> is set to MI, then the processor will examine whether the check box N in the unit, and, if set, executes the command, otherwise the command will not be executed. If the field <COND> is not defined, it is equivalent to the symbol "AL" for the field <COND>, determines that the operation should always be performed.

Field <addr_mode> specifies the addressing mode for the operation, and according to a preferred variant implementation there are different addressing modes listed above, together with the shortened form of the PC - Naur form for the team. As mentioned above, the field <fully_qualified_stack_pointer> specifies the fully qualified name of the stack pointer associated with one of the execution modes for the processor.

The following are possible options command SRS, which can be derived from the reduced form of PC - Naur form:

SRSDB SP_SVC!

SRSEQDB SP_SVC!

SRSEQDB SP_SVC

Figure 6 shows a block diagram illustrating a system containing a processing unit according to the preferred options for implementation of the present invention. According to preferred variants of the invention, the processing unit takes the form of core 60, the CPU generated within the CPU 10. The core 60, the CPU will contain processor commands, data and the set of registers 70, which is available to the processor. The CPU 10 generally includes a core 60 of the CPU and a few other optional elements, for example, Manager 45 memory (DP) and the cache 50.

The CPU 10, typically through a bus 30 is connected with other elements and, therefore, can be connected with a permanent storage device 40 (ROM) and random access memory device 20 (RAM). The ROM 40 may be configured to store, among other information, command 80, which must be performed by a core 60 of the CPU. According to preferred variants of implementation of the present invention, stacks 90 provided for each operating mode of the processor may be stored in RAM 20.

From the above description of the preferred alternative implementation of the present invention, it is necessary that its use leads to a number of advantages. First, the use of the preferred alternative implementation of the present invention can reduce the code size. In the described options shows how you can use the preferred implementation to reduce the number of commands that can be used at the start of the interrupt handler, with twenty to six teams. Additionally, the use of the preferred option implementation will usually lead to a better work characteristical the examples described above, shows a preferred method of implementation decreases from 127 to 37 the number of cycles at the start of the interrupt handler. Additionally, reducing the number of cycles also reduces the latency of interrupt processing, because these cycles are usually performed at the critical point, where interrupts are blocked.

When using the method according to the preferred variant of the invention, an additional advantage is that it can be used to reduce the power consumption of the processor, which is extremely important in devices powered by batteries, such as mobile phones and personal digital assistants (OCA). If we consider the system based on the above options and illustrations, and assume that for servicing high-priority interrupts will require continuous support this system, the response time to interrupts in 10 microseconds, it becomes clear that the system must operate at a speed sufficient to ensure compliance with 127 cycles for 10 microseconds, as in the case of systems using a well-known approach. However, if the system uses the method according to preferred variants of implementation of the present invention, the required performance, sufficient to ensure compliance with 37 cycle is in 10 microseconds. Therefore, the following relations define the required minimum clock frequency:

Without using the method according to the preferred options for implementation:

l.0E-5 Seconds/127 Cycles = 7.874E-08 Seconds/Cycle

1/7 .874E-08 = 1.27E + 7 Cycles per Second = 12.7 MHz

Using the method according to the preferred options for implementation:

l.0E-5 Seconds/37 Cycles = 2.701E-08 Seconds/cycle

1/2 .701E-08 = E+6 Cycles per Second = 3.7 MHz

As consumed by the processor power depends on the frequency approximately in a linear manner, a system using the method according to preferred variants of the implementation can use about 29% (3.7÷12.8×100) from power similar systems that do not use the method according to the preferred variant implementation.

Although the above has been described a particular variant of the invention, it is obvious that the invention is not limited to this option, and that in the framework of the present invention may be amended or supplemented. For example, without leaving the scope of the invention, can be obtained by different combinations of the features of dependent and independent claims.

1. A processing unit containing a processing unit for executing commands, data processing, and the processing unit has many modes of operation, each of which has sootvetstvujushij stack for data storage, corresponding to this mode, the processing unit is configured to write in response to the command data return data status return the status of the processing unit from its current mode of operation in the stack corresponding to the operation mode other than the current mode of operation while remaining in the current operation.

2. The processing unit according to claim 1, in which the command data return status is called when an exception occurs.

3. The processing unit according to claim 2, in which the exception is any exception from a predefined set of exceptions.

4. The processing unit according to claim 3, in which a predefined set of exceptions includes one or more interrupts.

5. The processing unit according to any one of the preceding paragraphs, further containing a set of registers includes a set of registers return the state to save data return status block processing for each mode of operation, and the processing unit is configured to access only registers return the state that contains the data return status of the processing unit, from the current mode function of the system.

6. The processing unit of claim 1, wherein each stack has a corresponding stack pointer that identifies the location within the stack, and the stack pointer for a particular stack is available only from the corresponding operating mode.

7. The processing unit according to claim 5, in which each stack has a corresponding stack pointer that identifies the location within the stack, and the stack pointer for a particular stack is available only from the corresponding operating mode, and the set of registers includes a set of registers stack pointer to save stack pointers for each stack, and the processing unit is configured to access only to the stack pointer register containing the stack pointer to the stack, corresponding to its current mode of operation.

8. The processing unit according to claim 1, in which the command data return status field contains the ID of the stack to identify the stack, in which data should be written return status block processing.

9. The processing unit of claim 8, in which the identifier field of the stack is intended to set the stack pointer to the stack, in which data should be written return the status of the processing unit, this clicks the zoom, providing access processing unit to the corresponding location in the specified stack while writing to the specified data stack return status.

10. The processing unit according to claim 9, in which the command data return status contains the optional field pack, which is set to indicate the need to update the stack pointer after writing data return condition in the stack.

11. The processing unit according to any one of p-10, in which the command data return status field contains addressing mode to identify the addressing mode stack, in which data should be written return status.

12. The processing unit according to any one of p-10, in which the command data return status field contains conditions for specifying command data return condition, so that the command data return condition was executed by the processing unit only when the specified conditions.

13. The processing unit according to claim 1, in which the current operation mode is the mode exceptions and operation mode different from the current operating mode is the preferred mode of operation.

14. Device processing and data according to claim 1, where the current operation mode is the mode exceptions and operation mode other than the current operation mode is the operation mode processing unit to enter exceptions.

15. The processing unit according to claim 1, in which the data return status contain the saved program counter and the stored state of the processor.

16. The method of operation of a processing unit containing a processing unit for executing commands, data processing, and the processing unit has many modes of operation, each mode of operation has a corresponding stack for storing data corresponding to the mode, the method includes a step whereby in response to the command data return status compel the processing unit to write data return status of the processing unit from its current mode of operation in the stack corresponding to the operation mode other than the current mode of operation while remaining in the current operation.

17. The data medium containing the recorded thereon a computer program that configures the processing unit to perform steps of the method according to item 16.



 

Same patents:

FIELD: computer science.

SUBSTANCE: device has n-byte query register, query limits location systems, each of which consists of counting timer and OR element, OR element, AND element, keys cascade.

EFFECT: higher reliability and speed of operation.

1 dwg

The invention relates to computing and is used in automatic control systems of technological processes

The invention relates to computing, and in particular to a device priority, and can be used to control access to multiple subscribers to the shared resource

The invention relates to the field of computer technology, in particular to a device priority service requests

The invention relates to systems and methods for displaying information on remote computers

The invention relates to the field of computer technology, in particular to a device priority service requests

The invention relates to the field of computer technology, in particular to a device priority service requests

The invention relates to computing

The invention relates to computing, and in particular to a device priority service requests

Spin echo processor // 2189580
The invention relates to the field of radio and can be used in systems processing pulsed signals

The invention relates to computer techniques, in particular to a device that occupies a middle position between laptops and pocket computers

The invention relates to the fields of computer and telecommunications equipment, in particular to devices for processing and distribution of data from different information systems with different information display systems

The invention relates to automation and computer engineering and can be used for processing character information

FIELD: method and device for processing data for preserving recurrent status in data processing device.

SUBSTANCE: device has data processing block, having multiple functioning modes, for each of which special memory stack is present. Method describes operation of this device. Data carrier contains program, configuring data processing device for performing stages of method.

EFFECT: decreased size of code and decreased interruption processing delay.

3 cl, 16 dwg

FIELD: physics; radio.

SUBSTANCE: invention relates to radio engineering and can be used in radar systems, for example in radar systems with synthetic aperture. The simplified system comprises a basic system and several units for active phased array generation. Each unit comprises a transceiver for wireless reception of a signal transmitted from a basic system, for wireless transmission of signals to a target, for wireless reception of signals from a target and for wireless transmission of the received signal back to the basic system. The system also comprises a subsystem for signal interference suppression between the transmitted and received signals. Each unit can also comprise a circuit for local generation of electric energy.

EFFECT: reduced weight, simplification and reduced cost.

16 cl, 28 dwg

FIELD: computer science.

SUBSTANCE: device has n-byte query register, query limits location systems, each of which consists of counting timer and OR element, OR element, AND element, keys cascade.

EFFECT: higher reliability and speed of operation.

1 dwg

FIELD: method and device for processing data for preserving recurrent status in data processing device.

SUBSTANCE: device has data processing block, having multiple functioning modes, for each of which special memory stack is present. Method describes operation of this device. Data carrier contains program, configuring data processing device for performing stages of method.

EFFECT: decreased size of code and decreased interruption processing delay.

3 cl, 16 dwg

FIELD: engineering of information processing systems.

SUBSTANCE: system contains master-system for processing information, interface, central communication device, client system for processing information, object model. In accordance to method each master system sends to central communication device elements of its data array determined in appropriate master-representation, while in master-representation of connected master system elements of data array are contained, for which system has data priority.

EFFECT: simplified specification and development of interfaces between technical applications.

2 cl, 6 dwg

FIELD: engineering of interrupt processing mechanisms in computer systems.

SUBSTANCE: system contains processor with multiple contexts for execution of commands stored in memory. In response to common interrupt logical processors of processor with multiple contexts compete for receiving access to jointly utilized register. First logical processor gaining access to aforementioned jointly utilized register processes common interrupt. Remaining logical processors return from interrupt.

EFFECT: increased productiveness of system.

4 cl, 5 dwg

FIELD: computer engineering, possible use in data exchange systems and local computing networks.

SUBSTANCE: device contains N≥2 client blocks, clock impulse generator, N client time controllers, OR element, AND-NOT element, selector-multiplexer, two N-input AND-NOT elements, two priority encoders, main wait time controller.

EFFECT: increased probability of timely servicing of clients under conditions of real functioning process of data exchange systems, with continuous dynamics of change of modes of different priority requests from clients.

4 cl, 7 dwg

Up!