Turbo-decoding device and method

FIELD: turbo-decoding in communication systems.

SUBSTANCE: high-speed buffer memory is disposed between receiver buffer memory and turbo-decoding device and operates at same frequency as turbo-decoding device; decoding device reads out information bits stored in receiver buffer memory through high-speed buffer memory, enters delay for read-out information-bits for time required by turbo-decoding device, and then sends delayed information bits to decoding device including flexible input and flexible output of data incorporated in turbo-decoding device; information bit output is effected by receiver buffer memory at operating or clock frequency of turbo-decoding device.

EFFECT: provision for matching operating frequency of turbo-decoding device and that of buffer memory.

32 cl, 20 dwg

 

The technical field to which the invention relates.

The present invention relates, in General, to a device and to a method of decoding in a communication system and, in particular, to a device and to a method of implementing turbodecoding.

The level of technology

In digital communication systems to effectively correct errors that may occur in the communication channel during transmission of data, usually used codes are forward error correction (PIO, FEC). This increases the reliability of data transfer. Codes are forward error correction include turbo code. Since the turbo code are better able to provide error correction for high-speed data transmission compared to the convolutional code, it is approved for use in synchronous multiple access code division (mdcr, CDMA) standard 2000, MDCR (CDMA2000), and asynchronous universal mobile telecommunications system (USMS, UMTS), both of which attracted widespread attention for use as a mobile communication system of the third generation.

1 shows a block diagram showing an example of a receiver of a mobile communication system of the third generation. Figure 1 shows the design of the receiver, for example, the specification "1x evolution - data and speech" (1x EV-DV), which allows high-speed transmission is in data packets.

As shown in figure 1, the processor 10 of the received signals performs the processing of the received signal in the band of radio frequencies (RF)to intermediate frequency (if) and in the frequency band of the original signal. The signal processed by the processor 10 of the received signals, share through appropriate channels. The receiver 30 performs signal processing of the main direct channel (MIC, F-FCH), the signal of the direct channel (WPC, F-SCH) and a signal allocated forward link control (HBCMS, F-DCCH). The receiver 40 performs signal processing forward link packet data (PCPD, F-PDCH). The receiver 50 is processing the forward link transmission control data packets (PCEPD, F-PDCCH). The receiver 40 includes blocks 42, 44, 46 and 48. Function block 42 is to minimize losses that may occur in the channel, and it includes the receiver component of the signal and the device Association (both of which are not shown). Function block 44 is the transformation of the signal in such a way as to enable the decoding of the channel, and it contains a buffer demodulation device removal Walsh code, the unit conversion character conversion and decoder pseudo-random sequences (all not shown). Function block 48 is an implementation of the decoding and presentation of the decoding in the first Phi is practical level 70 L1 to refer to it, and it contains the device turbodecoding and the output buffer (both of which are not shown). Function block 46 is transferred to the character demodulation block 48 for decoding, and it contains a device combining device for the treatment of shuffling, directed interleaver buffer and a storage device (all not shown).

Search device 20 is an element that searches the received signal, and the controller 60 of the hybrid query with auto repeat (GSAP, HARQ) is an element providing for the issuance of a request for re-transmission character, the reception of which was unsuccessful.

On the block diagram of Figure 2 shows an example of a conventional device turbodecoding and, in particular, shows an example of a detailed structure of the block 48 device turbodecoding shown in figure 1. Shown in the drawing the device turbodecoding created, for example, through a scheme with flexible input and flexible output (SISO). The device turbodecoding can also be implemented using a scheme based on the maximum a posteriori probability (MAV, MAP, or schema-based Viterbi algorithm with flexible data output by exchanging the contents of the registers (RESOVA), which are used instead of the SISO scheme. The SISO scheme is a scheme for the calculation of d is) proved the probability for the symbol, and the scheme RESOVA is a calculation of the probability for the code words given path, which passes through a symbol in the form of a long code word.

With reference to Figure 2, the symbols (data bits)stored in the buffer memory 46-1 block 46, as shown in figure 1, serves on the input unit 48. In the buffer storage device 46-1 carry out separate remembering systematic code is a systematic code perenesennyj bits, and code No. 1 parity code and No. 2 parity, which are nonsystematic codes perenesennyj bits. The bits of the systematic code bits and parity codes simultaneously served from the buffer storage device 46-1 in block 48. For example, in the system, the corresponding BOM 1x evolution - data and speech" (1x EV-DV), a buffer memory device 46-1 is a buffer storage device for quasitopological of turbo code (CDTC, QCTC), which serves to memorize the symbols received from the transmitter, after encoding by the code CDTC (QCTC). Since one code, the output of which is carried out from the buffer storage device 46-1, consists of M bits, and from the buffer storage device 46-1 discharge of all three codes, which are systematic code and parity codes: code No. 1 parity and the od No. 2 parity between the buffer storage device 46-1 and block 48 created 3×M-bit bus, and codes from the output buffer memory device 46-1 served in the multiplexer (MPX) 48-1 block 48.

Block 48 device turbodecoding contains a multiplexer 48-1, the unit 48-2 SISO decoding (or device decoding scheme SISO), interleaver 48-3 facing interleaver 48-4, buffer 48-5 output and the device 48-6 control by cyclic redundancy code (CEC, CRC). The multiplexer 48-1 provides multiplexing of bits received from the buffer storage device 46-1, with the output of the interleaver 48-3 and exit facing the interleaver 48-4. The unit 48-2 SISO decoding performs SISO decoding of the signal obtained at the output of multiplexer 48-1, using the scheme shown in Figure 3. Interleaver 48-3 performs interleaving signal obtained at the output device 48-2 SISO decoding, and turned interleaver 48-4 carries out the conversion of the alternation signal obtained at the output device 48-2 SISO decoding. Buffer 48-5 output provides storage of the converted alternation obtained by facing the interleaver 48-4, so that the processor 70 of the first level L1 can obtain information about the converted alternations. The device 48-6 control through the m CEC checks of the converted interleave, obtained by facing the interleaver 48-4, using the CEC and transmits the verification result using the CEC processor 70 level L1.

On the block diagram of Figure 3 shows an example of a conventional device SISO decoding. The drawing shows an example in which the device SISO decoding is implemented using the scheme, it provides a mode of "sliding window", and is here assumed that the number of Windows is equal to 2. The device SISO decoding is identical in its basic structure to the device MAP-decoding (or device decoding scheme MAP) and differs from the device MAP-decoding only the value that is obtained at its output.

With reference to Figure 3, the device SISO decoding in the decoding process computes several metrics. That is, during the operation of the decoding device SISO decoding computes the Delta metric, alpha (α) metrics, beta (β) metric and the logarithmic likelihood ratio (LOP, (LLR). The demultiplexer 205, designated as SLE (DEMUX), accesses the information bits stored in the buffer memory 46-1, with a predetermined frequency, i.e. with a frequency three times higher than the clock frequency (or operating frequency) device turbodecoding, and generates the first output signal is l (1), the second output signal (2) and the third output signal (3). Block 210 calculate the Delta metric contains three computing devices 211-213, computes the Delta metric, respectively for the first, second and third output signals (1)to(3). The Delta metric is calculated by device 211 calculate the Delta metric, enters the device 220 calculate the alpha metric, and it calculates the corresponding alpha-metrics. Block 230 calculate beta metric consists of two computing devices 231 and 232, and a multiplexer 233. That is, the block 230 calculate beta metric includes computing device 231, which is used to calculate the first beta (β1) metric, computing device 232, which serves to calculate a second beta (β2) metric, and the multiplexer 233, which is used for multiplexing the results of calculations obtained by computing devices 231 and 232. Block 240 calculate LOP consists of three computing devices 241 to 243, it enters the alpha metric, calculated by device 220 calculate the alpha metric and the result of multiplexing, obtained by means of the multiplexer 233, and it computes the corresponding values of LOP. Block 250 subtraction consists of three subtractive devices 251-253, which subtract the first output signal (1)obtained from demultiplexor is and 205, from the values of LOP calculated by device 241 to 243 calculate LOP, and supplying the result of the subtraction in the interleaver 48-3 and turned interleaver 48-4, shown in figure 2, for interleave/converted alternations.

As described above, the conventional device SISO decoding consists of a computing unit, the Delta metric, the unit for computing the alpha metric and the computing unit beta metrics that calculate metrics and evaluation unit LOP, providing the decoding metric based on the probability. In this embodiment, the computing unit beta metric consists of two computing devices that corresponds to the number of Windows.

The Delta metric, also known as the "metric status, displays the probability of transition of the encoder from one state to another state. Alpha (α) metric, also known as the "metric transition into a subsequent state, represents the sum of the metric values of the probability of transition from the previous state to the next state and the metric values of the probability of return to a previous state. α-metric refers to the accumulated probability for the time period of the signal calculated from the first received signal, and the calculation carried out sequentially. Beta (β) metric, also known as the "metric return to the previous the current state", represents the accumulated probability of a transition from the current state to the previous state. If the computed both metrics, α-metric and β-metric, computed, and the value of the LOP. LOP represents the probability of occurrence of symbol and expresses the probability of occurrence of "1" to the probability of occurrence of "0" on a logarithmic scale. Each device 241 to 243 calculate LOP, computes LOP, calculates the probability of occurrence of the symbol based on the probability of transition to the next state and the previous state. Here a positive value LOP displays the symbol "1"and a negative value LOP displays the symbol "0". To decode the signal, the reception of which is implemented in this way, the device SISO decoding calculates the values of both metrics: value α-metric and value β-metrics. In this case, since the calculation of the values βmetrics should be performed in the order reverse to the order of received signal stored in the buffer memory 46-1, the value of the LOP cannot be calculated until then, until the complete calculation β-metrics.

On Figa and Figb shows a block diagram depicting examples of metrics are calculated by the usual device of SISO decoding of Figure 3. In particular, figure 4 shows the process of computing α -metrics and Figb shows the process of computing β-metrics. With reference to Figa and Figb, you should pay attention to the fact that the process of computing α-metric differs from the process of computing β-metrics. Computation αmetrics αkeffected on the basis of (k-1)-th α-metric, which represents the previous value, and calculating βmetrics βkeffected on the basis of (k+1)-th β-metric, which represents the following value. To calculate β-metrics in this way the reference to the adopted signal should be performed in the order opposite to the order in which it was executed by his reception that leads to the presence of a source of delay for the entire duration of the received signal.

On the flowcharts of Figa and Figb shows an example of the execution order calculation by conventional devices SISO decoding of the 3-mode frame and window mode. In particular, Figa shows how to compute the metric unit 48-2 SISO decoding mode of the frame, and on Figb shows how to compute the metric unit 48-2 SISO decoding of Figure 3 in window mode.

With reference to Figa, because the calculation of metrics and values LOP designated as λcarry out after fully calculated β-metric, there is the initial delay equal to the period of the frame. The device SISO decoding with such a scheme, operating in the mode frame, computes the value of the LOP λ by calculating α-metrics after calculating β-metrics. Therefore, when calculating β-metrics, there is a delay in time. To reduce this source of delay was proposed scheme, operating in the "sliding window".

With reference to Figb, in window mode the unit 48-2 SISO decoding to calculate β-metric divides the received signal into sections of desired length. In that case, if the computation β-metrics implemented by dividing the received signal into sections of desired length, the originally calculated values are imprecise probabilities, and calculate more accurate values carried out later. In fact, when calculating the LOP can be used the value calculated for the period of time in which computed the exact value. Here, for convenience of computing the length of the time period in which inaccurate calculation, is set equal to the length of time to perform accurate calculations. While in one window calculate the exact values in another window calculate inaccurate values, thereby alternating the exact values and inaccurate values. Example calculations βmetrics using two OK the n is the block 230 calculate beta metric, shown in Figure 3. Therefore, the unit 48-2 SISO decoding in window mode calculates three values, which are α-metric β1-metric and β2-metric. Calculating the Delta metrics should be carried out before the calculation of these three metrics.

With reference to Figure 3, the devices 211-213 calculate the Delta metrics receive data bits of the received signal stored in the memory cells of the buffer memory devices 46-1, with different addresses, and calculate the corresponding Delta-metric. That is, as shown in Fig.7, devices 211-213 calculate the Delta metrics provide read signals from different locations of the buffer memory devices 46-1 during a single clock cycle at the operating frequency of the device turbodecoding.

On the block diagram of Fig.6 shows an example of the processing sequence of the input information bits and output metrics by device SISO decoding, is shown in figure 3. With reference to Fig.6, it is necessary to pay attention to the fact that devices 211-213 calculate the Delta metrics included in the device 48-2 SISO decoding, serves the information bits of the received signal stored in the cell buffer memory devices 46-1, with different addresses. Horizontal line represents the time axis, and you can see that filing various inform the information bits in the device 211-213 calculate the Delta-metric exercise after some time. To provide this functionality access to the buffer storage device 46-1 should be three times faster than the operating frequency of the device turbodecoding. That is, as the clock frequency for the buffer storage device 46-1 should be used clocked three times greater than the clock frequency of the device turbodecoding.

Figure 7 shows a time chart that shows an example of timing for operation of the access device SISO decoding of Figure 3 to the buffer storage device. With reference to Fig.7, the device SISO-decoder reads the data bits Data1 has (data1), dannie (data2) and Donnie (data3), stored in the memory cells of the buffer memory devices 46-1, with different addresses address1 (addr1), address2 (addr2) and adress (addr3), and calculates the Delta metric for α-metric, Delta metric for β1-metrics and the Delta metric for β2-metrics. For this operation are read from the buffer storage device 46-1 perform with a frequency three times greater than the clock frequency of the device turbodecoding.

The operation of the access to the buffer storage device and the processing operation of the data that is shown in Fig.6 and Fig.7, takes into account the assumption that the size of W (or length) of the window W=4, the cat is who is much smaller, than actually used length. In actual use in high-speed (or high) the device turbodecoding the window size is set in the range from 24 to 48 (W=24˜28), and depending on circumstances may be set greater its value. Despite the fact that changing the window size W, the structure of a buffer do not change and do not change the General view of the schema sequence data, but have it increase in proportion to length.

With reference to Fig.6, the letters of the alphabet written in each field of the data applied to the input of the Delta unit, display data bits stored in the memory cells of the buffer memory devices 46-1, with different addresses, and represent the value used in the device 210 calculate the Delta metric. In that case, when calculating β-metrics is carried out before the calculation of α-metrics, two devices 231 and 232 computation β-metrics are alternately (see Fig.6 with reference to the period T1 and the period T2). At the same time carry out the calculation of α-metrics, starting with the moment of time when the calculated reliable β1-metric (see the period T2). After calculating β-metrics during the initial period W discharge imprecise probabilities, but in the next period W implement Aut output metric values with the correct probability. The output signal α, the output signal β1and in the output signal β2the letters of the alphabet in each box indicate the order of the metric. Because coming from the output of the computing devices 212 and 213 Delta-metric signals for β1and β2alternate with each other, it β-metrics calculated by devices 231 and 232 calculate beta metrics are continuous. The circle shown in Fig.6 dashed line indicated that it is needed in the current time information bits are received signals stored in different places or in different memory locations of the buffer memory devices 46-1 with address d, n and f.

Meanwhile, if it is assumed that the device SISO decoding, shown in Figure 3, is used in the system, made according to the specification "1x evolution - data and speech" (1x EV-DV), in which it is necessary to provide high speed data transmission, it is required that the device turbodecoding, operating at a frequency of approximately 30-60 MHz. Therefore, the operating frequency of the buffer storage device 46-1 must be defined in the range from 90 to 180 MHz, which is three times the operating frequency of the device turbodecoding. This operating frequency of the device turbodecoding is impractical for Windows is knogo mobile communication device, for which it is necessary to ensure low power consumption.

As described above, the system, the corresponding BOM 1x evolution - data and speech" (1x EV-DV), is a typical mobile communications system of the third generation, enables high-speed transmission of data packets. In such a communication system to provide high performance requires high-speed device turbodecoding. To ensure high-speed decoding flow of information bits (or characters)stored in the buffer memory device is connected to the previous stage device turbodecoding, the device turbodecoding there should be proper way. The device SISO decoding with the scheme operating in the mode of the moving window, can reduce the initial delay in comparison with the device SISO decoding with the scheme operating in the mode frame. Therefore, the preferred option is the use as a device turbodecoding device SISO decoding with the scheme operating in the mode of the moving window. The device SISO decoding with the scheme operating in the mode of the moving window, performs a decoding operation after the reading from the buffer storage device information bits, with testwuide the number of Windows. For example, if the number of Windows is equal to 2, the device SISO decoding computes the metric for decoding the three reading data bits from the buffer storage device. This operation does not cause any problems in the case when the device turbodecoding runs at a low speed, but it can cause problems when the device turbodecoding works with high speed. This is because in the case when the buffer storage device should work three times faster than the device turbodecoding, and the working frequency of the device turbodecoding is low, the target device of the mobile communication buffer storage device that operates at a frequency three times higher than the operating frequency, is an appropriate solution, but when the operating frequency of the device turbodecoding is high, the use of a buffer memory devices operating at a frequency three times higher than the operating frequency, is a very impractical solution for a target mobile communication device. For example, the device turbodecoding system MDCR or to the system USMS, designed to provide high-speed data services, should work with highly the speed for the implementation of all its capabilities. In addition, even when the operating frequency of the buffer storage device is a sharp increase in power consumption of the target mobile communication device. A strong increase of the power consumption is unsuitable for the target mobile communication device, the design of which should ensure low energy consumption.

The invention

Therefore, the present invention is a device and method turbodecoding intended for use in the communication system offering high-speed packet data, for example, in the system, the corresponding BOM 1x evolution - data and speech" (1x EV-DV).

Another objective of the present invention is to provide a device and method to ensure harmonization of the operating frequency of the device turbodecoding with an operating frequency of a buffer memory device, which delivers the information bits in the device turbodecoding available in the target device is mobile, operating with a high transmission rate.

Another object of the present invention is to provide a device and method that reduces the power consumption of the target mobile communication device by eliminating the need to increase the operating frequency of the buffer is upominalsja device, where memorize received data bits for decoding in a mobile terminal device, working with a high transmission rate.

To solve the above and other objectives of the present invention proposed a high-speed buffer storage device operating on the same frequency as the device turbodecoding, and located between the buffer memory of the receiver and the device turbodecoding, and the proposed decoding device performing the read data bits stored in the buffer storage device of the receiver, via a high-speed buffer storage device, the delay read data bits to the time required for the device turbodecoding, and subsequent use of information bits with a delay in the decoding device with flexible input and flexible output (SISO)device turbodecoding. The buffer storage device of the receiver output data bits at the operating frequency (or clock frequency) device turbodecoding. The present invention eliminates the necessity of increasing the operating frequency of the buffer storage device of the receiver even in the case of increasing the data rate that must be Powergen what you're processing device turbodecoding. Thus, the present invention reduces the power consumed by the electronic circuit for mobile equipment.

According to the first variant implementation of the present invention the device turbodecoding in the communication system includes a buffer memory device, and the device SISO decoding. A buffer memory device consists of a unidirectional shift register and one or more bi-directional shift registers. The device SISO decoding consists of blocks of metrics are calculated from the first to the fourth unit of the subtraction.

Unidirectional shift register has an input output used for data input and output, is used to output data. Unidirectional shift register generates bit streams of the first length by sequentially receiving and shifting bits of the input data through input / output, and then provides a serial output generated streams of bits of the first length through the output.

Each of the bidirectional shift register has a first output and a second output, which are used for input/output of data bits and the input data are divided into groups, each of which consists of bits and has a second length, which is equal to 1/2 of the first length. Bidirectional shift register generates bit streams Deut is th length by sequentially receiving and shifting bits of odd groups of the divided groups, coming through the first output, and then provides a serial output generated flow of bits through the first output; and generates bit streams of the second length by sequentially receiving and shifting bits of even-numbered groups of separated groups received via the second output, and then provides a serial output generated flow of bits through the second output.

In the first computing unit metric receives bits from outputs of the respective shift registers, and it calculates the corresponding Delta-metric. The second computing unit metrics do Delta metric from the first computing unit metric corresponding to the unidirectional shift register, and it calculates the alpha metric. The third computing unit metrics do Delta metric from the first computing unit metric corresponding to the bidirectional shift registers, and it calculates the beta metrics. In the fourth computing unit metric enters the alpha metric, and it receives the result of multiplexing the beta metric, and it calculates the values LOP corresponding to the respective shift registers. The subtraction unit subtracts the output signal of the unidirectional shift register of the corresponding values LOP and provides the output of the subtraction to interleave/converted alternations.

In PR doctitle embodiment, a buffer memory device further comprises a logic control device, determines whether the bits of the input data of the divided groups of bits from the odd-numbered groups or bits of even-numbered groups, and feed in the bidirectional shift registers, the selection signals, providing bits of input data to the first output or the second output in accordance with the definition.

In a preferred embodiment, the buffer memory device further comprises a demultiplexer and a multiplexer corresponding to each of the bidirectional shift registers. The demultiplexer has an input output, which receives the bits of the input data and the first output and the second output connected, respectively, with the first output and the second output delivers the bits of the odd groups to the first output via the first output in response to a corresponding select signal received from the logical unit management, and delivers the bits of the even-numbered groups to the second output via a second output. The multiplexer performs the multiplexing of streams of bits output through the first output, and the flow of bits output through the second output in response to a corresponding select signal received from the logical unit management, and provides the output multiplexed streams of bits in the first block of the calculation of the metric.

In a preferred embodiment, the selection signals which are control signals, providing bits of input data in a bidirectional shift registers at different points in time.

In a preferred embodiment, the serial output bits odd groups is performed via the first output and simultaneously engaged in serial receiving and shifting bits of even-numbered groups via a second output.

In a preferred embodiment, the number of bidirectional shift registers is determined by the number of Windows.

In a preferred embodiment, the first length and the second length are determined by the window size and number of Windows.

In a preferred embodiment, the second length is determined by the product of the window size on the number of Windows.

In a preferred embodiment, the reception of bits of the input data is carried out at a clock frequency of the device turbodecoding.

According to the second variant of implementation of the present invention, the device turbodecoding in the communication system includes a buffer memory device, and the device SISO decoding. A buffer memory device comprises a bidirectional shift registers of the first stage and the bidirectional shift register of the second stage. The device SISO decoding consists of blocks of metrics are calculated from the first to the fourth unit of the subtraction.

Each of the bidirectional shift register of the first stage is per the first output and the second output, which are used for input/output of data bits and the input data are divided into groups, each of which consists of bits and has the specified length. Bidirectional shift registers of the first stage to form the threads above length by sequentially receiving and shifting bits of odd groups of separated groups coming through the first output, and then carry out serial output generated flow of bits through the first output; and forming bit streams of the above-mentioned length by sequentially receiving and shifting bits of even-numbered groups of separated groups received via the second output, and then carry out serial output generated flow of bits through the second output.

The bidirectional shift register of the second stage having a third output and a fourth output, which are used for input/output data, and this bidirectional shift register of the second stage generates bit streams of the above-mentioned length by sequentially receiving bits sequentially extracted through the first output through the third output and shift, and then provides a serial output generated flow of bits through the third output; and generates bit streams of the above-mentioned length by sequentially receiving bits sequentially extracted through the second output via the fourth output and SD the yoke, and then provides a serial output generated flow of bits through the fourth output.

In the first computing unit metric receives bits from outputs of the respective shift registers, and it calculates the corresponding Delta-metric. The second computing unit metrics do Delta metric from the first computing unit metric corresponding to the unidirectional shift register, and it calculates the alpha metric. The third computing unit metrics do Delta metric from the first computing unit metric corresponding to the bidirectional shift registers, and it calculates the beta metrics. In the fourth computing unit metric enters the alpha metric, and it receives the result of multiplexing the beta metric, and it calculates the values LOP corresponding to the respective shift registers. The subtraction unit subtracts the output signal of the unidirectional shift register of the corresponding values LOP and provides the output of the subtraction to interleave/converted alternations.

In a preferred embodiment, the buffer memory device further comprises a logical control unit that determines whether the bits of the input data of the divided groups of odd bits or groups of bits from the even-numbered groups, and feed in the bidirectional shift reg is the two first stage of the selection signals, providing bits of input data to the first output or the second output in accordance with the definition.

In a preferred embodiment, the buffer memory device further comprises a demultiplexer and a multiplexer corresponding to each of the bidirectional shift register of the first stage. The demultiplexer has an input output serving for the reception of bits of the input data and the first output and the second output connected, respectively, with the first output and the second output delivers the bits of the odd groups to the first output via the first output in response to a corresponding select signal received from the logical unit management, and delivers the bits of the even-numbered groups to the second output via a second output. The multiplexer performs the multiplexing of streams of bits output through the first output, and the flow of bits output through the second output in response to a corresponding select signal received from the logical unit management, and provides the output multiplexed streams of bits in the first block of the calculation of the metric.

In a preferred embodiment, the buffer memory device further comprises a multiplexer corresponding to the bidirectional shift register of the second stage, and the above-mentioned multiplexer Khujand who performs multiplexing of bits withdrawn through the third output, and bits output via the fourth output in response to a corresponding select signal received from the logical unit management, and provides the multiplexed output bits in the first block of the calculation of the metric.

In a preferred embodiment, the selection signals are control signals, providing bits of input data in a bidirectional shift registers at different points in time.

In a preferred embodiment, the serial output bits odd groups is performed via the first output and simultaneously engaged in serial receiving and shifting bits of even-numbered groups via a second output.

In a preferred embodiment, the number of bidirectional shift registers of the first stage is determined by the number of Windows.

In a preferred embodiment, the first length and the second length are determined by the window size and number of Windows.

In a preferred embodiment, the second length is determined by the product of the window size on the number of Windows.

In a preferred embodiment, the reception of bits of the input data is carried out at a clock frequency of the device turbodecoding.

Brief description of drawings

The above and other objectives, features and advantages of the present invention will become more apparent from the following detailed what about the description when viewed in conjunction with the accompanying drawings, which depict the following:

1 shows a block diagram showing an example of a receiver in the mobile communication system;

figure 2 is a block diagram showing an example of a typical device turbodecoding;

figure 3 shows a block diagram showing an example of a typical device SISO decoding;

on Figa and Figb depicts a block diagram showing an example of order of evaluation metrics through normal device SISO decoding;

on Figa and Figb depicts a block diagram showing an example of a calculation mode of the frame and window mode through normal device SISO decoding;

figure 6 shows a block diagram that shows an example of the processing sequence of the input information bits and output metrics through device SISO decoding of Figure 3;

7 depicts a timing diagram that shows an example of synchronizing the operation of the access to the buffer storage device, executed by the device SISO decoding of Figure 3;

on Fig shows a block diagram that shows an example of the structure of SISO decoding according to one of embodiments of the present invention;

figure 9 shows a block diagram that shows an example of a highly korotogo buffer storage device of Fig according to one of embodiments of the present invention;

figure 10 depicts the sequence of operations, which shows an example of control operations performed by the logical device management from Fig.9, according to one of embodiments of the present invention;

figure 11 depicts a timing diagram that shows an example of synchronizing the operation of the access to the buffer storage device, perform high-speed buffer storage device from Fig.9, according to one of embodiments of the present invention;

on Fig depicts a block diagram showing another example of construction of a high-speed buffer storage device of Fig according to a variant implementation of the present invention;

on Fig shows the precedence diagram showing an example of control operations performed by the logical control device of Fig, according to a variant implementation of the present invention;

on Fig shows a block diagram that shows an example of sequence data through a shift register for the alpha metrics from Fig, according to a variant implementation of the present invention;

on Fig shows a block diagram that shows an example of sequence data, the implementation of the act through a shift register for beta metrics from Fig, according to a variant implementation of the present invention;

on Fig shows a block diagram that shows an example of synchronizing the operation of the access to the buffer storage device, perform high-speed buffer storage device of Fig, according to a variant implementation of the present invention;

on Fig shows a block diagram that shows another example of a high-speed buffer storage device of Fig according to a variant implementation of the present invention;

on Fig shows the precedence diagram showing an example of control operations performed by the logical control device of Fig, according to a variant implementation of the present invention;

on Fig shows a block diagram that shows an example of sequence data through a shift register for the alpha metrics from Fig, according to a variant implementation of the present invention; and

in Fig. 20 shows a block diagram that shows an example of synchronizing the operation of the access to the buffer storage device, perform high-speed buffer storage device of Fig, according to a variant implementation of the present invention.

A detailed description of the preferred options implemented the program inventions

Below is a detailed description of several embodiments of the present invention with reference to the accompanying drawings. The same or similar elements in the drawings are marked with the same number of positions. A detailed description of known functions and structures incorporated in the composition of the present invention, is not shown here for brevity.

On the block diagram of Fig shows an example of a device SISO decoding according to one of embodiments of the present invention. The drawing shows only the device SISO decoding, comprising the device turbodecoding shown in figure 2, and a buffer memory device that is connected to the previous stage device SISO decoding.

With reference to Fig, the decoding device according to a variant implementation of the present invention contains the device SISO decoding, which includes block 210 calculate the Delta-metric unit 220 calculate the alpha metric block 230 calculate beta metric unit 240 calculate LOP and the subtraction unit 250. The decoding device characterized in that it further comprises a high-speed buffer storage device 260 that is positioned between the device SISO decoding and buffer storage device 46-10, in which the memorization of making the s symbols (or data bits), shown in Figure 3. In addition, the buffer storage device 46-10 included in the decoding device, characterized in that operates at a clock frequency of the device turbodecoding, and not at the frequency of the buffer storage device 46-1 available in conventional decoding device (see Fig.7 and 11), which is three times the clock rate of the device turbodecoding. That is, the proposed decoding device characterized in that it further comprises a high-speed buffer storage device 260 which is located after the buffer storage device 46-10, to provide access to the accepted information bits stored in different locations of the buffer memory device 46-10, for 1 clock pulse device turbodecoding, and supplying information bits, which was accessed in the corresponding computing devices 211-213 block 210 calculate the Delta metric, due to which the calculation of the Delta-metric by block 210 calculate the Delta metrics perform for 1 clock pulse device turbodecoding.

In the proposed device decoding, even when it is used in the communication system offering high-speed packet data, for example in the system, the corresponding specification is of "1x evolution - data and speech" (1x EV-DV), is not required to increase the operating frequency of the buffer storage device. Therefore, the decoding device suitable for providing reducing power consumption of the target mobile communication device. As a reference, as in the conventional decoding device of Figure 3 the transmission of the received information bits carried out directly in the device turbodecoding through the demultiplexer 205, connected to the buffer storage device 46-1 receiver, the operation of reading data from the buffer storage device 46-1 from the receiver performs three times, as shown in Fig.6. However, the proposed invention is a decoding device differs in that instead of the demultiplexer includes an additional buffer storage device 260, which is located in the input stage decoding device that allows you to ensure the normal operation of the device SISO decoding a read operation in one clock pulse. That is, in the proposed device decoding when calculating the three Delta metrics required only one read operation from the storage device, and this operation is performed with a frequency equal to the working frequency of the device turbodecoding. Such operation is possible because the high the high-speed buffer storage device 260 in advance provides memorizing therein the received signal, and then carries out the rearrangement of the received signal so that it matches the required input for devices 211 - 213 calculate the Delta metric.

Because the design of the device SISO decoding has been described above, its detailed description will be omitted, and the following description of the invention focuses on the design and operation of high-speed buffer storage device 260 with respect to the present invention.

High-speed buffer storage device 260 of the proposed device, decoding can be performed as shown in Fig.9, Fig and Fig. Figure 9 shows an implementation option, in which high-speed buffer storage device 260 consists of a single unidirectional shift register 310 and from a variety of bidirectional shift registers 321, 322 and 323, the number of which is equal to the number N of Windows. On Fig shows an implementation option, in which high-speed buffer storage device 260 consists of a single unidirectional shift register 410 and many bidirectional shift registers 421 and 422, the number of which coincides with the number of Windows equal to 2. The construction shown in figures 9 and Fig are, in principle, identical, but differ in what kolichestvo Windows. On Fig shows an implementation option, in which high-speed buffer storage device 260 consists of a single bi-directional shift register 510 and many bidirectional shift registers 521 and 522, the number of which coincides with the number of Windows equal to 2. The design shown in Fig, is fundamentally different from the structures shown in figures 9 and Fig. In the construction shown in figures 9 and Fig, submitting information bits from the buffer storage device 46-10 in unidirectional shift register and a bidirectional shift registers operate at the same time. In contrast, in the construction shown in Fig, data bits from the buffer storage device 46-10 served in the bidirectional shift registers 521 and 522, and the bidirectional shift register 510, a corresponding unidirectional shift registers 310 and 410 of the first and second embodiments, serves the information bits from the outputs of the bidirectional shift registers 521 and 522.

Below in more detail revealed first, second and third embodiments of the invention depicted, respectively, in Figure 9, Fig and Fig.

The first variant embodiment of the invention

On the block diagram of Figure 9 shows an example design of a high-speed buffer storage device 260, and obnajennogo on Fig, according to the first variant implementation of the present invention. With reference to Figure 9, a high-speed buffer storage device 260 consists of a single unidirectional shift register 310, N bidirectional shift registers 321-323, logical unit 330 controls, demultiplexes (SLE) 341-343 and multiplexers (MPX) 351-353.

Unidirectional shift register 310 has 2NW memory (length) and contains input output used for data input and output, is used to output data. Here N is the number of Windows, and W is the window size. The size W of the window can be changed. However, even when changing the window size W ratio (for example, 2W and 4W) shift registers do not change. For W=24 unidirectional shift register 310 for α has a size equal to 96, and shift registers 321-323 for β1and β2have a size equal to 48. When changing W appropriately changing the length of the shift registers, and changes the processing sequence. However, even if you change W the structure of the shift registers do not change. Unidirectional shift register 310 performs consecutive reception of bits of the input data from the buffer storage device 46-10 through the input output in accordance with a given clock frequency of the device turbodecoding and shifting the received bits I is-breaking data on the left (side A) right (B-side). After the formed bit streams the data to the first length (2NW), unidirectional shift register 310 provides a serial output generated streams of data bits of the first length through the output. Data bits derived from the unidirectional shift register 310, served in the device 211 calculate the Delta metric, connected to the input stage block 220 calculate alpha metrics.

Each of the bidirectional shift registers 321-323 NW has memory and contains the first output and the second output to input/output data. The first conclusion is a conclusion that is located on the left side of each of the bidirectional shift registers 321-323, and the second conclusion is a conclusion that is located on the right side of each of the bidirectional shift registers 321-323. The first output and the second output may be provided as output data and input data. The number of bidirectional shift registers 321-323 is determined by the number of Windows. If the number of Windows is equal to N, the number of bidirectional shift registers 321-323 set equal to N, and if the number of Windows is equal to two, the number of bidirectional shift registers 321-323 set equal to 2. Bits of incoming data from the buffer storage device 46-10, divided into groups, each of which consists of bits and who meet the second length (NW), which is equal to 1/2 of the first length. Each of the bidirectional shift registers 321-323 takes consecutive reception of bits of odd groups of separated groups received via the first output, and performs a shift to the left (side A) right (B-side), and if the generated bit streams of the second length, each of the bidirectional shift registers 321-323 provides a serial output generated flow of bits through the first output in the order from left to right, which is the reverse order in which they appear in the input. Each of the bidirectional shift registers 321-323 takes consecutive reception of bits of even-numbered groups of separated groups received via the second output, and a shift from right to left, and if the generated bit streams of the second length, each of the bidirectional shift registers 321-323 provides a serial output generated flow of bits through the second output in order from left to right, which is the reverse order in which they appear in the input.

Between the output pin of the buffer storage device 46-10 and shift registers 321-323 are demultiplexes 341-343, and between the shift registers 321-323 and block 210 calculate the Delta metrics are multiplexers 351-353. The input terminals of the demultiplexes 341-343 uedineny with the output pin of the buffer storage device 46-10, the first output terminals of the demultiplexes 341-343 connected with the second pins shift registers 321-323, and the second output terminals of the demultiplexes 341-343 connected with the first conclusions of the shift registers 321-323. The first input terminals of the multiplexers 351-353 connected with the second pins shift registers 321-323, the second input terminals of the multiplexers 351-353 connected with the first conclusions of the shift registers 321-323, and the output terminals of the multiplexers 351-353 connected with devices 211-213 calculate the Delta metric.

Logical device 330 management creates the selection signals "Vybor" (select1) - "N" (selectN) to control the operation of the shift registers 321-323 of demultiplexes 341-343 and multiplexers 351-353. The selection signals can be characterized as the signals used to control bits of incoming data from the buffer storage device 46-10, therefore, to provide a supply of bits of the input data in the shift registers 321-323 at different points in time. Logical device 330, control determines whether the bits of the input data received from the buffer storage device 46-10, odd bits or groups of bits from the even-numbered groups of the divided groups, and provides a supply of bits of input data from the buffer storage device 46-10 on the first findings or conclusions on the second change is new registers 321-323 in accordance with the definition.

For example, in the case when the bits of the input data bits are odd groups, logical device 330 performs control output selection signals with a level equal to "0"or from "low logic level, and in the case when the bits of the input data bits are even groups, logical device 330 performs control output selection signals with a level equal to "1"or from "high logic level". In the case of output selection signals with a level equal to "0", demultiplexes 341-343 serves bits of the input data from the buffer storage device 46-10 on the first conclusions shift registers 321-323. Then shift registers 321-323 carry out serial shift data bits received through their first conclusions, from left to right (towards the right). Simultaneously with this shift registers 321-323 again carry out serial shift NW information bits obtained earlier through their second conclusions, and then remembered, from left to right, and discharge subject to shift data bits through their second conclusions.

In the case of output selection signals with a level equal to "1", demultiplexes 341-343 serves bits of the input data from the buffer storage device 46-10 conclusions on the second shift registers 321-323. Then shift registers 321-323 carry out serial shift informationinfo, obtained through their second conclusions, from right to left (towards the left). Simultaneously with this shift registers 321-323 again carry out serial shift NW information bits obtained earlier through their first conclusions, and then memorized, right to left, and discharge subject to shift data bits through their first conclusions.

Data bits outputted through the first conclusions shift registers 321-323, served on the second input terminals of the multiplexers 351-353, and data bits outputted through the second set of conclusions shift registers 321-323, served on the first input terminals of the multiplexers 351-353. Multiplexers 351-353 perform multiplexing of the information bits, is fed through the first input pins and the second input pins, and perform output multiplexed data bits in corresponding devices 211-213 calculate the Delta metric.

As described above, the proposed decoding device delivers the data bits stored in different locations of the buffer memory device 46-10, in the device SISO decoding using a high-speed buffer storage device 260, the structure of which is shown in Fig.9. That is, high-speed buffer storage device 260 through shift registers 310 and 321-323 change is adok sequence of information bits, the reception which was previously carried out sequentially so that he could comply with this order they appear, which is required for the device SISO decoding with the scheme operating in the mode of the moving window.

Referring to Fig.9, the M bits from the buffer storage device 46-10 served in the shift registers 310 and 321-323 with 2NW or NW areas of memory. Here the symbol N indicates the number of Windows, the symbol W is indicated the size of the Windows, and the symbol M is indicated the number of information bits received from the buffer storage device 46-10 for one clock pulse device turbodecoding. In that case, when the buffer storage device 46-10 is a buffer storage device for CDTC, M is the sum of the length of a systematic code in bits and length codes the parity bits. That is, the M-bit signal is a signal generated by summing M/3 bits of a systematic code, M/3 bits of the first code parity and M/3 bits in the second code parity. For the input M-bit signal shift registers 310 and 321-323, demultiplexes 341-343 and multiplexers 351-353 all made M-bit. M-bit output signal, that is, the values derived from the shift registers 310 and 321-323, served in devices 211-213 calculate the Delta metric. Devices 211-213 compute the deltas of the metrics get three M/3-bit signal, the sum of which is equal to M bits.

Figure 10 shows the control operations performed by the logical unit 330 controls depicted in Fig.9. In particular, the drawing shows the sequence of operations management, in which the logical device 330 management manages the shift registers 321-323 for β-metrics, demuxers 341-343 connected to the inputs and outputs of the shift registers 321-323, and multiplexers 351-353.

Figure 10 operation 1011-1017 represent a sequence of operations of the control shift register 321, a demultiplexer 341 and the multiplexer 351. Operations 1021-1027 represent a sequence of operations of the control shift register 322, a demultiplexer 342 and the multiplexer 352. Operations 1031-1037 represent a sequence of operations of the control shift register 323, the demultiplexer multiplexer 343 and 353. Since the corresponding sequence is identical to perform operations, except for the initial moments of time and names of signals used, for simplicity, the following describes only the sequence of operations 1011-1017. To ensure compliance with these operations, the control logic unit 330 contains a control counters corresponding shift registers 321-323. DL the operation of counting the initialization of the counters is carried out in different moments of time at a given offset, equal to W. the initialization of the counter No. 1, the corresponding shift register 321, exercise at time T=0, the initialization of the counter No. 2, the corresponding shift register 322, exercise at time T=Wt, and the initialization of counter # N corresponding to the shift register 323, exercise at time T=(N-1)Wt. Here the symbol t designated time, i.e. the duration of a single clock pulse.

With reference to Figure 10, when the operation 1011 logical control unit 330 performs the initialization of the shift register 321. When performing the initialization, the initial value of the countdown counter No. 1 is set to otschel=0, and the initial state of the select signal "Vybor" is set to wybor=0. In addition, the left (side A) output shift register 321 is defined as the input to the output, and the right (B side) output shift register 321 is defined as output. At operation 1012 logical unit 330 reads data bits by accessing the buffer storage device 46-10 from Fig. When the operation 1013 logical unit 330, the control checks whether the value of the reference otschel" equal to the NW, to determine whether the shift register 321 is completely filled. If the reading "otschel equal to NW, then the carried out operation 1014 logical device 330 control sets the value of the reference otschel" is equal to 0. If the value of the reference otschel not equal to NW, then at operation 1015 logical device 330 management increases the value of the reference otschel 1. After the operation 1014 logical unit 330 controls when performing the operation 1016 inverts the signal Vybor". That is, the logical device 330 control converts the signal "Vybor"equal to "1", the signal "Vybor", "0"and the signal "Vybor", "0", the signal "Vybor"equal to "1"by inversion signal Vybor". Through operation 1016 change the direction of the I / o and the shift direction information bits. After the operation 1016 or after surgery 1015 perform an operation 1017, in which a logical device 330 control writes data bits received from the buffer storage device, 46-10, in the shift register 321. After the operation 1017 logical device 330, control returns to operation 1012, enabling repeated execution of the above operations.

Figure 11 depicts a timing diagram that shows an example of synchronizing the operation of the access to the buffer storage device, perform high-speed buffer storage device 260 from Fig.9, according to a variant implementation of the present invention. With reference to 11, a high-speed buffer storage ustroystvo accesses information bits, stored in different locations of the buffer memory device 46-10. In this example, the high-speed buffer storage device 260 provides access to information bits Data1 has, dannie and dannie stored in the three addresses of the buffer memory device 46-10. While input from all three data bits Data1 has, dannie and dannie in high-speed buffer storage device 260 for one clock pulse device turbodecoding computing devices 211-213 block 210 calculate the Delta metrics simultaneously perform the operation of calculating the Delta metric. Data bits Data1 has (M-bit) refers to the systematic code (M/3 bits) + code No. 1 parity (M/3 bits) + code No. 2 parity (M/3 bits), and data dannie and dannie also equal to the volume of data Data1 has.

The second option of carrying out the invention

On the block diagram of Fig shows another example of construction of a high-speed buffer storage device 260 shown in Fig, according to the second variant of implementation of the present invention. The drawing shows the design of high-speed buffer storage device 260 for the option, when the number of Windows N=2, i.e. when the beta has two Windows.

With reference to Fig, high-speed buffer storage device 260 comprises one what about the unidirectional shift register 410, N=2 bidirectional shift registers 421 and 422, logical unit 430 controls, demultiplexes (SLE) 441 and 442, and multiplexers (MPX) 451 and 452.

Shift register 410 has 2NW=4W memory (length) and contains input output used for data input and output, is used to output data. Shift register 410 performs consecutive reception of bits of the input data from the buffer storage device 46-10 through the input output in accordance with a clock frequency of the device turbodecoding and shifting the received bits of the input data on the left (side A) right (B-side). After the formed bit streams the data to the first length (4W), the shift register 410 provides a serial output generated streams of data bits of the first length through the output. Data bits outputted from the shift register 410, served in the device 211 calculate the Delta metric, connected to the input stage block 220 calculate alpha metrics.

Each of the shift registers 421 and 422 is NW=2W memory and contains the first output and the second terminal is used for input/output data. The first conclusion is a conclusion that is located on the left side of each of the shift registers 421 and 422, and the second conclusion is a conclusion that is located on the right side of each of the shift registers 421 and 42. The first output and the second output may be provided as output data and input data. The number of shift registers 421 and 422 is determined by the number of Windows. If the number of Windows N=2, the number of shift registers 421 and 422 set equal to 2. Bits of incoming data from the buffer storage device 46-10, divided into groups, each of which consists of bits and has a second length (2W), which is equal to 1/2 of the first length. Each of the shift registers 421 and 422 performs consecutive reception of bits of odd groups of separated groups received via the first output, and a shift to the left (side A) right (B-side), and if the generated bit streams of the second length, each of the shift registers 421 and 422 provides a serial output generated flow of bits through the first output in the order from right to left, which is the reverse order in which they appear in the input. Each of the shift registers 421 and 422 performs consecutive reception of bits of even-numbered groups of separated groups received via the second output, and a shift from right to left, and if the generated bit streams of the second length, each of the shift registers 421 and 422 provides a serial output generated flow of bits through the second output in order from left to right, which is about the military order of their sequence in the input.

Between the output pin of the buffer storage device 46-10 and the shift registers 421 and 422 are demultiplexes 441 and 442. Between the shift registers 421 and 422 and block 210 calculate the Delta metrics are multiplexers 451 and 452. The input terminals of the demultiplexes 441 and 442 are connected to the output pin of the buffer storage device 46-10, the first output terminals of the demultiplexes 441 and 442 are connected with the second findings of the shift registers 421 and 422, and the second output terminals of the demultiplexes 441 and 442 are connected with the first conclusions of the shift registers 421 and 422. The first input terminals of the multiplexers 451 and 452 are connected with the second findings of the shift registers 421 and 422, the second input terminals of the multiplexers 451 and 452 are connected with the first conclusions of the shift registers 421 and 422, and the output terminals of the multiplexers 451 and 452 are connected with devices 211-213 calculate the Delta metric.

Logical device 430 management creates the selection signals "Vybor" (select1) and "Vybor" (select2) to control the operation of the shift registers 421 and 422, demultiplexes 441 and 442, and multiplexers 451 and 452. The selection signals can be characterized as the signals used to control bits of incoming data from the buffer storage device 46-10, therefore, to provide a supply of bits of the input data shifts the s registers 421 and 422 at different points in time. Logical device 430 control determines whether the bits of the input data received from the buffer storage device 46-10, odd bits or groups of bits from the even-numbered groups of the divided groups, and delivers the bits of the input data from the buffer storage device 46-10 on the first findings or conclusions on the second shift registers 421 and 422 in accordance with the definition.

For example, in the case when the bits of the input data bits are odd groups, logical unit 430 performs control output selection signals with a level equal to "0"or from "low logic level, and in the case when the bits of the input data bits are even groups, logical unit 430 performs control output selection signals with a level equal to "1"or from "high logic level". In the case of output selection signals with a level equal to "0", demultiplexes 441 and 442 serves bits of the input data from the buffer storage device 46-10 on the first findings of the shift registers 421 and 422. Then shift registers 421 and 422 carry out serial shift data bits received through their first conclusions, from left to right (towards the right). Simultaneously, the shift registers 421 and 422 again carry out serial shift 2W information bits obtained earlier through their second conclusions, and ZAT is m memorized, from left to right, and discharge subject to shift data bits through their second conclusions.

In the case of output selection signals with a level equal to "1", demultiplexes 441 and 442 serves bits of the input data from the buffer storage device 46-10 conclusions on the second shift registers 421 and 422. Then shift registers 421 and 422 carry out serial shift data bits received through their second conclusions, from right to left (towards the left). Simultaneously, the shift registers 421 and 422 again carry out serial shift 2W information bits obtained earlier through their first conclusions, and then memorized, right to left, and discharge subject to shift data bits through their first conclusions.

Data bits outputted through the first conclusions of the shift registers 421 and 422 is fed to the second input terminals of the multiplexers 451 and 452, and the information bits are outputted through the second findings of the shift registers 421 and 422 is fed to the first input terminals of the multiplexers 451 and 452. Multiplexers 451 and 452 provide multiplexing of the data bits, is fed through the first input pins and the second input pins, and perform output multiplexed data bits in corresponding devices 211-213 calculate the Delta metric.

With reference to Fig,computing devices 211-213 first block 210 calculate metrics admit bits received from the output shift registers 410, 421 and 422, and calculate the corresponding Delta-metric. The second block 220 compute the metric computes the alpha metric, receiving the Delta metric of the computing device 211 of the first block 210 compute the metric corresponding to the shift register 410. The third block 230 compute the metric computes the beta metric, receiving the Delta metric of the computing devices 212 and 213 of the first block 210 compute the metric corresponding to the shift registers 421 and 422. Computing device 241 to 243 of the fourth block 240 compute the metric calculates the LOP, the corresponding shift registers 410, 421 and 422, getting the alpha metric and the result of multiplexing the beta metrics obtained through multiplexer 233. Subtractive device 251-253 block 250 subtraction subtract the output signal of the shift register 410 of the corresponding values LOP and implement the results of the subtraction to interleave and turned alternations.

In the diagram the sequence of operations of Fig shows an example of control operations performed by the logical device 430 management of Pig, according to a variant implementation of the present invention. In particular, the drawing shows the sequence of operations management, in which the logical device 430 management manages DV is directional shift registers 421 and 422 for β -metrics, demuxers 441 and 442 connected to the inputs and outputs of the shift registers 421 and 422, and multiplexers 451 and 452.

On Fig operations 1111-1117 represent a sequence of operations of the control shift register 421, the demultiplexer 441 and the multiplexer 451. Operations 1121-1127 represent a sequence of operations of the control shift register 422, a demultiplexer multiplexer 442 and 452. Since the corresponding sequence is identical to perform operations, except for the initial moments of time and names of signals used, for simplicity, the following describes only the sequence of operations 1111-1117. To ensure compliance with these operations, the control logic device 430 control contains the counters corresponding to the shift registers 421 and 422. To perform the operation of calculating the initialization of the counters is carried out in different moments of time at a given offset equal to W. the initialization of the counter No. 1, the corresponding shift register 421, exercise at time T=0, and initialize the counter No. 2, the corresponding shift register 422, exercise at time T=Wt. Here the symbol t designated time, i.e. the duration of a single clock pulse.

With reference to Fig, when in the execution of the operation 1111 logical device 430 management carries out the initialization of the shift register 421. When performing the initialization, the initial value of the countdown counter No. 1 is set to otschel=0, and the initial state of the select signal "Vybor" is set to wybor=0. In addition, the left (side A) output shift register 421 is defined as the input to the output, and the right (B side) output shift register 421 is defined as output. At operation 1112 logical unit 430 reads the information bits by accessing the buffer storage device 46-10 from Fig. When the operation 1113 logic device 430 control checks whether the value of the reference otschel" equal to 2W, to determine whether the shift register 421 is completely filled. If the reading "otschel equal to 2W, then at operation 1114 logic device 430 control sets the value of the reference otschel" is equal to 0. If the value of the reference otschel not equal to 2W, then at operation 1115 logic device 430 management increases the value of the reference otschel 1. After the operation 1114 logical unit 430 controls when performing the operation 1116 inverts the signal Vybor". That is, the logical device 430 control converts the signal "Vybor"equal to "1", the signal "Vybor", "0"and the signal "Vybor", "0", the signal "Vybor"equal to "1", PU is eat inversion signal Vybor". Through the operation 1116 change direction input/output and shift direction information bits. After the operation 1116 or after surgery 1115 perform an operation 1117, in which a logical device 430 control writes data bits received from the buffer storage device, 46-10, in the shift register 421. After the operation 1117 logic device 430 control is returned to operation 1112, enabling repeated execution of the above operations.

On the block diagram of Fig shows an example of the processing sequence of the data shift register 410 for the alpha metric shows on Fig. With reference to Fig, the shift register 410 performs serial receive data bits from the buffer storage device 46-10 shown in Fig, and their shift from left to right. In the drawing "side a" indicates the position of the input information bits, and "party B" represents the location of the output data bits. When submitting information bits at the input of shift register 410, the output bits of the input data is performed with the delay on 4W. Shift register 410 simply has the structure of a FIFO type (first in first out).

On Fig shows the processing sequence of the data shift register 421 for beta metric shows on Fig. This sequence of clicks is ODI data is identical to the sequence data of the other shift register 422 for beta metrics.

With reference to Fig, the shift register 421 introduces a delay data read sequentially from the buffer storage device 46-10, for a specified time to time of the output data coincides with the time desired for the device turbodecoding. The shift register 421 systematically memorizing bits of the input data. If the shift register 421 is full, the shift register 421 performs the conclusion of the previous data bits while moving the stored data bits in the opposite direction to the input, and delivers the bits of the output data to the device 212 calculate the Delta metric. As a result, on the opposite side of the shift register 421 is a blank space. As you enter new information bits happening again fill this empty space in the direction opposite to the direction input, in which was made the previous input data bits. In this way provide repeated operations of the data input into the shift register 421 and the output from it, and this resulted in the submission of information bits in the appropriate device 212 calculate the Delta metric is carried out in accordance with the data flow shown in the drawing.

On the block diagram of Fig shows an example synchronize the access operation to the buffer storage device, perform high-speed buffer storage device 260 of Fig, according to a variant implementation of the present invention. On Fig the symbol "enter the Delta block for alpha" denotes the procedure of input/output data bits to the unidirectional shift register 410 of Fig, where "A" denotes input data bits, and "party B" denotes output data bits. In addition, the symbol "enter the Delta block for beta" denotes the procedure of input/output information bits bi-directional shift register 421, and the symbol "enter the Delta block for beta2" denotes the procedure of input/output information bits bi-directional shift register 422. In the legend "enter the Delta block for beta" and "enter the Delta block for beta2" names "A side entrance and side exit marked those information bits, the I / o is performed via the first output, and the names of the "B-side entrance" and "side B output" denotes those data bits, input/output is performed through the second conclusion. Names "Vybor" and "Vybor" denotes the control signals, the generation which was implemented by the logical unit 430 controls, and which were then filed in the shift registers 421 and 422. The names of the output alpha", "pickup is beta and output beta2 indicated inferred result metrics while calculating the value of the LOP is performed with the use of these derived metrics.

"Enter the Delta block for beta" input information bits at the initial stage, through the side of A. the Input information bits produced in the following order: a, b, c, d,..., h, and the output data bits from And exercise after a period of time equal to 2W, elapsed from the initial moment of time. During the operation of the output from A perform an operation input from B. This means that the shift register 421 operates in such a way that changes the running direction of shift. After the next period of time equal to 2W when And again perform an operation input through the input q-what information bits from B to produce the output p-informational bits.

The functioning part "enter the Delta block for beta2" carried out in the same manner as the operation of the input Delta-block for beta". However, since the initialization shift register 422 differs from the time of initialization of the shift register 421, the input/output data bits is performed in different periods of time.

"Enter the Delta block for alpha side And perform only the operation input, and side B only perform the output operation. The output of the first floor is a Chennai-information bits carried out after a period of time, equal 4W elapsed from the starting time.

Comparing the bits output from the output shift registers 410, 421 and 422, the bits of the output, shown in Fig.6, it can be understood that the output data bits is performed in the same sequence. However, there is a difference, namely, that the output of Fig creates an initial delay equal to 2W, compared with the output of 6. However, this difference occurs only at the initial moment of a high-speed buffer storage device 260. That is because the difference occurs only in the initial phase at the start of the decoding operation performed by the device turbodecoding, it does not affect the performance of the decoding.

The third variant embodiment of the invention

On the block diagram of Fig shows another example of a high-speed buffer storage device 260 of Fig according to the third variant of implementation of the present invention. With reference to Fig, high-speed buffer storage device 260 comprises a bidirectional shift registers 521 and 522 of the first stage of the bidirectional shift register 510 second stage logical unit 530 control, demultiplexes 541 and 542, and multiplexers 551-553.

Each of the bidirectional sdvigov the registers 521 and 522 of the first stage has the NW areas of memory and includes a first output and a second output for input/output data. Here the symbol N indicates the number of Windows, and the symbol W is indicated the size of the Windows. The number of shift registers is determined by the number of Windows and the number of memory areas is determined by the product of the number of Windows on the Windows size. The first conclusion is a conclusion that is located on the left side of each of the shift registers 521 and 522, that is, the output side a, And the second conclusion is a conclusion that is located on the right side of each of the shift registers 521 and 522, that is, the output side B. the First output and the second output may be provided as output data and input data. Bits of incoming data from the buffer storage device 46-10, divided into groups, each of which consists of bits and has a length NW. Each of the shift registers 521 and 522 performs consecutive reception of bits of odd groups of separated groups received via the first output, and performs a shift to the left (side a) right (B-side), and if the generated bit streams of a given length, each of the shift registers 521 and 522 provides a serial output generated flow of bits through the first output in the order from right to left, which is the reverse order in which they appear in the input. Each of the shift registers 521 and 522 performs consecutive reception of bits odd what's groups of the divided groups, received via the second output, and a shift to the right (B-side) left (side a), and if the generated bit streams of a given length, each of the shift registers 521 and 522 provides a serial output generated flow of bits through the first output in the order from left to right, which is the reverse order in which they appear in the input.

Bidirectional shift register 510 of the second stage is NW of memory and includes a third output and a fourth output, used for input/output data. The shift register 510 receives bits sequentially extracted through the first output shift register 521, through its third output, and produces a serial shift of the received bits from left to right. In that case, if the generated bit streams of a given length, the shift register 510 produces a shift of the generated streams of bits from right to left in the order reverse to the order in which they appear in the input, and provides a serial output subjected to shear flow of bits through the third conclusion. The shift register 510 receives bits sequentially extracted through the second output shift register 521, through his fourth output, and produces a serial shift of the received bits from right to left. In that case, if the generated bit streams of a given length, the shear reg is page 510 produces a shift of the generated bits from left to right in the order the reverse order in which they appear in the input, and provides a serial output subjected to shear flow of bits through the fourth output.

Between the output pin of the buffer storage device 46-10 and shift registers 521 and 522 are demultiplexes 541 and 542, and between the shift registers 510, 521 and 522 and the block 210 calculate the Delta metrics are multiplexers 551-553. The input terminals of the demultiplexes 541 and 542 are connected to the output pin of the buffer storage device 46-10, the first output terminals of the demultiplexes 541 and 542 are connected with the second findings of the shift registers 521 and 522, and the second output terminals of the demultiplexes 541 and 542 are connected with the first conclusions of the shift registers 521 and 522. The first input terminals of the multiplexers 551-553 connected with the second findings of the shift registers 510, 521 and 522, the second input terminals of the multiplexers 551-553 connected with the first conclusions of the shift registers 510, 521 and 522, and the output terminals of the multiplexers 551-553 connected with devices 211-213 calculate the Delta metric.

Logical device 530 control creates the selection signals "Vybor", "Vybor" and "Vybor to control the operation of the shift registers 510, 521 and 522, demultiplexes 541 and 542, and multiplexers 551-553. The selection signals can be characterized as the signals used to control bits of the output data, coming from the buffer storage device 46-10, therefore, to provide a supply of bits of the input data in the shift registers 521 and 522 at different points in time. Logical device 530 control determines whether the bits of the input data received from the buffer storage device 46-10, odd bits or groups of bits from the even-numbered groups of the divided groups, and submit to the shift registers 521 and 522 of the selection signals "Vybor" and "Vybor"providing bits of the input data on the first findings or conclusions on the second in accordance with the definition.

For example, in the case when the bits of the input data bits are odd groups, logical unit 530 performs control output selection signals with a level equal to "0"or from "low logic level, and in the case when the bits of the input data bits are even groups, logical device 330 performs control output selection signals with a level equal to "1"or from "high logic level". In the case of output selection signals with a level equal to "0", demultiplexes 541 and 542 serves bits of the input data from the buffer storage device 46-10 on the first findings of the shift registers 521 and 522. Then shift registers 521 and 522 carry out serial shift data bits received through their first conclusions on the left nab the AVO (towards the right). Simultaneously, the shift registers 521 and 522 again carry out serial shift 2W information bits obtained earlier through their second conclusions, and then remembered, from left to right, and discharge subject to shift data bits through their second conclusions.

In the case of output selection signals with a level equal to "1", demultiplexes 541 and 542 serves bits of the input data from the buffer storage device 46-10 conclusions on the second shift registers 521 and 522. Then shift registers 521 and 522 carry out serial shift data bits received through their second conclusions, from right to left (towards the left). Simultaneously, the shift registers 521 and 522 again carry out serial shift 2W information bits obtained earlier through their first conclusions, and then memorized, right to left, and discharge subject to shift data bits through their first conclusions.

Data bits outputted through the first conclusions of the shift registers 521 and 522 is fed to the second input terminals of the multiplexers 552 and 553, and the information bits are outputted through the second findings of the shift registers 521 and 522 is fed to the first input terminals of the multiplexers 552 and 553. Multiplexers 552 and 553 perform multiplexing of the information bits, is fed through the first inlet vivodi second input pins, and provide the output multiplexed data bits in corresponding devices 211-213 calculate the Delta metric.

Data bits outputted through the first output shift register 521, also served on the first output shift register 510 and the data bits outputted through the second output shift register 521, also served on the second output of the shift register 510. Operations shift register 510, equivalent to the operations shift registers 521 and 522. Data bits outputted through the first output shift register 510 is fed to the second input of the output multiplexer 551, and the information bits are outputted through the second output shift register 510 is fed to the first input of the output multiplexer 551. Data bits from the output of the multiplexer 551 served in the device 211 calculate the Delta metric, connected to the input stage of the device 220 calculate alpha metrics.

This alternative implementation of the present invention differs in construction from high-speed buffer storage device 260 shown in Fig, but identical to his functioning. According to this variant implementation of the present invention, the shift register 510 for α-metrics is a bidirectional shift register having a length 2W, in contrast to the variants of the invention, shown in figures 9 and Fig, and instead to receive the information bits received from the buffer storage device 46-10, the shift register 510 receives information bits received from the shift register 521 for β1-metric, and then provides output information bits through the multiplexer 551. That is, the shift register 510 having the same structure again receives the outputs of the shift register 521 for β1-metrics. In this embodiment of the invention in the case, if the shift register 521 for β1metrics designed in such a way that creates a reverse order compared to the actually received signal, then carry out his recombine in reverse order to ensure recovery of the signal in the order corresponding to the original input signal, and then serves the recovered signal in the shift register 510 for α-metrics. If a high-speed buffer storage device is structurally designed so that the shift register 510 for α-metric and the shift register 521 for β1metrics are always working in the opposite direction, the amount of shift registers in the buffer memory can be reduced to 2W compared to the high-speed buffer for minumim device, shown in Fig.

On Fig shows the precedence diagram showing an example of control operations performed by the logical device 530 management of Pig, according to a variant implementation of the present invention. Shown in the drawing, the sequence of control operations similar sequence of operations depicted in Fig. However, the only difference is that the added sequence control shift register 510 for α-metrics. In the scheme of the sequence of operations management operations 1211, 1221 and 1231 indicate that initialization routines are different.

With reference to Fig, the initialization of the shift register 510 for α-metric exercise at time T=(2W-1)t, the initialization of the shift register 521 for β1-metric exercise at time T=0, and the initialization of the shift register 522 to β2-metric exercise at time T=(W-1)t. That is, the initialization of the shift register 510 is carried out after the clock pulse (2W-1), the initialization of the shift register 521 carried out during the 0-th clock pulse, and the initialization of the shift register 522 is carried out after the clock pulse (W-1). Assuming that the total period for the shift registers is equal to 4W, it should be noted that these dasdview register work in opposite directions with periods equal to 2W. Except for the initialization routines, the operation of Fig identical to the operations of Fig, so for simplicity, a detailed description is not provided here.

On the block diagram of Fig shows an example sequence of data processing carried out shift register 510 of Fig, according to a variant implementation of the present invention. With reference to Fig, data processing operations shift register 510 performs the same way as the operation data shift registers for β-metrics described for Fig.

On the block diagram of Fig shows an example of synchronizing the operation of the access to the buffer storage device, perform high-speed buffer storage device 260 of Fig, according to a variant implementation of the present invention. With reference to Fig, the access operation of the buffer storage device, perform high-speed buffer storage device 260 differs from the operations of the shift register 510, but in the end provides the obtaining of the same metrics α, β1and β2.

As described above, the present invention provides transmission of data bits from the buffer storage device of the receiver device turbodecoding through the use of high-speed what about the buffer storage device, having the same operating frequency as the device turbodecoding. In addition, the present invention enables realization of a device suitable for use in the equipment for mobile communication, requiring lower power consumption by eliminating the need to increase the operating frequency of the buffer storage device of the receiver.

Although the invention has been shown and described with reference to certain variations in its implementation, specialists in the art will understand that can be made various changes in form and detail, without going beyond the nature and scope of the invention, which are defined in the attached claims and their equivalents.

1. A buffer memory device, receipt of a frame, consisting of the serial input symbols, and the filing of the above-mentioned input symbols in the decoding device with flexible input and flexible output (SISO device-decoding), working in N-windowed mode, in which the window size is W characters long, and contains a first shift register having input output output output input output clock pulses carrying out serial shift and memorizing 2NW of consecutive characters coming from the input the first output, in a given direction, and performing a serial output subjected to shear characters through output, and N second shift registers, in which each of the above-mentioned second shift register includes an input output clock pulses, the first and second input pins, the first and second output findings, and conclusions of choice, with the above-mentioned second shift registers sequentially actuate or initiate intervals of W characters from the serial character received on the input the output of the first shift register, and each of the above-mentioned second shift registers after the actuation receives the first characters from the NW consecutive symbols, and performs shift and storing the received symbols in a given direction, then each of the above-mentioned second shift register receives the second NW characters through its second input the output moves and storing the received symbols in the direction opposite to the specified direction, and simultaneously performs the serial output remembered the first NW characters through its first output, and then each of the above-mentioned second shift registers receives third NW characters through the first input / output, shift and Suominen the s received symbols in a given direction, and at the same time provides a serial output remembered NW second character through its first output.

2. A buffer memory device according to claim 1, characterized in that the above-mentioned W characters contain consecutive characters of the received frame from the first to the W-th.

3. A buffer memory device according to claim 1, characterized in that each of the above-mentioned shift register operates in response to the fronts of the clock pulses.

4. A buffer memory device according to claim 1, characterized in that N is equal to 2.

5. A buffer memory device according to claim 1, characterized in that the W characters of the window is determined by dividing the received frame into the specified number of frames.

6. The device turbodecoding in the communication system containing a unidirectional shift register having an input the output of which is used for data input and output, is used to output data, with the above-mentioned unidirectional shift register generates bit streams of the first length by sequentially receiving and shifting bits of the input data through input / output, and then provides a serial output generated streams of bits of the first length through the output, the buffer storage device that contains one or more bidirectional shift register having a first output and a second output, which are used for input/output of data bits and the input data are divided into groups, each of which consists of bits and has a second length equal to 1/2 of the first length, with the above-mentioned bi-directional shift register generates bit streams of the second length by sequentially receiving and shifting bits of odd groups of separated groups received via the first output, and then provides a serial output generated flow of bits through the first output and generates bit streams of the second length by sequentially receiving and shifting bits of even-numbered groups of separated groups received via the second output, and then provides a serial output generated flow of bits through the second output, and a buffer memory device further comprises a logical control unit that determines whether the bits of the input data of the divided groups of bits from the odd-numbered groups or bits of even-numbered groups, and feed in the bidirectional shift registers, the selection signals, providing bits of input data to the first output or the second output in accordance with a result of determination, in addition, a buffer memory device further comprises a demultiplexer and a multiplexer corresponding to each of the bidirectional shift registers, and demultiple the SOR contains input output serving for the reception of bits of the input data and the first output and the second output connected respectively with the above-mentioned first output and the second output delivers the bits of the odd groups to the first output via the above-mentioned first output in response to a corresponding select signal received from the logical unit management, and delivers the bits of the even-numbered groups to the second output through the above second output, and a multiplexer performs the multiplexing of streams of bits output through the first output, and the flow of bits output through the second output in response to a corresponding select signal received from the logical unit management, and provides the output multiplexed streams of bits in the first block of the calculation of the metric, the first computing unit metrics, which take the multiplexed streams of bits from the multiplexer buffer storage, and calculation of the corresponding Delta-metric, the second computing unit metrics, which take the Delta metric from the first computing unit metric corresponding to the unidirectional shift register, and the calculation of the alpha metric, the third computing unit metrics, which take the Delta metrics from the first computing unit metric corresponding to the bidirectional add the tax registers, and calculating beta metrics, the fourth computing unit metrics, which take the alpha metrics, as well as carrying out reception of the multiplexing beta metrics obtained through additional multiplexer, and computes the values of the logarithmic likelihood ratio (LOP)corresponding to the respective shift registers, and the decoding device with flexible input and flexible output (SISO device-decoding), containing a subtraction unit that performs subtraction of the output signal of the unidirectional shift register of the corresponding values LOP and the output of the subtraction to interleave/converted alternations.

7. The device turbodecoding according to claim 6, characterized in that the above selection signals are control signals, providing bits of input data in a bidirectional shift registers at different points in time.

8. The device turbodecoding according to claim 6, characterized in that the serial output bits odd groups is performed via the above-mentioned first output and at the same time carry out consecutive reception of bits of even-numbered groups through the above second output and shift.

9. The device turbodecoding according to claim 6, characterized in that the number of bidirectional shift registers determine eleesa number of Windows.

10. The device turbodecoding according to claim 6, characterized in that the above-mentioned first length and the aforementioned second length is determined by the window size and number of Windows.

11. The device turbodecoding of claim 10, characterized in that the above-mentioned second length is determined by the product of the window size on the number of Windows.

12. The device turbodecoding according to claim 6, characterized in that the reception of bits of the input data is carried out at a clock frequency of the device turbo decoding.

13. The device turbodecoding in the communication system containing one or more bi-directional shift registers of the first stage having a first output and a second output, which are used for input/output of data bits and the input data are divided into groups, each of which consists of bits and has a specified length, while bidirectional shift registers of the first stage to form streams of bits above the length by sequentially receiving and shifting bits of odd groups of separated groups coming through the first output, and then carry out serial output generated flow of bits through the above first conclusion, and form streams of bits above the length by successive receiving and shifting bits of even-numbered groups of separated groups received via the second output, and then Khujand what are the serial output generated flow of bits through the above second output, a buffer memory device containing the bidirectional shift register of the second stage having a third output and a fourth output, which are used for input/output data, while the bidirectional shift register of the second stage generates bit streams of the above-mentioned length by sequentially receiving bits sequentially extracted through the first conclusion through the above third conclusion of their shift, and then provides a serial output generated flows through the third bits of the output, and generates bit streams of the above-mentioned length by sequentially receiving bits sequentially extracted through the second output via the fourth output and shift, and then provides a serial output generated flows bits through the above fourth output, and a buffer memory device further comprises a logical control unit that determines whether the bits of the input data of the divided groups of bits from the odd-numbered groups or bits of even-numbered groups, and feed in the bidirectional shift registers of the first stage of the selection signals, providing bits of input data to the first output or the second output in accordance with a result of determination, in addition, a buffer memory device further comprises a demultiplexer and multip EXOR, corresponding to each of the bidirectional shift register of the first stage, and the demultiplexer includes an input output serving for the reception of bits of the input data and the first output and the second output connected respectively with the above-mentioned first output and the second output delivers the bits of the odd groups to the first output via the first output in response to a corresponding select signal received from the logical unit management, and delivers the bits of the even-numbered groups to the second output via a second output, the multiplexer performs the multiplexing of bits extracted through the above-mentioned first output, and bits extracted through the above-mentioned second output in response to a corresponding select signal received from the logical unit management, and provides the multiplexed output bits in the first block of the calculation of the metrics, in addition, a buffer memory device further comprises a multiplexer corresponding to the bidirectional shift register of the second stage, the multiplexer performs the multiplexing of bits output through the third output, and bits output via the fourth output in response to a corresponding select signal received from the logical unit management, and provides output multiplexer the bathrooms bits in the first block of the calculation of the metric, the first computing unit metrics, which take the multiplexed bits from multiplexer buffer storage, and calculation of the corresponding Delta-metric, the second computing unit metrics, which take the Delta metric from the first computing unit metrics and calculation of the alpha metric, the third computing unit metrics, which take the Delta metrics from the first computing unit metric corresponding to the bidirectional shift registers, and calculating beta metrics, the fourth computing unit metrics, which take the alpha metrics, as well as carrying out reception of the multiplexing beta metrics obtained through additional multiplexer, and computes the values of the logarithmic relationship likelihood (LOP)corresponding to the respective shift registers, and the decoding device with flexible input and flexible output (SISO device-decoding), containing a subtraction unit that performs subtraction of the output signal of the unidirectional shift register of the corresponding values LOP, and the output of the subtraction to interleave/converted alternations.

14. The device turbodecoding indicated in paragraph 13, characterized in that the above selection signals are control signals, providing bits of the output data in the bidirectional shift registers at different points in time.

15. The device turbodecoding according to item 13, wherein the serial output bits odd groups is performed via the above-mentioned first output and at the same time carry out consecutive reception of bits of even-numbered groups through the above second output and shift.

16. The device turbodecoding according to item 13, wherein the number of shift registers of the first stage is determined by the number of Windows.

17. The device turbodecoding according to item 13, wherein the reception of bits of the input data is carried out at a clock frequency of the device turbodecoding.

18. The method of operation of a buffer memory device, receipt of a frame, consisting of the serial input symbols, and the input symbols in the decoding device with flexible input and flexible output (SISO device-decoding), working in N-windowed mode, the window size is W characters, namely, that perform sequential shifting and storing 2NW of consecutive characters received from the input / output of the first shift register, in a given direction, carry out serial output subjected to shear characters through the output of the first shift register, perform sequential actuation or initialization N the second is shift registers intervals, is W characters from the serial character received on the input the output of the first shift register, each of the second shift register includes an input output clock pulses, the first and second input pins, the first and second weekends of the findings and conclusions of choice, after actuation of each of the second shift registers shall be implemented by them receiving the first NW of characters from the above-mentioned sequential characters, perform the shifting and storing the received symbols in a given direction, and then through each of the second shift registers admit NW second character through its second input the output, and perform the shifting and storing the received characters in the direction opposite to the specified direction, and simultaneously provide a serial output remembered the first NW characters through its first output, and then through each of the second shift registers admit third NW characters through the first input / output, shift and storing the received symbols in a given direction and at the same time carry out serial output remembered NW second character through its first output.

19. The method according to p, characterized in that N is equal to 2.

20. The method according to p, characterized in that it further perform R is sdelanie accepted frame for a specified number of frames, defining W characters of the window.

21. The way to ensure turbodecoding in the communication system, namely, that through the unidirectional shift register, having an input the output of which is used for data input and output, is used to output data form the bit streams of the first length by sequentially receiving and shifting bits of incoming data through the above input, the output, and then carry out serial output generated streams of bits of the first length through the above output, carry out the separation of the input data into groups, each of which consists of bits and has a second length equal to 1/2 of the first length in the buffer storage device that contains one or more bidirectional shift register having a first output and a second output, which are used for input/output of data using a bi-directional shift register to form the bit streams of the second length by sequentially receiving and shifting bits of odd groups of separated groups coming through the first output, and then carry out serial output generated flow of bits through the first output, and generate the bit streams of the second length by sequentially receiving and shifting bits of even-numbered groups of separated groups received via the second output, asetem carry out serial output generated flow of bits through the second output, additionally, for the logical device management contained in the buffer storage device, determine whether the bits of the input data of the divided groups of bits from the odd-numbered groups or bits of even-numbered groups, and served in the bidirectional shift registers, the selection signals, providing bits of input data to the first output or the second output in accordance with a result of determination, when the buffer storage device further comprises a demultiplexer and a multiplexer corresponding to each of the bidirectional shift registers, and the demultiplexer includes an input output serving for the reception of bits of the input data and the first output and the second output, the United accordingly, with the above-mentioned first output and the second output delivers the bits of the odd groups to the first output via the above-mentioned first output in response to a corresponding select signal received from the logical unit management, and delivers the bits of the even-numbered groups to the second output through the above second output, and a multiplexer performs the multiplexing of streams of bits output through the first output, and the flow of bits output through the second output in response to a corresponding select signal received from the logical device control is, and generates multiplexed streams of bits in the first block of the calculation of the metrics admit multiplexed streams of bits from the multiplexer buffer storage device, and calculates the corresponding Delta-metric in the first computing unit metrics admit a Delta metric from the first computing unit metric corresponding to the unidirectional shift register, and calculate the alpha metric in the second computing unit metrics admit the Delta metrics from the first computing unit metric corresponding to the bidirectional shift registers, and calculate the beta metrics in the third computing unit metrics admit the alpha metric and the reception of the multiplexing beta-metrics obtained through additional multiplexer, and calculate values of the logarithmic likelihood ratio (LOP)corresponding to the respective shift registers, in the fourth block calculate metrics and perform the subtraction of the output signal of the unidirectional shift register of the corresponding values LOP and the output of the subtraction to interleave/reverse alternation in the decoding device with flexible input and flexible output (SISO device-decoding)containing block subtraction.

22. The method according to item 21,characterized in that what the above selection signals are control signals, providing bits of input data in a bidirectional shift registers at different points in time.

23. The method according to item 21, wherein implementing the serial output bits odd groups through the above-mentioned first output and at the same time carry out consecutive reception of bits of even-numbered groups through the above second output and shift.

24. The method according to item 21, wherein the amount of the above-mentioned bi-directional shift registers determine the number of Windows.

25. The method according to item 21, wherein the above-mentioned first length and the aforementioned second length is determined by the window size and number of Windows.

26. The method according A.25, characterized in that the above-mentioned second length is determined by the product of the window size on the number of Windows.

27. The method according to item 21, wherein the reception of bits of the input data is carried out at a clock frequency of the device turbodecoding.

28. The way to ensure turbodecoding in the communication system, namely, that by means of one or more bi-directional shift registers of the first stage having a first output and a second output, used for input/output data, carry out the separation of the bits of the input data into groups, each of which sostoi is from bits and has the specified length, using a bidirectional shift registers of the first stage to form streams of bits above the length by sequentially receiving and shifting bits of odd groups of separated groups coming through the first output, and then carry out serial output generated flow of bits through the above first conclusion, and form streams of bits above the length by sequentially receiving and shifting bits of even-numbered groups of separated groups received via the second output, and then carry out serial output generated flow of bits through the above second output of the bidirectional shift register of the second stage having a third output and a fourth output, which are used for input/output data form the bit streams of the above-mentioned length by sequentially receiving bits sequentially extracted through the first output through the third output and shift, and then carry out serial output generated flow of bits through the above third conclusion, and form streams of bits above the length by sequentially receiving bits sequentially extracted through the second output via the fourth output and shift, and then carry out serial output generated flow of bits through the above fourth output, d is additional to a logical control unit determines whether the bits of the input data of the divided groups of bits from the odd-numbered groups or bits of even-numbered groups, and served in the bidirectional shift registers of the first stage of the selection signals, providing bits of input data to the first output or the second output in accordance with a result of determination, in addition, a buffer memory device further comprises a demultiplexer and a multiplexer corresponding to each of the bidirectional shift register of the first stage, and the demultiplexer includes an input output serving for the reception of bits of the input data and the first output and the second output connected respectively with the above-mentioned first output and second output, delivers the bits of the odd groups to the first output via the above-mentioned first output in response to a corresponding select signal received from the logical unit management, and delivers the bits of the even-numbered groups to the second output through the above second output, and a multiplexer performs the multiplexing of streams of bits output through the first output, and the flow of bits output through the second output in response to a corresponding select signal received from the logical unit management, and provides the output multiplexed streams of bits in the first block of vychisleniyami, additionally via the multiplexer buffer storage device corresponding to the bidirectional shift register of the second stage, carry out the multiplexing of bits output through the third output, and bits output via the fourth output in response to a corresponding select signal received from the logical unit management, and provide the multiplexed output bits in the first block of the calculation of the metrics admit multiplexed bits from multiplexer buffer storage device, and calculates the corresponding Delta-metric in the first computing unit metrics admit a Delta metric from the first computing unit metric and calculate the alpha metric in the second computing unit metrics admit Delta metrics from the first computing unit metric corresponding to the bidirectional shift registers, and calculate the beta metrics in the third computing unit metrics admit the alpha metric and the reception of the multiplexing beta metrics obtained through additional multiplexer, and calculate values of the logarithmic likelihood ratio (LOP)corresponding to the respective shift registers, in the fourth block calculate metrics and perform the subtraction output signal od is napravlennogo shift register of the corresponding values LOP and the output of the subtraction to interleave/reverse alternation in the decoding device with flexible input and flexible output (device SISO decoding)containing block subtraction.

29. The method according to p, characterized in that the above-mentioned selection signals include control signals, providing bits of input data in a bidirectional shift registers at different points in time.

30. The method according to p, wherein the serial output bits odd groups is performed via the above-mentioned first output and at the same time carry out consecutive reception of bits of even-numbered groups through the above second output and shift.

31. The method according to p, characterized in that it further determine the number of shift registers of the first stage in accordance with the number of Windows.

32. The method according to p, characterized in that it further perform receiving bits of the input data at a clock frequency of the device turbodecoding.



 

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2 cl, 8 dwg

FIELD: engineering of data transfer systems for performing automatic control over manufacture of products from glass.

SUBSTANCE: system has multiple electronic devices, meant for performing operations over products made of glass, and also network, mutually connecting devices for mutual information transfer, and including network concentrator of star type and connections, connecting aforementioned concentrator to multiple devices in accordance to network configuration of star type for two-directional data transfer among these devices through concentrator. Network concentrator includes controller, meant for controlling concentrator operations in accordance to communication protocol CANbus, circuits, meant for initialization of measurements and data transfer from one of devices, and circuits, meant for blocking transfer of such data from device, data transfer from which was initiated, and allowing data transfer from device through network concentrator of star type through other devices, connected to concentrator.

EFFECT: increased overall efficiency of data transfer.

7 cl, 9 dwg

FIELD: engineering of telecommunication equipment.

SUBSTANCE: wireless initialization device is a system for administrating computer data traffic, capable of routing TCP/IP traffic with utilization of 2,4 GHz equipment. Aforementioned wireless initialization device, strategically, is subject to positioning in areas of logical segments of wireless network for facilitation of traffic administration. This device operates to provide for possible connection between wireless access points and main line. Device also may be positioned in client local network, providing possibility of access to global network. Wireless device has authentication means, maintaining operative connection with operation system. Wireless device is capable of filtering IP-addresses, controlling a firewall and/or router and/or bridge.

EFFECT: increased effective TCP/IP traffic capacity for global network or local network, at the same time, realization of safe administration and improved integrity.

2 cl, 3 dwg

FIELD: computer science, in particular, engineering of device for input-output of information in electronic computing machine, transferred along communication channels for transferring information; in particular, device is meant for acting as an intellectual multi-port telecommunication port of personal computer, used in mode of central transport station in data transfer networks for specialized use.

SUBSTANCE: multiplexer has system block, wherein four-channeled telegraph one-polar and two-polar modules are positioned, as well as four-channeled standard-joint C2 module, bi-impulse one-channeled and two-channeled modules, one-channeled telephone module, m modules of four-channeled asynchronous adapter, group control electronic board, and also block for adjustment and control, and combination board.

EFFECT: expanded functional capabilities, possible increase of number and types of connected input-output channels, possible synchronization with several types of specialized equipment.

4 cl, 4 dwg, 1 tbl

FIELD: advanced correction of bit and frame error coefficients using turbo-decoding in communication system.

SUBSTANCE: proposed device has composite turbo-code decoder incorporating first adder that computes logarithmic ratio of received code character similarity by calculating difference between character probability equal to 1 and character probability equal to 0 in arbitrary state of turbo-coding lattice; second adder that functions to add transfer information and a priori code character information; third adder that computes difference between outputs of first and second adders as peripheral information; first multiplier that multiplies result obtained from output of third adder by predetermined weighting coefficient; correcting value computer that computes correcting value using difference between best metric and second best metric of code character; fourth adder that adds correcting value to result obtained from first multiplier output.

EFFECT: improved turbo-decoding algorithm using less intricate hardware.

8 cl, 16 dwg

FIELD: advanced correction of bit and frame error coefficients using turbo-decoding in communication system.

SUBSTANCE: proposed device has composite turbo-code decoder incorporating first adder that computes logarithmic ratio of received code character similarity by calculating difference between character probability equal to 1 and character probability equal to 0 in arbitrary state of turbo-coding lattice; second adder that functions to add transfer information and a priori code character information; third adder that computes difference between outputs of first and second adders as peripheral information; first multiplier that multiplies result obtained from output of third adder by predetermined weighting coefficient; correcting value computer that computes correcting value using difference between best metric and second best metric of code character; fourth adder that adds correcting value to result obtained from first multiplier output.

EFFECT: improved turbo-decoding algorithm using less intricate hardware.

8 cl, 16 dwg

FIELD: turbo-decoding in communication systems.

SUBSTANCE: high-speed buffer memory is disposed between receiver buffer memory and turbo-decoding device and operates at same frequency as turbo-decoding device; decoding device reads out information bits stored in receiver buffer memory through high-speed buffer memory, enters delay for read-out information-bits for time required by turbo-decoding device, and then sends delayed information bits to decoding device including flexible input and flexible output of data incorporated in turbo-decoding device; information bit output is effected by receiver buffer memory at operating or clock frequency of turbo-decoding device.

EFFECT: provision for matching operating frequency of turbo-decoding device and that of buffer memory.

32 cl, 20 dwg

FIELD: the invention refers to the field of radio liaison particularly to arrangements and modes for definition of logarithmic likelihood ratio for turbo codes and the metrics of embranchment for convolutional codes at using preliminary coding.

SUBSTANCE: the technical result is reduction of the effect of multiplication of errors achieved because multitude of signal elements is received. At that the signal element contains the totality of modulation symbols out of the totality of coded bits, the first subset of signal elements for which the bit has the first meaning and the second subset of signal elements for which the bit has the second meaning are defined. At that the first and the second subsets are signal elements out of an extended signal group. The probability that the bit equals the first meaning or the second meaning depending from the received signal element is defined, then the symbol of flexible decision of possibility that the bit equals the first meaning or the second meaning is defined. At that the symbols of flexible decision may be represented by the logarithmical likelihood ratios.

EFFECT: reduces effect of multiplication of errors.

38 cl, 7 dwg

FIELD: information technology.

SUBSTANCE: high correcting capacity decoder has a receiving unit, a codeword storage, a unit for correcting deletions, a signal analyser and an estimate storage, as well as a random number sensor, a unit for generating deletions, an estimate ordering unit, an equivalent code unit, a linearity control unit, a comparator and inversion unit. Due to randomisation of deletion solutions, the number of false deletions is reduced and by using transformation of equivalent codes, full use of redundancy introduced into the code is ensured.

EFFECT: high reliability of receiving information.

1 dwg, 2 tbl

FIELD: information technologies.

SUBSTANCE: device comprises a buffer data memory, a unit of syndromes calculation, a Galois processor, a unit of discrete Fourier transformation, a unit for searching of weight error positions t+1, a unit of symbol positions sorting, a unit of error values calculation, a summator of Galois field elements.

EFFECT: higher efficiency of errors correction outside the border of the half of minimum distance by using information on reliability of symbols received from the channel.

6 cl, 10 dwg

FIELD: information technology.

SUBSTANCE: for all resolved code combinations of a systematic (n,k)-code, based on f most significant bits thereof, the cluster number is determined, the value of f lying in the range 1<f≤k/2. Vector V is obtained and the accuracy of receiving the cluster number is estimated based on reliability gradations and the parity bit. In case of a positive solution, the (n-f,k-f)-code is then processed using ordered statistics by first creating a recourse vector Wyk by multiplying f bits by the first f rows of the code generating matrix G and temporary removal therefrom of cluster bits, after which vector Wyk is subtracted from vector V, for which cluster bits are also neglected, while assigning the least significant bit of the newly formed vector Vyr the lowest reliability gradation estimate. The remaining symbols arranged in descending order of their estimates. The error vector E for the shortened code is found using an equivalent code and after subtraction thereof, the decoder performs bitwise summation of vectors Wyk, Vyk and E, forming the transferred vector by repositioning the most significant bits of the cluster number, where is parity check of the cluster number is not performed, the decoder inverts the most unreliable bit from the checked bits.

EFFECT: high decoding speed and reliability of received information.

4 tbl

FIELD: information technology.

SUBSTANCE: soft decision apparatus and method are used to output a soft decision value for each bit of each symbol, used when decoding each symbol, as a value which corresponds to a function value obtained by applying a predetermined function for each bit to the sampling value of each symbol in accordance with the demodulated signal such that probability distribution of the sampling value in each symbol point is a Gaussian distribution. The function for each bit approaches a curve which expresses probability that each bit is equal to 1 or 0 for the sampling value of each symbol of the demodulated signal, and is also defined using a quadratic function.

EFFECT: high accuracy of decoding.

5 cl, 17 dwg

FIELD: radio engineering, communications.

SUBSTANCE: device comprises a correction device, a circuit of bit quality identification, a demodulator, a circuit of symbol quality detection and selection of least valid symbols, a circuit of code cycle synchronisation with integrated soft and hard decisions, a circuit of error vectors generation for least valid symbols, a unit of summators by module two, a unit of decoders of a BCH code, a circuit for detection of least weight, a controller of PC code decoder.

EFFECT: increased validity of information reception in channels with high level of noise.

1 dwg

FIELD: radio engineering, communication.

SUBSTANCE: device comprises data buffer memory, a syndrome computing unit, a Galois processor, a discrete Fourier transform unit, an error position search unit, a symbol position sorting unit, an error value computing unit, a first Galois field element adder.

EFFECT: high efficiency of error correction owing to correction of two additional errors beyond the boundary of half the minimum distance using relaxed solutions.

10 dwg

FIELD: radio engineering, communication.

SUBSTANCE: invention proposes a decoder of a product of 3D codes with requests, which includes a receiving unit, the first output of which is connected to a statistical assessment unit, and the second output is connected to the first input of the line processing unit. The proposed device includes a matrix processing unit, a 3D decoder, a tag unit, a data sampling unit and a request unit. One output of the statistical assessment unit is connected to the second input of the line processing unit, and its output is connected to the first input of the matrix processing unit; the second input of the same unit is connected to the other output of the statistical assessment unit. The first, the second and the third outputs of the matrix processing unit are respectively connected to the first input of the 3D decoder, to the other input of the data sampling unit and to the second input of the tag unit, the first input of which is connected to the third output of the receiving unit, and the first output of the tag unit is connected through one input of the data sampling unit to the second input of the 3D decoder while the second output of the tag unit is connected to the input of the request unit.

EFFECT: improving reliable transmission of information.

1 dwg

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