Method for processing digital data in recording device and recording device for realization of said method

FIELD: digital data processing.

SUBSTANCE: device in form of semiconductor memory device has control block with control elements and memory cells, each of which is made with possible connection to system of buses for connection to central processor and has an in-built microprocessor, including registers, made with possible storage of signs of start of data flow name and its end, information about state and mode of in-built microprocessor. Method describes process of data processing in aforementioned recording device.

EFFECT: higher speed of operation.

6 cl, 7 dwg

 

The invention relates to the field of digital data processing, namely, processing of data in the semiconductor storage device (memory) and the memory architecture, in particular to devices random access memory (RAM), dynamic RAM (DRAM), cache memory, etc.

A computer system typically includes a Central processor for executing commands on a given task and a memory for storing data, programs, etc. requested by the CPU. To improve the characteristics of the computer system mainly trying to increase the speed of the Central processor, as well as to make the access time to memory as short as possible, so that the CPU could work, at least without of wait States. However, the current status in this area is characterized by a growing gap between the speed of data processing in the processors and the speed of the RAM, in particular, the limited width of used tires. We can say that the run time of the se team CPU much more less time to access memory outside of the crystal [see for example: Warneet. The parallel computing system. M: Knowledge, 1999]. To compensate for the gap between the performance of the CPU and memory speed, use different-the e solution.

It is known to use dynamic memory with random access (DRAM), and the data transfer between the DRAM and the CPU is carried out by consecutive blocks of information or data. Thus, for example, the conventional semiconductor memory formed on the semiconductor chip, matrix memory, divided into two banks, consisting of upper and lower matrix of memory cells [patent RU 2156506, publ. 20.09.2000]. Between the first and second banks of memory installed in the control device is designed to generate control signals and devices choice of tires. However, this solution only allows you to minimize the time wait state CPU.

Known application to increase performance optimization systems for handling requests for access to the bus, for example, a known system, switching the microprocessor in the state of the interrupt in response to requesting the interrupt signal and connecting the microprocessor to the local bus of the Central processor of the device to a predetermined minimum period of time [patent RU 2067314, publ. 27.09.1996]. Use the system address bus is not significantly increase system performance.

Known application to increase the performance of computers, multiprocessor systems, the construction of the computer. E.g. the measures the known system and method for assigning a data bus for the processor with digital signal processing [application PCT/GB 95/02130, publication WO 9608774 from 21.03.1996]. The known system includes multiple processors, a common bus to a resource that is used by the processors together. Each processor may contain internal memory, so he has the ability to execute commands without assigning it a bus, each processor may contain registers that allows him to execute commands without prescription tyres. The performance of such a system is also constrained by the width of the bus and the bus address.

Know the use to improve the performance of unidirectional tires. As a prototype of a selected one of such technical solutions, as it is known chip containing data storage device, and a method of processing data in such integrated circuit [patent RU 2137186, publ. 10.09.1999]. Integrated chip includes a CPU, connected to a unidirectional bus read and unidirectional bus write address data memory (e.g. cache, NVR or disk) in the form of a cache memory containing a matrix of memory cells. Bus read and bus write address is generated only in one direction. The technical result is to eliminate loss of time is Yeni due to the reversal of the signal on the bus. Word data read command and a data word is transferred from the cache memory in the core Central processor bus read. The command and address word, the word read address, write address and write data are multiplexed time division bus of entry and address for receipt of the core in the cache memory. Technical solution enables the transfer in batch mode, thereby reducing the number of addresses that you want to transfer on the bus and write addresses, freeing up bandwidth on the bus to use the words of write data. The presence of the address bus is also hinders the performance of the known system. In addition, this system has limited use for specific devices.

Solved technical problem - increasing the speed of processing digital data in a computer system.

We propose a method of processing digital data in a memory device includes a write operation and the read digital data in the memory cells of the storage device by the CPU via the bus system according to the commands of the Central processor, as well as operations management recording and reading digital data. What's new is that part of management operations operate independently of the Central processor in the storage device, when this one is temporarily or consistently in multiple memory cells perform one or more of the following control operations: set bit mode, when a write operation or a read performed on one memory cell; set stream mode in which a write operation or read simultaneously performed on the group of cells; search the name of the digital data; a pointer to the next thread to receive a new portion of the name of the digital data from the Central processor; transferring the pointer to the next thread for the reception of the end of the name of the digital data from the Central processor; transferring the pointer to the previous or next thread to read digital data by the Central processor; translation of the pointer forward or backward to initialize the digital data; a pointer to the previous or next thread to write digital data to the Central processor; transfer pointer to the previous or next thread to check the status of the memory; the pointer to the previous or next thread for comparison; loss of pointer; the command of the Central processor.

In each memory cell can be further record digital data from groups: the sign of the beginning and/or end of the name of the stream; the sign of the memory cell; a sign of the operations performed by the memory cell; a characteristic data bus to which you want to connect the memory cell.

For implementing the method proposed storage device (memory) as provodnikov memory device, containing memory cells, configured to connect to a bus system for connecting with the Central processor. What's new is that the memory further includes a control unit with controls, and each memory cell has a built-in microprocessor, including registers, configured to store the indication of the beginning of the name of the data flow and its end, information on the status and operating mode of the integrated microprocessor, the control unit configured to control the processing of information in the memory cells, and memory cells configured to connect to the data bus and the control bus, including line management interrupt. Naturally, physically bus interrupt can be performed separately, in this case, the memory cell is configured to connect to the data bus and the control bus and to the bus interrupt.

Built-in microprocessor may include the following registers:

- the register storing the sign of the beginning of the name of the digital data stream;

- register storage terminator behalf of the digital data stream;

- one or more status registers of the embedded microprocessor;

one or more mode registers built-in microprocessor, as the number of registers condition, and the number of Regis the ditch operation mode is equal to the number of simultaneously available threads. Built-in microprocessor may also include a register storing information about the line data bus to which you want to connect the memory cell.

The control unit may include a control line sequentially connecting embedded microprocessors (for example, through their registers) with embedded between adjacent memory cells of the keys. When this control line is better to perform unidirectional.

The control unit can contain controls as comparison sites, which include elements And at least one element And each memory cell, the first input of each element And configured to connect only to one particular memory cell, the second input of each element And configured to connect to the data bus, and the output of each element And can be connected to the key between the specified memory cell and adjacent along the line control memory cell. Thus nodes can be connected to a power source.

Keys can be made on the basis of transistors that can be integrated into the control line through the emitter and collector and base of the transistor when it is connected with the control devices of the control unit and/or embedded microprocessors.

The memory cell can be made possible is part of connections:

- to the same data bus and a control bus;

- to the same data bus and two or more buses;

- two or more data buses and the same number of buses.

The memory in all of its elements can be performed as separate integrated circuits, with such an integrated chip better be equipped with a cooling device (e.g., a fan).

The invention is illustrated graphics.

Figure 1 shows the schematic diagram of the memory. Arrows show the direction of data (signals).

Figure 2 presents a drawing explaining the principle of storing data in the memory cells. Slanted arrows pointing downwards, marked memory cells, registers "Stop" written down "the Truth."

Figure 3 presents schematically the principle of operation of node comparisons. We apply the following notation: & logical element AND; SU - control device. Arrows show the direction of data (signals).

Figure 4 illustrates the transmission of the signal on the control line, which also marked with & - logical element I. the Arrows indicate the direction of data (signals).

Figure 5 illustrates the operation of passing a pointer. The arrows show the path of the signals, while the arrows are made of CL is blowing lines: signal "Receive pointer - thin solid line; the control signal keys - dashed line; the signal "pointer" is a continuous main line.

Figure 6 illustrates the operation of passing a pointer to the next thread. The character lines of the arrows is the same as described for figure 5.

Figure 7 presents an exemplary diagram of the layout of the host transfer pointer. Here the arrow is made thin solid line shows the plot line management, you want to signal to transfer the pointer to the previous thread; arrow, made by a dotted line is a plot of the line of control, you want to signal to transfer the pointer to the next thread; and the arrow made a solid main line signal "Receive the pointer.

In General (see figure 1) the proposed storage device 1 (hereinafter referred to memory) 1 includes N memory cells 2 (hereinafter - cell) with built-in microprocessors MK1-N, sequentially connected to the data bus 3 and the control bus 4, including line management interrupt 5, for connection with the Central processing unit (hereinafter CPU; not shown). The address bus is missing, so that, firstly, there is no need to increase the bit address bus used for "classic" architectures to increase the amount of memory, therefore, it is possible to increase the performance of memory 1 is almost unlimited; secondly, the process of reading the digital data (hereinafter " data") is made easier, as will be shown below, which increases the speed of reading.

As in the proposed architecture, the address bus is missing, the cell 2 itself determines what operations to perform using its built-in microprocessor MK when receiving signals from the CPU or multiple CPUs. Built-in microprocessor MK of each cell 2 contains a number of registers (not shown), in the General case, the number of which depends on how much data streams at the same time he can access. For access to a single thread needed: one register for storing the sign of the beginning of the thread name data register "Name"; one register for storing terminator named data stream - register "Stop"; one register for storing information indicating the state in which the microprocessor - register Index; one register, which stores information about which lines in the data bus 3 data transfer must connect the cell 2, - case "Line" (this is done to ensure that the memory architecture, designed for 64-bit systems could be successfully implemented in 16-bit systems); one register to store information about the operating mode of the integrated microprocessor - register "Mode"Razumeetsa, there are actually cell 2, in which to store the necessary information. When multiple simultaneously available threads, the number of registers is increased by two for each additional stream by adding extra register "Index" and an additional register "Mode" for each additional stream.

Each built-in microprocessor MC can independently execute the following commands:

- set bit mode code 00001;

- set streaming mode code 00010;

search name code 00011;

to pass a pointer to the next thread to receive a new portion of the name - code 00100;

to pass a pointer to the next thread for the reception of the end of the name - code 00101;

to pass a pointer to the previous thread to read the data code 00110;

to pass a pointer to the next thread to read the data code 00111;

- move the pointer back to the initialization code 01000;

- move the pointer forward to the initialization code 01001;

to pass a pointer to the previous thread to write data code 01010;

to pass a pointer to the next thread to write data code 01011;

to pass a pointer to the previous thread to check the status code 01100;

to pass a pointer to the next thread to check the status code 01101;

to pass a pointer to the previous thread for comparison code 01110;

p> to pass a pointer to the next thread for comparison code 01111;

- loss of pointer - code 10000;

to run the command - code 10001.

Consider the principle of operation of the memory card 1 with the proposed architecture, which follow the process of executing the above commands. Please accept the condition you have one CPU, and it can simultaneously receive access to only one data stream.

The first two commands set the mode of operation. In bitmap mode operations are performed only on a single cell 2, this mode is effective when you want to change any bits in the stream. In streaming mode, operations are performed on a group of memory cells 2 at the same time; its introduction is associated with the need to increase computer performance when reading or writing large amounts of data. The magnitude of the flow (the number of simultaneously processed memory cells) is determined in the initialization process, but cannot be greater than the number of lines in the data bus 3. The transition from one mode to another can be done at any time. If it was streaming, and passed in bitmap mode, the pointer becomes the first cell 2 of that thread that was active. If the transition from bit mode to streaming mode, the options are:

a) the threads were not created (in this memory still nothing, zapisywa the axis); in this case, possible loss of data, because the memory will accept data still on the same cell 2 (bat), and CPU - send as a stream (bytes), and distortion when the memory outputs a signal on one line, while the CPU reads all lines of the data bus 3, that all this has occurred, it is necessary to check the condition of the cell 2 as a separate command;

b) flows exist; in this case becomes active the whole thread, which would belong to this cell 2.

Let us dwell on the notion of flow. Schematically the in-memory data presented in figure 2, where each of the depicted cell is a cell 2 with built-in microprocessors MK1-MK. Darker cells with a value of "0" or "1" inside " the cell 2, which stores the name of the variable (the more variables can simultaneously be stored in memory, the more cells 2 must be removed to store the name). Lighter cells with a value of "0" or "1" inside " the cell 2, which stores the value of the variable. White cells are empty cells. Thus, shown in figure 2, the variable is represented by three streams: the first stream includes cells numbered from the bottom with MK1 to Mk6 inclusive; the second stream consists of cells with MK to Mk12; in the third stream includes cells with MK to MK. In General, cell MC and Mk20 also represent the way the th threads. Cell MC-MC are part of the name of the next variable (next thread).

Explain the command "Search name" for streaming mode, when the memory 1 is written, the variable a (see piggy, 3 and 4).

So when the CPU needs to get the value of the variable As it sets on the control bus 4 the command "Search name", upon receipt of which the data bus 3 are connected to one input of the item, but only those cells 2, which are characteristic of the "base name". At the same time, registers the Index of these cells 2 writes the value "true"and the line management interrupt set signal with the code "00001", indicating that the memory card 1 is detected file names or variables (and it makes sense to conduct the search). Second input elements And connect itself to the cells 2. After this CPU delivers on the control bus 4 command code "10000", and the data bus 3 is the first part of the name. If the signal received from the data bus 3, corresponds to the signal recorded in the memory cells 2, the input control device (hereinafter - YY) the last cell 2 active flow of a signal is "true" or "false". This happens as follows. Elements And control keys, which are included in the control line, which signal is "true" as shown in figure 4. SU processes this information the following is m follows: if the input received signal is "false", that generates a signal in which all cells of this thread write "false" in their registers Index, and line management interrupt 5 cannot receive any signals; if true, then there are two possible ways, namely, the CPU will signal code "00100" or "00101". When a signal with the code "00100" will be active the next thread, and the cells 2 of this thread will wait for the CPU will signal that allows to compare the information received on the data bus, with the information they store. When a signal with the code "00101" everything happens almost as if the signal code is "00100", with one exception - when the operation is completed on-line management interrupt 5 will receive the signal with the code "00010", indicating that a variable with the same name was found.

So, at the request of the CPU is stored in the memory 1 a variable named "A", the CPU has received an affirmative answer. Now, in order to obtain the value of this variable, the CPU sends the command code "00111", upon receipt of which will be active the next thread, and the cells 2 are connected to the data bus 3 (each cell will be connected to its lines in the data bus 3) is not over the element And and directly. After such connection, the CPU will only give the command code "10001", to place the read operation. If the value of the PE the temporal occupies in memory, for example, 32 bits, and the reading flows is 8 bits, in order to read the next portion, the CPU passes point "00111" and "10001". It should be noted that the CPU does not need to know, how many bits is 1 information about the value of the variable "A" to the CPU found the information about the value of a variable to all cells, just after reading the recent thread on the line of control interrupt 5 is generated a signal with the code "00011", indicating that the end of a variable (file). This occurs as follows: if the next read attempt, namely after the command "00111", the pointer moves to the cell that contains the variable name, the generated signal is the last cell 2 of the first stream, which will give the signal on the control line interruption; if the next read attempt, namely after the command "00111", the pointer moves to the cell 2 that do not contain data, it SU also generates the signal "00011" line management interrupt. Storage variable parts is unacceptable.

We will consider how the process of comparing a variable name with the name passed via the data bus 3.

For this purpose, as already mentioned above, the information of cell 2 flows into the node comparison, implemented on the item And there Postup is no information with the corresponding line of the data bus 3 (see 3). Site comparison controls the key, which is open, if during the operation the result is "true", and closed if the "lie". The control line in which is mounted a key, depending on what is recorded in the register "Stop", can connect to its built-in microprocessor MK (when true) or to the exit, marked in figure 3 as "From the previous cell, if there is a recorded signal is "False". Moreover, if there is a connection to its built-in microprocessor MC, then on exit From the previous cell automatically signal is "True". The connection is achieved that the control line has a built-element "Keys", which is implemented with two transistors. The switch key is performed automatically when you change information in the appropriate register. In addition, regardless of whether the cell 2 a pointer or not, stores the cell 2 any information or not, on site compare power is done to ensure that the line has always been a high potential signal is "true". As shown in figure 4 for an example of an information pack of five cells 2, the signal is "true" reaches the last built-in microprocessor MC only when all the keys will be opened, i.e. the information is transferred via the data bus 3 will coincide with the information stored in the memory cells 2. Built-in mi is reprocessor MC will have the right to process this information, as he recorded in the register is "true". Processing character was shown above.

Let's consider how to implement the process of passing a pointer between the five cell 2 (see figure 5). When giving commands codes from "00100" to "01111", each cell 2 of the active thread, first, checks if there are any in the register "Stop" signal is "true", and if Yes, built-in microprocessor MK1 with this record puts on one of the bus control signal "Receive pointer (depending on which way you pass a pointer, for example, figure 5 transfer is the previous thread), and then sets the register Pointer signal is "false". If the record in this case no, the built-in microprocessor MK2 is reported in the register "Index" signal "false" (the pointer is lost immediately). Built-in microprocessors Mk3 and MK4, on the contrary, recorded in their registers Index signal is "true"because they received signal "Receive the pointer. The mode of operation of the keys depends on the information stored in the register "Stop" and in the General case, for five of the cells 2 is as follows: when the signal is "true" registers "Stop"relevant embedded microprocessors MK1-MK-5, the keys 11, 21, 31, 41 and 51 are closed, and when the signal is "false" in these registers are open; when the signal is "true" registers "Stop" keys 12, 22, 32, 42 and 52 are open, and when the signal is "false" in these registers - close the you; when the signal is "true" registers "Stop" keys 13, 23, 33, 43 and 53 are closed, and when the signal is "false" in these registers are open. With reference to figure 5 the status of the following keys: keys 11, 31, 51, 13, 33, 53, 22 and 42 is closed, the keys 12, 21, 23, 32, 41, 43 and 52 are open.

The pointer to the next thread is implemented easier than described above (see Fig.6), as for the built-in microprocessor MC containing the last bit of the active thread (it generates the signal "Get pointer"), are immediately embedded microprocessors, which you need to pass a pointer. Therefore, for each built-in microprocessor MC requires only one key, which is determined by the data stored in the register "Stop". If in case "Stop" recorded signal is "true", then the key is closed, otherwise, the switch is open. Figure 6 shows that the built-in microprocessors MK1 and Mk3 keep the last bit of thread, but the built-in microprocessor MK1 - active thread, so generates the signal "Get pointer", and Mk3 passive flow, so the key 34 is closed, so the signal does not pass on. An embodiment of the composition of the host transfer pointer shown in Fig.7.

We will consider how the initialization process (markup). I noticed immediately that when power is applied to the cells 2 in their registers "Stop" immediately recorded signal is "True" and it shall own built-in microprocessors MK1-N, and not the CPU. Suppose that the memory card 1 has already been posted some data and need to make the allocation of some variable. The process of finding a place in the General case is reduced to a simple translation of the pointer from one cell 2 to the other, checking its state (stores information or stores the name of a variable or empty) and the count of consecutive empty cells 2. Finally found a place to put a variable and a pointer mounted on the first cell 2, then this cell, after receiving a command code "01000 or 01001", will be connected to the data bus 3, all the registers in a predetermined order, for example: the first line is the register Name; the second line - case "Stop"; the third line is the actual memory cell 2; other lines - case "Line". Because of this simultaneous connection initialization occurs in one cycle.

Consider the possible aspects of programming computers built using the proposed method and storage device. When programming, you must consider the fact that because of the virtually unlimited amount of memory you can record a huge number of variables, constants, files, and similar information. However, running two identical programs has its own characteristics, because you need a slave who you are with the same variables (although to record two variables with the same names, but when they are read can cause problems). To solve the problem by writing a program that will test not currently running the same program, and if Yes, then this program should change the names of variables, constants or files so that when running programs in memory, there would be two variables with the same names, and then would have compiled the program and ran the new version.

Using the proposed technical solutions possible construction of the computer that contains:

1) One data bus and a control bus. Application of computers built with this technology in industry (e.g., CNC), will give a high economic effect as due to the nature of there you don't need high performance, and acquire the low cost of production of this kind of computer, and therefore the industrial equipment based on them.

2) One data bus and several buses. This scheme can be successfully used in consumer electronics. A distinctive feature is the higher speed of computers compared to the first option.

3) Multiple data buses and the same number of buses (multicomputer). This scheme has a high calculation speed. The main application of such the VM - servers.

Consider the peculiarities of application of the proposed technical solutions in multi-processor computers. One of the main issues that are fixed as to ensure maximum write speed-reading when addressing two or more CPUs to the same flow (cell). To do this at the software level may result in a list of commands built-in microprocessor MC of the memory cell 2 commands for handling the above situation. If the cell 2 at the same time will address at least two CPU CP and CP, and CP higher priority and it is connected to the bus No. 1, the cell 2 generates on bus interrupt No. 1 (interrupt line) signal ID "00100", and the data bus No. 2 or disables pre-filing on its bus interrupt signal "00101" (if CP requested record or the processor CP demanded reading, and processor # 2 entry)or leave connected (if CP demanded reading and CP also demanded reading), but also by filing the bus interrupt No. 2 signal "00101". With the arrival of the signal "00100" CP, generating the signal "10001", will be able to perform the desired operation at any time. The receipt of the same signal with the code "00101" means that the CPU must wait, or when CPU with more senior priority will perform its operations, or when you receive data (for scity the years), either move the pointer. Of course, that the CPU must support the above principles. Thus, in the first place will be processed the command, the CPU has the highest priority of those who applied, but the coincidence of the requested action of the CPU with the lowest priority can receive the data (the exception is the write command and initialization). After the operations of the CPU with the highest priority cell 2 will determine which of the remaining CPUs (if any left) have the greatest level of tolerance, and will handle his team.

Of course, that during operation of the proposed storage device will increase the power consumption for an integrated circuit, which implements a mass storage device, you will need forced cooling, for example, by using a fan. However, these shortcomings will be largely offset by a significant increase in performance of computers.

1. A method of processing digital data in a memory device including a write operation and the read digital data in the memory cells of the storage device by the CPU via data bus commands of the CPU applied to the memory device on the control bus, wherein after receiving the command of the Central processor at least the art of processing operations of the digital data carried out independently of the Central processor in the storage device using a microprocessor, embedded in each memory cell, namely at least one operation from the group of: setting a bit of the mode in which a write operation or a read performed on one memory cell, set stream mode in which a write operation or read simultaneously perform over a group of cells, searching for a name of the digital data, the pointer to the next thread to receive a new portion of the name of the digital data from the Central processor, the pointer to the next thread for the reception of the end of the name of the digital data from the Central processor, the pointer to the previous or next thread to read digital data by the Central processor, the translation of the cursor backward or forward to initialization of the digital data, the pointer to the previous or next thread to record digital data from the Central processor, the pointer to the previous or next thread to check the status of the memory cell, passing a pointer to the previous or next thread for comparison, loss of pointer, the command of the Central processor.

2. The method according to claim 1, characterized in that the selection of the memory cells to execute the command of the Central processor exercise using the entry in the register or registers of the microprocessor memory digital data from groups: the sign of the beginning and/or end of the name n is the current status indicator memory cell, the sign of the operations performed by the memory cell, the characteristic data bus to which you want to connect the memory cell.

3. The method according to any one of claims 1 and 2, characterized in that the command of the Central processor serves on the storage device on the same bus management, and recording and reading data by the Central processor of the memory cells operate on the same data bus.

4. The method according to any one of claims 1 and 2, characterized in that the command of the Central processor serves on the storage device by two or more buses, and the recording and reading of data by the Central processor of the memory cells operate on the same data bus.

5. The method according to any one of claims 1 and 2, characterized in that the command of the Central processor serves on the storage device by two or more buses, and the recording and reading of data by the Central processor of the memory cells is performed in the same number of data bus.

6. The method according to claim 1, characterized in that the storage device is cooled.



 

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EFFECT: higher speed.

8 dwg

FIELD: computers.

SUBSTANCE: system has four registers, device for identifying territory of election area, block for determining of direction of data selection, block for forming reading signals, counter, memory block for selection parameters, comparator, elector sex identification block, block for identification of lower limit of age range, block for identification of upper limit of age range, two AND elements and thee OR elements.

EFFECT: higher speed of operation.

5 dwg

Processor // 2248608

FIELD: computers, data protection.

SUBSTANCE: processor has bus interface device, device for selection/decoding of commands, device for dispatching/execution, program string decoding device, which string is selected from program and loaded in first levels command cash, which contains a set of N two-input elements XOR, keys memory, storing different N-bit decoding keys.

EFFECT: higher efficiency.

2 dwg

FIELD: technologies for authentication of information.

SUBSTANCE: method includes performing absolute identification for confirming legality of data carrier according to first rule in preset time. Authentication information is recorded on this data carrier in previously set position. Process of arbitrary authentication is performed for confirming legality of said data carrier in accordance to second rule in arbitrary time. First rule includes announcing confirmation of standard match, if information for authentication is detected as registered in selected preset position. Second rule in given arbitrary authentication process includes announcing standard match, if information for authentication is detected as not registered in arbitrary positions, different from given preset position.

EFFECT: higher reliability.

6 cl, 12 dwg

FIELD: computers.

SUBSTANCE: method includes, on basis of contents of central processor registers, received after processor performs some sort of command, by means of mathematical logical operation, forming certain finite control sum and storing it in memory, and on basis of contents of registers, received before start of execution by said processor of directly next command, certain starting checksum is formed, while if starting checksum mismatches finite checksum, error message is generated, which can be followed by halting of processor operation or blocking of chip board with its removal from circulation.

EFFECT: higher reliability.

2 cl, 2 dwg

FIELD: copy protection.

SUBSTANCE: system has content distribution block, multiple recording and playback devices for digital data, calculations processing block, meant to perform communications with recording and playback devices and performing calculations processing for transferring license payments.

EFFECT: higher reliability of copy protection.

5 cl, 55 dwg

FIELD: electronics.

SUBSTANCE: device has signaling bus, loaded with clock signal, at least one couple of buses serving for encoding one bit, detector circuit, multiplexer. According to method in case of first value of signal of signal bus two buses of one couple detect same level of signal, and in case of second value of signal of signal bus two buses of one couple detect different signal levels, detect forbidden states during operation of board, change process of system functioning, to generate alarm in that way.

EFFECT: higher reliability of protection.

2 cl, 7 dwg

FIELD: microprocessors.

SUBSTANCE: device has central processing devices, including first cryptographic block, at least one peripheral block, including second cryptographic block, device also has data bus, random numbers generator, conductor for supplying clock signal, conductor for providing random numbers signal, set of logical communication elements, while each cryptographic block has register of displacement with check connection.

EFFECT: higher level of unsanctioned access protection.

7 cl, 1 dwg

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