Device for measuring bit error coefficients in fiber-optic communication lines

FIELD: measuring equipment.

SUBSTANCE: device additionally features microcontrollers, one of which generates gating pulses, guided into controlled fiber-optic line before test pseudo-random series, and second one, while receiving gating pulses, produces synchronization signals.

EFFECT: simplified construction, higher efficiency, broader functional capabilities.

5 dwg

 

The invention relates to the field of measurement technology and can be used to measure parameters of optical fiber transmission lines of information.

A device for measuring bit errors in transmission lines, including two generators of pseudorandom sequences, comparing the device, clock, drive errors [1 (p.62, RES)].

Generators of pseudo-random sequences are on different ends of the transmission line. The generators are synchronized from one clock. The signal generated by the first pseudo-random sequence generator and passed the controlled transmission line, compares the bit with the output signal of the second oscillator. In case of discrepancy between the transmitted bits produces an error signal that is accumulated in the counter. The ratio of bit errors is determined by the ratio of the number of bits affected by errors total number of transmitted bits.

The device has the following disadvantages:

- when checking the lines of great length, it was not always possible synchronization of pseudorandom generators from one source;

- the device does not contain optoelectronic and electro-optical converters to control fiber-optic communication lines.

Considered n the drawbacks do not allow to use this device to control the ratio of bit errors of the extended optical fiber data transmission line.

Well-known domestic and foreign device for measuring the ratio of bit errors in communication channels (including fiber optic):

- EDT-135 company Global Headquarters (USA) [2];

- "SHOT-15", CJSC "Technicals" (St. Petersburg, Russia) [3];

IN 30/120 enterprise "ELECTRONICS" (Hungary) [4];

- OG-3 firm "Siemens" [5];

- IR-2-2(5) ZAO "Supercarrier" [5];

- ID-2/8/34 firm "Radian" [6];

CM-E1 firm "Simos" [7].

All of these devices are built on the same block diagram and contain pseudorandom generators at different ends of the line and the clock on the transmitting end of the monitored line. For the functioning of all the considered devices require channeling equipment, which forms the test measurement signal, comprising of a pseudo-random sequence and synchronization signals. And for mixing of the synchronization signals in the transmitted message all these units use a three-tier linear codes HDB-3 or AMI (negative level to a positive level, a value of zero). Fiber optic information transmission can only work with two-level linear codes (optical signal is always unipolar - level optical power of a zero or non-zero).

In affect, the, these units cannot be used to control fiber-optic transmission lines without additional conversion of the three-level linear code into a duplex. As required complex encoders and decoders, the device has a complex architecture and roads (measuring bit errors on the transmission speed of 34 Mbps costs about $6000). Also check the transmission channel is a fiber-optic line is tested at the same time the device channel translating and converters linear codes, so it is difficult to allocate bits errored directly in the fiber optic tract.

The closest to the constructive characteristics of the proposed device is a device for measuring bit errors, described in [8].

The device contains two sections: the generator and the section of the analyzer. The generator section includes a shift register, clock generator, encoder, comparator, and the output of the clock generator is connected to the synchronization input of the shift register and one input of the encoder, the first input of the comparator connected to the output of one of the bits of the shift register, the second to the last digit of the shift register and output to the data input of the shift register. Section analyzer includes a second shift register, the two devices sravnenie is, error count (bits errored), the decoder, and the output clock of the decoder is connected to the synchronization input of the shift register, the first input of the second comparator is connected to the output of one of the bits of the second shift register, the second to the last digit of the second shift register and output to the data input of the second shift register, the first input of the third comparator connected to the output of the second shift register, a second input to the output of the data decoder, and the output of the third comparator connected to the input of counter bits errored.

The device operates as follows. The clock generating section generates periodic pulses (pulse synchronization), shifting the information on the input data in the register. The data input of the shift register is connected to the output of the logical element of comparison "EXCLUSIVE OR". The comparison element EXCLUSIVE OR produces a signal of logical units, if the bits of information at its inputs do not match, and the signal is a logical zero if the bits are the same. The inputs of the logic element connected to the output of the shift register (the last digit) and the output of one of the bits of this register. This circuit allows you to organize generator pseudo-random sequence of bits. The length of the pseudorandom PEFC is the sequences (the number of bits of the register) is defined by ITU-T recommendations O depending on the speed of the digital transmission channel. In addition, there are recommendations on the choice of the configuration of the test sequence. So, for speed digital transmission in the channel 64 to 8448 kbit/s pseudo-random bit sequence should be described by a polynomial of the D15+D-14+1=0, and the speed of 34368 kbit/s - polynomial of D23+D-18+1=0. To simulate a pseudo-random sequence, described by a polynomial of the D15+D-14+1=0, it is necessary in the scheme described above, connected to the inputs of the logic element comparison of EXCLUSIVE-OR outputs 15-th and 14-th digits shift 15-bit register. Similarly, to simulate a pseudo-random sequence, described by a polynomial of the D23+D-18+1=0 must be connected to the inputs of the logic element comparison of EXCLUSIVE-OR outputs 23rd and 18th bits of the shift 23-bit register.

The generated pseudorandom sequence information is sent to the encoder input. The synchronization input of the encoder signal from the clock generator. The device of the encoder depends on the speed of information transmission in the channel.

The clock signal from the clock generator and the output data of the shift register receives the inputs of encoder (encoder), combining these signals in a code sequence. In the simplest case, you use lesiona digital hierarchy (PCI or PDH). For the data transfer rate of 2048 kbit/s synchronous multiplexing the eight-bit code combinations and thus forming the primary digital signal, denoted by E1. The structure of the primary digital signal according to the recommendations G.704 and G.732 presented in figure 1.

It consists of a 32-channel positions duration 3,91 ISS each with a total duration equal to 125 μs. Zero and sixteenth intervals are used for internal purposes:

- zero channel interval (CI) for transmitting signals such as synchronization, control, monitoring and alerts about the accident;

- sixteenth channel interval CI is used for transmitting signaling messages, the synchronization multiframe and indication of an emergency condition.

Pseudo-random test sequence fills the channel information intervals from 1 to 15, 17 to 29 and 31.

The next level of the hierarchy (characterized by higher transmission speed) can be obtained by bit-by-bit multiplexing several signals of the first stage, for example the second step (E2) is provided by combining the four signals E1 with the formation of a cycle 100,4 ISS (see figure 2).

For digital stream E2 the first ten bits represent the signal. The whole cycle is divided into four blocks I, II, III, IV teams matching of speeds, is the quiet used to alert the receiving party for the presence of inserts, the leveling speed of E1 and deleted at the reception.

Blocks I, II, III, and IV contain interleaved data bits four signals E1 with pseudo-random test sequence.

Similarly, it turns out cyclic structure of the third degree of multiplexing E3, which provides transfer speeds 34,368 Mbit/s, however, when this bit together four threads E2 or sixteen E1 and cycle time is reduced to 44,7 ISS. The fourth degree of multiplexing provides a transmission rate of 139,264 Mbit/s (considered as a prototype device provides this level of the hierarchy) and the last fifth degree plesiochronous digital hierarchy provides the speed 564,992 Mbit/s

Consider the device can also work with virtual containers of communication systems with synchronous digital hierarchy (SDH or SDH). Thus, the encoder device fills an information strip container test sequence.

The decoder section of the analyzer performs the inverse function of the encoder it from a structured digital stream extracts the synchronization signals and pseudo-random test sequence. The synchronization signals are received at the synchronization input of the second pseudo-random sequence generator, similar to what tamemasa in the generator section and consisting of the second shift register and the second logic element comparison "EXCLUSIVE OR". The selected decoder pseudo-random test sequence is applied to one of inputs of the third logic gate EXCLUSIVE-OR, to the second input element served a pseudo-random sequence with the output of the second pseudo-random sequence generator (output of the second shift register). With different bit sequences logical element produces a signal of logical units counted by the error counter. The ratio of bit errors is determined by the ratio of the number of bits affected by errors, the total number of bits transmitted.

The device has the following disadvantages:

- high cost and complexity of production;

- does not allow to allocate bits errored directly in the transmission channel, as these errors are errors in the encoder, the decoder, the synchronization channel;

standard linear codes digital streams from E1 and above HDB-3 or AMI have a three-layer structure and may not be transferred by fiber-optic communication lines (for transmission needs to convert a three-level code in the duplex, which can make additional bit errors in the transmission channel).

Not all digital lineages structured digital streams of PCI (PDH or SDH (SDH). There are local digital data collection system, use jsousa signals, coming from transducers of physical quantities, telemetry systems using digital transmission channels to control objects with their own structure of digital streams [10]. To control the ratio of bit errors for these transmission lines is impractical to use expensive canalobre machine.

The proposed device solves the problems of ease and the possibility of measuring the number of bits errored directly in the fiber optic transmission lines information.

The invention consists in that in the generator section of the device entered a microcontroller, an electronic switch, the transmitting optical module, in the section of the analyzer device entered the second microcontroller, the second electronic switch, the receiving optical module, the second clock generator, the clock generator generating section is connected to the synchronization input of the first microcontroller, one of the output ports of the first microcontroller connected to the synchronization input of the first shift register, the output of the shift register through the switch, the second input is connected to one of the output ports of the microcontroller and the control input to the other output port of the microcontroller, is connected to the input of the transmitting optical m is the module, optically linked by fibre-optic cable with optical receiver module, the output of which is connected to one of the input ports of the second microcontroller and to one input of the second comparator, the output of the comparator connected to the counter bits errored through the second electronic switch, the control input of which is connected to one of the output ports of the second microcontroller, one of the output ports of the microcontroller is connected to the synchronization input of the shift register section of the analyzer, the output of the clock generator section of the analyzer is connected to the synchronization input of the second microcontroller.

Figure 3 shows a block diagram of the meter coefficient of bit errors in a fiber optic transmission lines.

The device consists of a generator section HS section analyzer CA. The generator section includes a clock generator 1, the microcontroller 2, the shift register 3, the comparator 4, the electronic switch 5, the transmitting optical module 6. Section analyzer includes a second microcontroller 7, the second clock generator 8, a receiving optical module 9, the second comparator 10, the second electronic switch 11, the second shift register 12, the third comparator 13, the counter bits errored 14. Sections are connected by fibre-optic is Abel, outside the device, and forming part of the controlled fiber-optic transmission lines.

The device operates as follows.

When switching on the supply voltage of the microcontroller 2 and 7 begin to follow the instructions written in the memory resident programs. The plot of processes at different points generator section and analyzer are presented in figure 4.

Program execution begins with the installation of the control input of the switch 5 signal for enabling connection of the input of the transmitting optical module to the output port of the microcontroller 2. After waiting for run-time N machine cycles, which are necessary for the operation of the switch 5, the output port is generated by the start pulse. The duration of this pulse is determined by two conditions:

- the duration of the start pulse must be longer than the pulse duration of the data transmitted over the transmission line, and to ensure energy supply, sufficient for transmission without distortion;

- the duration of the start pulse should correspond to the allowed range in duration for transmitting and receiving modules.

After generation of the start pulse, the microcontroller 2 sets the control input of the switch 5 signal, an enable input before the irradiation of the optical module 6 to the output of the shift register 3. After waiting, during which occurs the trigger switch 5, the output of the microcontroller 2, connected to the synchronization input, the shift register 3 generates a sequence of clock pulses. The duration of the pulses is determined by the duration of a machine cycle of the microcontroller 2 and is determined by the frequency of the clock generator 1. The repetition rate must match the data rate at which the tested line. The number of pulses in the sequence of clock pulses must comply with the recommendations of ITU-TO.152 (GOST 26783-85). The shift register 3 at the front of synchronization signals generates at its output a pseudo-random sequence of pulses. The structure of the pseudo-random sequence is defined by the comparator 4 in accordance with the recommendations of ITU-TO.152 (GOST 26783-85) and is determined by the numbers of bits of the register 3, the outputs of which are connected with inputs of the comparator 4. A pseudo-random sequence through the switch 5 is directed to the input of the transmitting optical module 6, is then converted into an optical signal and sent to the test optical fiber transmission line.

The microcontroller 2 is transferred to the formation of the next test sequence consisting of a start pulse and a pseudo-random sequence is acceptable duration and structure.

Generated by the generator section of the test sequence on the optical fiber transmission line information supplied to the optical input of the receiving optical module section of the analyzer 9. The output of the receiving optical module 9 is connected to the input of the microcontroller 7 and one of the inputs of the comparator 10. The second microcontroller 7 the decay of the signal at its input starts to execute the processing routine external interrupts. The interrupt processing subprogram performs the following steps:

- disables external interrupts;

- generates a signal at the input of the second switch 11, permitting the connection of the output of the comparator 10 to the input of counter bit errored 14 (in the initial state, the switch is open);

through N machine cycles (frequency generators 1 and 8 must be equal) generates a sequence of pulses similar sequence generated in the generator section;

after the formation of the sequence of clock turns off the switch 11 (severs the link between the counter bit errored 14, and the output of the comparator 10);

- enables external interrupts.

This routine interrupt processing terminates.

The sequence of synchronization signals generated by the microcontroller 7, n is problemsa to the synchronization input of the shift register 12 is similar to the shift register 3. The case 12 together with the comparator 13 generates a pseudo-random sequence similar to the sequence generated by the register 3 and the comparator 4. This sequence is sent to the second input of the comparator 10, which compares with a pseudorandom sequence output from the photodetector module 9. When mismatching bits sequences generated error signal, which is input to the counter 14. The ratio of the number of bits affected by errors total number of transmitted bits determines the ratio of bit errors. The count of bits transmitted may lead microcontroller 2 and the second microcontroller 7.

Thus, achieving the goal is the possibility to measure the ratio of bit errors of fiber-optic transmission lines and the device is greatly simplified, as it does not contain complex encoding and decoding devices for the transmission of synchronization signals together with the test sequence of bits.

Bibliography

1. Cormorants I.G. Testing and diagnostics systems. - M: Eco-Trends, 2001, - 264 C.

2. Information on the Web site of the company's Global Headquarters, http://www.acterna.com.

3. Information from the Web server of the company "Energy Telecom", http://www.energy-telecom.ru.

4. Information from the Web server of the company "ELECTRONICS", http://www.lektronika.ru.

5. Information from the Web server of the Internet project "RusCable.ru", http://www.ruscable.ru.

6. Information from the Web server of the company "Radian", http://www.radian.spb.ru.

7. Tester CM-E1. Technical description and operating instructions CM2. TO, July, 2003

8. Information from the Web server the Trend Communications, http://www. trendcomms.corn from March 2004

9. Ivanov P., Levin PS and other Complex terminal equipment digital transmission systems ENCORE // telecommunication, 1992, No. 3.

10. GOST RV 50899-96. The data collection network of fiber-optic based optical fibre sensors. General technical requirements.

Measuring the ratio of bit errors in a fiber optic transmission lines, containing installed in the generator sections of the comparator, the oscillator and the shift register output and an additional output which is connected to the inputs of the comparator, the output of which is connected to the data input of the register set out in the section analysis of the second shift register output and an additional output which is connected to the inputs of the second comparator, the output of which is connected to the data input of the second shift register, the counter bits errored, the third comparator, the first input connected to the output of the second shift register, wherein in the generating section introduced the microcontroller, electronic switchboard is Thor, the transmitting optical module connected to the test fiber-optic transmission line, in the analysis section introduced the second microcontroller, the second clock generator, the second electronic switch and the receiving optical module connected to a second end of the test fiber-optic transmission line, and the output of the clock generating section connected to the synchronization input of the first microcontroller, the outputs of which are connected to the synchronization input of the first shift register, the first dial-up and control inputs of the electronic switch, the output of the first shift register connected to the second dial-up input of the electronic switch, the output of which is connected to the input of the transmitting optical module, the output of the clock generator section analysis connected to the synchronization input of the second microcontroller, the outputs of which are connected to the synchronization input of the second shift register, the control input of the second electronic switch, the output of the receiving optical module is connected to the input of the second microcontroller and a second input of the third comparator, the output of which is connected to the input of counter bits errored through the second electronic switch.



 

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