Device for measuring and controlling amplitude-frequency characteristic of quadripole

FIELD: amplitude-frequency characteristics of quadripoles.

SUBSTANCE: control of quadripole is realized in two stages. At first stage, estimation stage, N counts of measurements results are received during length T of one signal period, and on second stage, analysis stage, during time T received signal estimation results are recognized with determining of class of technical state of object (like breakdown). To realize first stage of control, to present clock pulse generator, first counter, delay element, first register, first AND element, adder, additionally inserted are two keys, two analog-digital converters, second register and operative memory block for estimation results, to realize second control stage additionally to first and second comparison block, indication block, inserted are breakdowns signs memory block, breakdown counters and commutator, and for controlling control stages to present launch element, first counter, second AND element, key element is additionally inserted.

EFFECT: higher speed of operation.

5 dwg

 

The invention relates to techniques for telecommunication and can be used when checking the amplitude-frequency characteristic (AFC) of four terminal networks, including communication channels.

Known automated control system for automated control of electronic equipment complex objects containing the switch, the Converter analogue-code, two block matching, a buffer memory unit, the parallel Converter code serial decoder, the block of electronic keys, digital computing machine, block I / o, synchronization unit, interface unit, two optical transceiver, fiber-optic communication line, a personal computer, an additional interface unit, highway interchange (RF patent No. 2015622, CL N 04 3/46, 17/00, 1994).

The disadvantage of this device is the low performance of the diagnostic control object due to the need to measure a large number of different parameters.

The closest to the technical nature of the claimed invention is a device for measurement and control of amplitude-frequency characteristics of two-port network containing the starting element, the clock, the case of delay, the three elements, the driver of the reference signal, the notch filter, trigger, delay element, three p the selector, the unit of comparison, a band-pass filter (A.S. USSR № 1681392 A1, class H 04 3/46, publ. 30.09.91,, bull. No. 36).

The disadvantage of this device are low performance and reliability of the diagnostic control object. This is because the recognition of failures in the facility must measure the N values of the coefficient of mutual differences between the reference and the monitored signals. In this case N≫1, because of the need to ensure the required accuracy of recognition failure (minimizing the probability of error detection).

The main task, which directed the inventive device is to increase speed control of a quadrupole.

This assumes control of the quadrupole to be implemented in two stages:

at the first stage (the evaluation phase) to obtain N samples of the measurement results during the duration T of one period of the signal;

in the second phase (phase analysis) during the time T to recognition of the obtained results of the evaluation signal with a class definition of a technical condition (denial) of the object.

This technical result is achieved by the fact that in the known device for the implementation of the first phase control to the generator of clock pulses, a first counter, the delay elements, the first register, the first element And su is the transformer additionally introduced two key two analog-to-digital Converter, the second register and the memory block of the results of the evaluation for the second phase control in addition to the first and second set of comparisons, the display unit enters a block of memory signs of failure, meters bounce and switch, and to control the stages of control to an existing start-up element, the first counter, the second element, And optionally enter a key element.

Figure 1 presents the structural electrical diagram of the device.

Device for measuring and controlling the frequency quadrupole contains the starting element 1, the generator 2 clock pulses, a first counter 3, a key element 4, the first element 5 And two keys 6 and 7, the delay element 8, two analog-to-digital Converter 9 and 10, two registers 11 and 12, the adder 13, block 14 RAM evaluation results, the second element 15 And the second counter 16, the first block 17 comparison unit 18 memory signs of failure, the switch 19, the meters bounce 20.1...20.m, the second block 21 comparison unit 22 display.

Figure 2 - distortion frequency response in the region of the third harmonic signal, 3 - distortion frequency response due to the narrow bandwidth of the quadrupole (5-th harmonic of the signal).

The device operates as follows.

Before you begin block 14 RAM evaluation results, as well as the registers 11 and 12 n is formed in the initial (reset) state. In the cell block 18 of the memory contains information about the signs of the failure of the object.

When the trigger element 1, the voltage applied to the input of the generator 2 clock pulses, the first pulses to the first input of the second element And with the second output pulses for the first 3 counter that with the first pulse brings key element 4 in position "1". Output key element of the voltage applied to the second input of the first element 5 I.

The analyzed signal from the test object is supplied to the information input keys 6 (directly) and 7 (via the delay element 8). The voltage coming from the starting element 1 through the opened first element 5 And the control inputs of the keys 6 and 7 provides passing the values of the signal through the analog-to-digital converters 9 and 10 and then transformed to corresponding inputs of the registers 11 and 12. The recorded values via the adder 13 receives the first information block 14 RAM of the results of the assessment, which consists of N memory cells.

When calculating the N-th pulse from the output of the first counter 3 is fed to a key element 4, throwing it in the state "2", then the first counter 3 is reset to zero. The device is switched from a mode estimation signal mode of analysis results. The first element 5 And closed is provided, and the voltage with the key element 4 opens the second element 15 And passing through the gate pulses from the output of the generator 2the input of the second counter 16.

From the output of the second counter 16 pulses with a repetition frequency N/T is fed to the input unit 18 of the memory characteristics of failures in managing the third input unit 14 of the operational memory of the results of the evaluation and the control input of the switch 19. From the output of block 18 of the memory characteristics of the failure signal to the first input of the first 17 Comparer, to the second input of which receives the signal from the output of block 14 RAM evaluation results. In the first 17 block comparison is adding the value of diagnosed and reference signals modulo two. With the first beat of the second counter 16 is compared with the first technical conditions (TC) block 18 memory signs of failure. With the release of their first 17 unit compares those values are sent to the input of switch 19 in which the number of outputs corresponds to the number of TS in the memory block 18 signs of failure. From the output of the switch 19, the signal is fed to the input of the counter bounce 20.m, which records the number of discrepancies between the values obtained in the first 17 block comparison. The number of pulses of the second counter 16 corresponds to the number of technical conditions recorded in block 18 of the memory characteristic is in denial. After N pulse of the second counter 16 is value comparison unit 21 in the second block comparison, recorded in meters 20.1...20.m, the smallest number of units corresponds to a specific technical condition recorded in the memory block 18 signs of failure. The result from the second unit 21 of the comparison is supplied to the display unit 22 after the count N of the pulse from the output of the second counter 16. Upon receipt of the information in the display unit 22 is supplied enable signal to the second information input unit 14 of the operational memory of the results of the evaluation signal to reset the values of the memory cells.

Since the N-th pulse at the output of the second counter 16 corresponds to the N-th pulse is counted by the first counter 3 at the second stage operation of the device, with the output of the first counter 3 switch key of the element 4 in position "1". The device returns to its original position and ready to operate in the first mode estimation signal.

Device for measuring and control of amplitude-frequency characteristics of two-port network containing connected in series starting element, a generator of clock pulses and the first element And the second element And the first input of which is connected to the first generator output clock pulses, a first counter, an input connected to the second output clock pulse is law, the first block of comparison, connected in series, the second block comparison and indication unit, delay element, connected in series the first register and the adder, wherein the additionally introduced sequentially connected first key, the first analog-to-digital Converter and the second register, the output of which is connected to the second input of the adder, connected in series with the second key and the second analog-to-digital Converter, the output of which is connected to the input of the first register, a key element, the input of which is connected to the output of the first counter, the first key element is connected to a second input of the first element And whose output is connected to the control inputs of the first key and the second key, the input of which is connected to the output of the delay element, the input of which is combined with the input of the first key, is used to supply test signal from the test object, the first information input of the block RAM of the evaluation results is connected to the output of the adder, and the second information input connected to the output of the display unit, connected in series to the second counter and the memory block signs of failure, the output of which is connected to the second input of the first unit of comparison, the first input connected to the output of the block RAM of the evaluation results, the control input vtoro what about the counter connected to the output of the second element, And the second input is connected to the second key element, the third control input of the block RAM of the evaluation results is connected to the output of the second counter, the switch information input of which is connected to the output of the first unit of comparison, the m counters, bounce, the inputs of each of which is connected to the respective outputs of the switch, a control input connected to the output of the second counter, the outputs of the m counters bounce connected to the corresponding inputs of the second Comparer.



 

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