Method for manufacturing self-combined transistors with ultra- short channel length, produced by non-lithographic method

FIELD: technologies for making transistors.

SUBSTANCE: method includes following stages: precipitation of electric-conductive material on substrate of semiconductor material, forming of shape of first parallel band electrodes with step, determined by appropriate construction rules, while areas of substrate in form of stripes between first electrodes are left open, precipitation of barrier layer, covering first electrodes down to substrate, alloying of substrate in open areas, precipitation of electric-conductive material above alloyed areas of substrate with forming of second parallel band electrodes, removal of barrier layer, near which vertical channels are left, passing downwards to non-alloyed areas of substrate between first and second electrodes, alloying of substrate in open areas of lower portion of channels, filling channels with barrier material, removal of first electrodes, during which gaps between second electrodes are left and substrate areas are opened between them, alloying of open areas of substrate in gaps, from which first electrodes were removed, removal of electric-conductive material in said gaps for restoration of first electrodes and thus making an electrode layer, containing first and second parallel band electrodes of practically even width, which are adjacent to alloyed substrate and separated from each other only by thin layer of barrier material, while, dependent on alloying admixtures, used during alloying stages, first electrodes form source or discharge electrodes, and second electrodes - respectively discharge or source electrodes of transistor structures, precipitation of insulating barrier layer above electrodes and separating barrier layers. Precipitation of electric-conductive material above barrier layer and forming in said electric-conductive material of shape of parallel band valve electrodes, directed transversely to source and discharge electrodes, thus receiving structures matrix for field transistors with very short channel length and arbitrarily large width of channel, determined by width of valve electrode.

EFFECT: ultra-short channel length of produced transistors.

11 cl, 17 dwg

 

The technical field to which the invention relates.

The present invention relates to a method of manufacturing transistors with ultra-short channel length of.

The level of technology

The goal of many studies is to reduce the size of electronic circuits on substrates of silicon and other materials). This is combined with attempts to increase the switching speed, reducing the channel length to a greater extent than is allowed by the rules of design and the possibilities of lithography. In the field of semiconductor technology, a large proportion of efforts aimed at reducing the size of electronic circuits. For photolithography maximum possible dimensions of the elements will soon be achieved and therefore are very serious work in the field of x-ray lithography and the search for other, more exotic approaches to development until 2010 in production line widths and distances between the lines of the order of 0.04 μm (40 nm). However, while these values largely reflect only goal of the developers, such as creating a monomolecular keys, nanoparticales etc.

More promising may be alternative methods of forming the pattern without involving lithography, for example technology microforaminotomy relief or self-Assembly. However, the latter are even more exotic than the most daring experiments in the field of lithography, as they enter a completely new processes and equipment in a very conservative industry. Moreover, none of these two mentioned technologies currently does not have, and probably never will have the actual potential, which would allow to build complex schemes, partly because of alignment problems, partly because of the problems associated with the construction of multilayer structures. Other technologies (for example, using hard stamps, see Obducat) involve the same difficulties.

Problems that cannot be solved currently known technologies, the following: 1) receiving channels (i.e. distances between the electrodes of the source and drain) ultra-small length (a few atoms); 2) the achievement of ultra-small length of the channels using either standard methods of working with silicon, standard manufacturing techniques and standard equipment, either through non-standard techniques that are not associated with lithography; 3) the use of channels of ultra-low length to reduce the area occupied by the circuit on the substrate, i.e. to build more dense the schema with data lithography tools/build relief; 4 the attainment of the above results with samoobladanie elements.

Disclosure of inventions

Thus, the problem to be solved in the present invention is, is a method that effectively copes with the above-mentioned problems inherent in currently known techniques.

The solution of the problem posed by the invention, as well as obtaining a number of additional properties and advantages are achieved using the method corresponding to the present invention, which includes the following steps:

a) precipitated conductive material on a substrate of semiconductor material,

b) conductive material to form the relief of the first parallel strip electrodes with a spacing defined by the relevant design rules, while leaving the exposed region of the substrate in the form of strips between the first electrodes

c) precipitated barrier layer covering the first electrodes up to the substrate,

d) is produced by doping the substrate in the open field,

e) precipitated conductive material over the doped regions of the substrate, forming a second parallel strip electrodes,

f) removing the barrier layer covering the first electrodes, leaving the vertical channels, passing down to the undoped regions of the substrate between the first and second electrodes,

g) is produced by doping the substrate in the open areas of the lower part of the channels,

h) fill in the channel b is remim material

i) removing the first electrode, leaving gaps between the second electrodes and the opening between them is the area of the substrate,

j) is produced by alloying the open areas of the substrate in the intervals from which you removed the first electrodes

k) precipitated conductive material at specified intervals to restore the first electrodes and thereby obtaining an electrode layer containing first and second parallel strip electrodes, essentially equal to the width of that border with alloy substrate and separated from each other by only a thin layer of barrier material, in this case, depending on the dopants used during doping, the first electrodes to form source electrodes or drain, and the second electrodes, respectively, the electrodes of the drain or source of transistor structures,

l) precipitated insulating barrier layer over the electrodes and the separation barrier layers,

m) precipitated conductive material over the barrier layer and

n) form on the specified conductive material relief of parallel strip electrodes shutter, oriented transversely to the electrodes of the drain and source, thereby obtaining the matrix structures of field-effect transistors with very short channel length and arbitrarily large width of the channel defined by the width of the electrode satwa the A.

In the method corresponding to the present invention, the electroconductive material is preferably metal. Alternatively, as the conductive material may be selected organic material, preferably a polymer or copolymer material.

In the General case, it is desirable that at the stage of formation of the pattern was used photomicrography, but equally it is desirable that at the stage of formation of the pattern could be used nelitografichesky tools.

According to the method according to the present invention, it is desirable that the removal of the barrier layers and/or electrodes were produced by etching.

The formation of the thin film barrier layer is preferably produced by means of selective deposition; alternatively, a thin-film barrier layer can be formed by sputtering.

When implementing the method according to the present invention, it is desirable that the formation of the relief was carried out by etching.

It is also desirable that the material of the semiconductor substrate was selected silicon.

In the method corresponding to the present invention, to obtain the individual field-effect transistors or circuits containing more than one transistor of this type, the matrix transistor structures preferably Elat on corresponding zones.

Brief description of drawings

For a better understanding of the invention below is a stepwise description of the method of producing transistors with examples of options for implementing the various steps that are recommended to be considered together with the attached drawings.

The drawings (figures 1, 2A, 3-11a, 12 and 13) illustrate the sequence of process steps of a method of obtaining a transistor structures corresponding to the present invention, by providing cross-sectional structures formed at each stage,

fig.2b is a top view of the structures shown in cross section on figa,

fig.11b is a top view of the structures shown in cross section on figa,

figa is a top view of a matrix of field-effect transistors produced using the method corresponding to the present invention, with outlines of the channels and the electrodes of the source and drain, as shown by the dashed lines,

fig.14b is a cross-section of the matrix figa plane a-A.

The implementation of the invention

Next will be described steps of the method corresponding to the present invention.

1 shows a substrate 1 of semiconductor material with an appropriate barrier layer, which is produced by the deposition of a layer 2 electrically conductive material. This material may be any the m conductive material, both inorganic and organic, which is suitable for application suitable method of deposition. Itself substrate, depending on the selected material may be rigid or flexible. Preferably, the substrate was silicon. Then on the conductive layer 2 suitable means to form, for example by photomicrography followed by etching the pattern in the first parallel strip electrodes, as shown in figa and corresponding top view (fig.2b). Step, that is, the width w of the electrode plus the distance d to the next electrode, of course, will depend upon the relevant design rules and can meet the minimum size f element, which is limited by the capabilities of the process. In this case, the values of w and d will be approximately equal, although, of course, nothing prevents to make the value of d is much greater than w. When the formation of the relief remain cavity 3 between the first electrodes 2, as shown in figa, and now these parallel strip electrodes 2, which in fact can be made very thin, i.e. the height h is much less than its width w, the cover, as shown in figure 3, a thin film barrier layer 4, which passes over the first electrodes 2 and down to the substrate 1 in the hollows 3. The thickness of the barrier layer is not limited nor is akimi the design rules and, therefore, it can be very small, up to monatomic sizes.

The bottom of each trench 3 is corresponding to the open area of the substrate 1, as shown in figure 3. Further, as shown in figure 4, to produce the doping of the substrate 1 in these open areas in order to obtain the substrate 1 doped regions 5 with the desired conductivity type, for example, with electronic conductivity (conductivity of n-type or p-type conductivity (conductivity p-type). In the next process step, shown in figure 5, the trench 3 is filled with the conductive material 6, so that on top of the doped regions 5 in the substrate 1 to form a second parallel strip electrodes 6. After that, as shown in Fig.6, using any suitable process, such as etching, to remove the barrier layer 4 with the first electrodes 2, leaving the vertical channels or grooves 7 between the first and second electrodes 2, 6. As a result, the bottom of the vertical channel 7 opens unalloyed portions of the substrate 1, and during the second operation doping, shown in Fig.7, produce alloying these areas of the substrate with the aim of obtaining it doped regions 8. It is obvious that doping impurity are now choosing to create in the areas 8 of the substrate conductivity, for example, p-type, if fields 5 when doping was astanaproekt n-type, and Vice-versa.

Then the vertical channels (grooves) 7 fill insulating barrier material 4, which, for example, may be precipitated by controlled spraying or precipitated in the form of a barrier layer on the entire plate with subsequent removal of excess material. This barrier material 4 will be now, of course, to cover portions of the substrate 1, which is above the doped regions 8, as shown in Fig. In the next process step to remove the first electrodes 2, leaving depressions (grooves) 3' between the second electrodes 6 with a barrier layer 4, as shown in Fig.9. Removing the first electrode 2 can be produced, for example, by using photomicrography and etching, followed by a third alloying operation, whereby in the open and unalloyed portions of the substrate 1 in the grooves 3' will be introduced admixture with the aim of obtaining the substrate doped regions 9, as shown in figure 10.

The doping regions 9 will be conducted in order to obtain the corresponding conductivity type, i.e. n-type if in areas 5 when doping was formed an n-type conductance, and in areas 8 - conductivity p-type. Of course, can be obtained and the reverse combination type conductivity. At the next stage of the technological process restores the first ele is trudov, as shown in figa, simply by filling the grooves 3' above the doped regions 9 of the substrate 1 with a thin film of the respective electrically conductive material, which again may be either inorganic or organic. In any case, it should be understood that the first and second electrodes 2, 6 it is desirable to use electrically conductive material of the same type. The resulting structure is shown in the fig.11b.

It is seen that the first and second electrodes 2 and 6, the contact areas 5, 8, 9 in the substrate 1, with appropriate doping, can form a parallel strip, very closely spaced electrodes, respectively, the source and drain in the transistor structure. The channel length L, i.e. the distance between, for example, the source electrode 2 and the electrode 6 flow (figa) under the barrier layer 4 is determined by the width of alloy region 8 in the substrate. This length can be made extremely small - if you want, much less than 1 nm, due to the fact that the thickness of δ the barrier layer 4 is obtained in the process of deposition of extremely thin film barrier material, and this process has not imposed any restrictions associated with the design rules. Specialists in this field it is well known that it is possible the deposition of such barrier layers even monatomic thickness, what upon nalos earlier. Therefore, the length L of the channel in the transistor structure, made in a way consistent with the present invention, can be almost arbitrarily small, and this, as will be seen, is a very desirable property, for example, field-effect transistors.

In addition, the upper surfaces of the electrodes 2, 6 source and drain supply barrier layer 4, so that the electrodes 2, 6 in any case be mutually isolated, and the upper surface is also isolated, as shown in Fig Now applied over the entire plate barrier layer 4, also on the whole plate, put a layer in the form of another thin film 10 of electrically conductive material, then the layer 10 to form a relief in order to obtain the gate electrodes in the transistor structures produced in a way consistent with the present invention. It should be clear that the actual formation of the gate electrodes can be made through technological operations, such as those which were used when forming the first and second electrodes 2, 6, and different stage of this process will be a copy of the steps shown in figure 1, 2A, 3 and 5. Therefore it can be obtained very dense grid of electrodes 10.

Each of the second set of gate electrodes is created at the stage of formation of the pattern, which can osnovyvat is, for example, in photomicrography followed by etching performed before deposition of a suitable barrier layer. This, of course, implies that the possible sizes of the electrodes of the shutter caused by the same considerations that were taken into account based on the amount of the first and second electrodes 2, 6. Therefore, it is possible to make separate electrodes 10 different shutter width W. this, in turn, implies that the individual transistor structure produced by a method corresponding to the present invention, it is possible to do with changing the ratio of channel width to the channel length, W/L. the Experts in this field it is well known that it is highly desirable to have a large ratio W/L as the amount of current IDflow is proportional to this ratio, multiplied by the effective value of the voltage control and the value of the parameter, depending on the technological process.

Thus, transistors made in a way consistent with the present invention can provide several advantages. For example, the switching speed of the transistors depends on various factors, but the main structural parameter affecting the switching speed will always be the distance L between the electrodes of the source and drain, as the charge carriers takes time to overcome this distance is. In other words, the smaller the distance L, the higher, ceteris paribus, the switching speed. The currently known technical solutions and modern technologies have and will be limited by the minimum feature dimensions, permissible pursuant to applicable technological processes. For example, the use of lithography with a resolution of 0.18 μm assumes a minimum channel length of 180 nm. Although lithography, in accordance with modern standards, will continue to be used at the stage of forming the pattern of the electrodes, it is obvious that the method corresponding to the present invention, can actually reduce the length L of the channel to, for example, is much smaller than 10 nm as the thickness of the barrier layer, there are no restrictions imposed by the design rules.

It may be that the width W of the gate electrode corresponding to the width of the channel, the rules of construction relating to the formation of the pattern, which is used to create this particular electrode, impose a limitation on the bottom. In this case, as shown in fig.14b, correction of the actual width W of gate electrodes formed on the stage, similar to that shown in figure 5 to create electrodes 6, can be done by simply increasing the thickness of the barrier layer 4 between electr who DAMI 10 shutter before how to perform an additional deposition of electrode material in the grooves for the gate electrodes, the pattern which has already been formed. Consequently, each of the second gate electrode in the transistor matrix structure will now be possible to form the electrodes of the shutter so that it is possible to obtain transistors with different width W.

It follows that one of the most important aspects of the method corresponding to the present invention, is the ability to control the ratio of the width W and channel length L of the channel, i.e. the ratio W/L, which is a very important settlement option. Indeed, this parameter is a scale factor for the current IDrunoff. Moreover, the present invention allows fabricating field-effect transistors of any type. In addition, it will be possible to produce on the same substrate field effect transistors, identical in structure but with different values of the selected design parameters. For example, one substrate can be produced by two or more MOS transistors having the same threshold voltage VTbut different maximum currents, as it will be possible to use different values for the W/L. High values of current IDflow, for example, of the order of several milliamps, can only be obtained from transistors with a high on the wearing W/L. In the case of technologies used at present, this means that we are talking about devices that use very large area substrate. In the case of the present invention the ratio W/L can be chosen almost arbitrarily large, and thus will not be busy unacceptably large area on the substrate. It is noticed that the ratio W/L can be increased to ensure any desired level of current. However, modern technology suggests that this means an increase in the area of the shutter and thus increase the electrical capacitance of the device, which affects the speed of the switching transistor. For example, MOSFET transistors, the ratio W/L is limited to not more than 10. These unwanted restrictions completely eliminated, if the manufacture of transistors to implement the method corresponding to the present invention.

Described preferred variant implementation in relation to the formation of the pattern of the electrode structures is based on the use of traditional processes microphotolithography and etching. Note, however, that the method corresponding to the present invention with equal success can be achieved when using more complex processes of pattern formation, including soft lithography and the use of funds is not connected is with lithography, such as, for example, hard or soft stamps for obtaining the required drawings of relief. To obtain a further reduction in the minimum size of the element, it is also possible to form the relief of the electrodes, for example, using printing technology. This printing technology can be implemented on the basis of the so-called nanomachine, which is developing at the present time. It is assumed that this method can be obtained, for example, bump electrodes with a minimum feature size down to 10 nm and even less, with comparable values of film thickness. Thus, it will be possible to create a relief on a scale comparable with the length of the channel, which is achievable in a way consistent with the present invention.

Furthermore, the method corresponding to the present invention, could, with appropriate selection of the additional steps further processing or additional intermediate stages, to allow manufacturing on the same substrate of a more complex circuit structure. Indeed, it provides the ability to choose the appropriate type conductivity and the calculated dimensions and use it for the manufacture of non-standard field-effect transistors of a special type. In addition, there may be a deposition of additional intermediate layers, for example, for the manufacture of devices with a matrix address the corruption on the basis of a transistor or memory for the formation of the complementary transistor circuits. It is obvious, for example, that you can remove any parts of the transistor structures or transistor structure as a whole, for example, during etching, and replace them with various passive elements formed, for example, by thin-film technology, in particular, resistors or connecting lines, thus creating a more complex scheme that is fully integrated with the original transistor structures made in a way consistent with the present invention.

1. A method of manufacturing transistors with ultra-short channel length of, which includes the following steps:

a) precipitated conductive material on a substrate of semiconductor material,

b) conductive material to form the relief of the first parallel strip electrodes with a spacing defined by the relevant design rules, while leaving the exposed region of the substrate in the form of strips between the first electrodes

c) precipitated barrier layer covering the first electrodes up to the substrate,

d) is produced by doping the substrate in the open field,

e) precipitated conductive material over the doped regions of the substrate, forming a second parallel strip electrodes,

f) removing the barrier layer covering the first electronic the birth, leaving vertical channels, passing down to the undoped regions of the substrate between the first and second electrodes,

g) is produced by doping the substrate in the open areas of the lower part of the channels,

h) fill the channels of the barrier material,

i) removing the first electrode, leaving gaps between the second electrodes and the opening between them is the area of the substrate,

j) is produced by alloying the open areas of the substrate in the intervals from which you removed the first electrodes

k) precipitated conductive material at specified intervals to restore the first electrodes and thereby obtaining an electrode layer containing first and second parallel strip electrodes, essentially equal to the width of that border with alloy substrate and separated from each other by only a thin layer of barrier material, while depending on the dopants used during doping, the first electrodes to form source electrodes or drain, and the second electrodes, respectively, the electrodes of the drain or source of transistor structures,

1) precipitated insulating barrier layer over the electrodes and the separation barrier layers,

m) precipitated conductive material over the barrier layer and

n) on the specified form electroconductive the m material relief of parallel strip electrodes of the shutter, oriented transversely to the electrodes of the drain and source, thereby obtaining the matrix structures of field-effect transistors with very short channel length and arbitrarily large width of the channel defined by the width of the gate electrode.

2. The method according to claim 1, characterized in that the electrically conductive material is a metal.

3. The method according to claim 1, characterized in that as the electrically conductive material is chosen organic material, preferably a polymer or copolymer material.

4. The method according to claim 1, characterized in that the steps of forming pattern using photomicrography.

5. The method according to claim 1, characterized in that the steps of forming pattern using nelitografichesky tools.

6. The method according to claim 1, characterized in that the removal of the barrier layers and/or electrodes is performed by etching.

7. The method according to claim 1, characterized in that the formation of the thin film barrier layer is carried out by selective deposition.

8. The method according to claim 1, characterized in that the formation of the thin film barrier layer is carried out by spraying.

9. The method according to claim 1, wherein the relief forming performed by etching.

10. The method according to claim 1, characterized in that the material of the semiconductor substrate choose silicon.

11. JV the property according to claim 1, characterized in that for obtaining individual field-effect transistors or circuits containing more than one transistor of this type, the matrix transistor structures are divided into appropriate zones.



 

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SUBSTANCE: method includes following stages: precipitation of electric-conductive material on substrate of semiconductor material, forming of shape of first parallel band electrodes with step, determined by appropriate construction rules, while areas of substrate in form of stripes between first electrodes are left open, precipitation of barrier layer, covering first electrodes down to substrate, alloying of substrate in open areas, precipitation of electric-conductive material above alloyed areas of substrate with forming of second parallel band electrodes, removal of barrier layer, near which vertical channels are left, passing downwards to non-alloyed areas of substrate between first and second electrodes, alloying of substrate in open areas of lower portion of channels, filling channels with barrier material, removal of first electrodes, during which gaps between second electrodes are left and substrate areas are opened between them, alloying of open areas of substrate in gaps, from which first electrodes were removed, removal of electric-conductive material in said gaps for restoration of first electrodes and thus making an electrode layer, containing first and second parallel band electrodes of practically even width, which are adjacent to alloyed substrate and separated from each other only by thin layer of barrier material, while, dependent on alloying admixtures, used during alloying stages, first electrodes form source or discharge electrodes, and second electrodes - respectively discharge or source electrodes of transistor structures, precipitation of insulating barrier layer above electrodes and separating barrier layers. Precipitation of electric-conductive material above barrier layer and forming in said electric-conductive material of shape of parallel band valve electrodes, directed transversely to source and discharge electrodes, thus receiving structures matrix for field transistors with very short channel length and arbitrarily large width of channel, determined by width of valve electrode.

EFFECT: ultra-short channel length of produced transistors.

11 cl, 17 dwg

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2 cl, 1 dwg, 1 tbl, 5 ex

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