Pulse shaping device

FIELD: digital pulse engineering.

SUBSTANCE: proposed device that can be used for shaping output pulses of desired length for each of three events (power turn-on, detection of input-signal pulse skipping or hanging [stop of changing] when detection is enabled in response to signal from closing button, including chatter suppression) provides for shaping output pulse during power turn-on and can function as hardware watch timer enabling generation of output pulse in case of skipping or hanging of input signal pulse. Device has first and second resistors 1, 2, closing button 4, capacitor 5, logical follower 6, inverted pulse signal output, common bus, and power supply bus. In addition, device has third resistor 3, NAND gate 7, first and second AND gates 8, 9, power turn-on and push-button signal integrator 10, pulse detector 11, pulse signal input 12, and control input 13.

EFFECT: enlarged functional capabilities.

1 cl, 1 dwg

 

The invention relates to pulsed digital technology, is intended for generating output pulses of the desired duration for each of the three events (when the power is turned on, the signal from the trailing buttons bounce suppression, detection of pass or “freezing” (suspension of amendments) pulse input pulse signal, when the resolution of detection) and can be used, for example, as a device for pulse shaping system reset (RST)) microcontroller or microprocessor system (M-system) information processing and control hardware watchdog timer to restart the application program crashes” M-system, designed in accordance with the following principles [1]: software management, main information exchange, modular construction, and capacity of computing power.

Modern standard M-system contains a module device software management (UPA), the modules are functionally oriented controllers and modems for I / o information in the process of interaction of M-system with external objects (operator sensor event control object, devices, related systems and so on), the power supply unit and the system bus formed by the tire management (SHU, address (SHA) and data (SM), to exchange information between modules (functionally complete parts M-systems) in the process of its functioning [2, p.14, figure 1.1].

In the General case, the module UPA contains a stand-alone memory, for example a combined (RAM+ROM+CSU), the transmitter containing, for example, a microcontroller, a quartz resonator and two capacitor to ensure the functioning of the internal oscillator clock of the microcontroller [2, 63, Risa], the inner rail, and the inputs and outputs of SHU, the outputs SA and bi-directional SM highway system, the transceivers and the mains adapter for functionally oriented interfacing microcontroller with internal and systemic arteries, and a device for pulse shaping system reset (in [2] it is not shown) to control the transmitter upon the occurrence a series of events, such as switching on and switching off of the power supply circuit on the body of the button system reset.

When the power supply voltage EP apparatus for forming pulses generates a reset pulse RST, the duration of which (on the basis of the data presented, for example, in [3, pp. 27, 28]) can be estimated by the ratio

where ty90 MS - setup time voltage EP with an accuracy of about 10% after inclusion;

tRST050 MS - pulse width RST at the end of tydetermining the minimum value of the real duration of the RST pulse when the power supply voltage.

At the end of each pulse RST integral part of the M-system are in working condition (reset, initialized and tested under the control of the UPA), and then M-system generally performs the separation in time several management functions. These functions are typically implemented cyclically as interacting quasi parallel processes [2, p.18-34] on the time grid M-system with some elementary time interval, which is formed using the corresponding timer/counter of the microcontroller operating mode account internal impulses. During the operation of the M-system as a complex digital machine with rapid and constant memory are prone to failure, which leads, in particular, to “freeze” the application program of the UPA. In this regard, the watchdog timer (Watchdog) is becoming increasingly popular among manufacturers of microcontrollers. For example, the microcontroller AT89S8252 the watchdog timer when enabled, the hardware is initialized by writing to register WMCON code PS[2:0] timer period and WDTRST bit on/reset and is designed to generate a reset on the hardware level is e (WDTRST=1), if the application program performs uncontrolled actions, such as “hung” [2, s, 108].

However, the built-in microcontroller hardware and software watchdog timer, although useful, but in General does not completely eliminate the “freeze” M-system, because when you reset the microcontroller WDTRST bit because of the interference of the microcontroller and then interference may modify the initialization and “hang out”. In addition, when installing due to the noise in the PCON register bits PD (or IDL) control mode microparasite (or idling), the microcontroller hangs in General (or at the time of termination, or until the arrival of the pulse RST) [2, s, 95], and the exit microparasite can only be done by applying to the input of the active RST pulse of duration tRST1defined by the constraint

Thus, when building the model of the modern M-system of information processing is accepted with online access to the RESET button (RESET) and especially unattended reset only at power-up and access to the RESET button only during the debugging process - urgent task is a reliable automatic detection of “freezing” of the application UPA and restart. In this regard, the creation of a simple device for pulse shaping system, the aqueous effluent from reliable hardware detection “freezing” of the application UPA (for example, due to the discovery of pass or “freezing” of the pulses in the input pulse signal generated by the microcontroller software UPA as a function of time grid M-system with pulse frequency varying within certain limits) and pulse shaping reset to the required length (i.e. taking into account the constraints of type (1) when the system is powered on and the constraints of type (2) in the formation of pulses of the reset signal from the trailing buttons with suppression of chattering or when you see the “hang” of the application is an urgent technical problem.

The shapers as an integral part of modern electronic systems typically include devices designed to convert the input and/or internal signals - event with the appropriate parameters in the normalized amplitude and steepness of the fronts of the digital output pulse signals of the required duration to control the subsequent parts of the system [4, s-265].

It should be noted that on modern element base shapers as pulse digital device, it is preferable to develop using logic elements CMOS technology, compared to the TTL are more suitable for operation in pulsed devices with high input impedance, good for those who eratures stability, as well as the transfer characteristic close to the ideal [4, s].

From the point of view of the digital circuitry the proposed device belongs to “support” elements of digital components and devices [5 p.24-37], famous for pulse shaping are the following four groups of devices.

The first group includes the pulse shapers button with the elimination of contact bounce:

diagram eliminate contact bounce based flip-flop with asynchronous or synchronous reset inputs, and installation and SPST switch to the two positions [5, pp.118, RES:b or C];

- shaper pulses [6], containing RS-trigger, two JK flip-flop element And the input clock and the control, output, two resistors and a single-pole switch two position, the contacts of which are connected to the inputs of an RS flip-flop connected through resistors bus bias voltage, is designed to generate at the output of one clock pulse (or series of clock pulses) for each switch of the switch and the logical signal “1” or “0”) at the control input;

device to eliminate the effect of contact bounce [7]containing the switch, bus logic signals “0” and “1”, RS-trigger, direct connected to the inverted reset input of the trigger and its direct and inverted output is coupled to the switching contact of the switch, inverse input set trigger and its inverted output;

device suppress the bounce [8], which contains a closing button, three two resistor-capacitor D-flip-flop and the output, which is the direct output of the trigger;

diagram suppress the bounce button with one pair of contacts [9, p.55, 100 [:a, b, C] contains a button with one pair of contacts, two combinational element CMOS technology, two resistors, a capacitor and direct and inverted outputs;

diagram suppress contact bounce by using a Schmitt trigger [10, p.85, RES] contains a button with one pair of contacts, two resistors, a capacitor, output and Schmitt trigger whose output is the output;

diagram, use the one-shot to suppress contact bounce [10, 119, RES] contains a button with one pair of contacts, the resistor, the output and the one-shot whose output is the output device.

The second group includes the pulse shapers initial setup power-on:

diagram of the initial installation MC [3, p.27, RES] performs the function of multiplexer signals power-on and off the button and contains a button with one pair of contacts, two resistors, a capacitor and an output connected to the first terminals of the resistors and capacitor, the second terminal of which is connected to common bus driver connected to p the pout contact buttons, a second contact which is connected to the second output of the first resistor, the second terminal of the second resistor is connected to the bus power supply shaper;

the pulse shaper initial installation on power [10, s, RES] contains a resistor, a capacitor, a Schmitt trigger and an output connected through a Schmitt trigger with the first terminals of the resistor and capacitor, the second terminal of which is connected to common bus driver, the bus supply voltage which is connected to the second output resistor.

The third group includes the pulse shapers, eg a series of pulses, each of which is designed to generate at the output a digital signal “1” (or 0) in the presence (or absence) of an input sequence of pulses:

device for controlling the pulse sequence [11], containing the triggers control and memory, the three elements, three inputs of the three clock pulses, the input of the controlled sequence of pulses and the output, which is the inverted output of the trigger memory;

the pulse shaper, the envelopes of the series of pulses [12], which contains a reference frequency generator, two keys, two trigger, reversible counter, a pulse shaper, the input pulse train and the output being the output of the first trigger;

- driver signal envelope of the input is mulsow [10: p.116, the first (or second) version of the launch of the one-shot AHP on is explaining risk on pp.118] contains a one-shot with a restart, the input sequence of pulses connected to the direct (or inverse) input start the one-shot, and one output, which is the direct output of one-shot;

- driver signal envelope of the input signal triggers [10, s, RES] contains an element NOT two trigger input pulse, which is connected through the element is NOT inverted asynchronous reset inputs of both triggers, the information input of the first of which is connected to the bus logic “1” shaper and inverse asynchronous inputs the settings of the two triggers, a clock input connected to the state clock inputs of both triggers, and output, which is the inverted output of the second trigger, an information input connected to the output of the first trigger.

The fourth group related device for detecting loss of momentum [13], designed for generation of output pulses when the loss of the input pulses.

Based on the above auxiliary devices of the first, second and third (or fourth) groups can build a device with the features offered. However, such a device will repeat the shortcomings of its component parts, which are narrow specialization or limited to the ity of their functionality and hardware complexity when using them to build devices for pulse shaping system reset of the modern M-system.

A device [8] suppress the bounce, containing a closing button, the trigger CMOS technology, a direct output which is the output of the device, three resistors, two capacitor bus supply voltage connected through the first resistor to the first output of the first capacitor and the first button contact, a second contact which is connected to the first output of the second resistor and synchronator trigger inverted output of which is connected through a third resistor with the information input trigger and the first output of the second capacitor, the second terminal of which is connected to the second pins of the first capacitor and the second resistor and a shared bus device.

In the initial state, the button is open, the trigger is in the state X=0 (or 1), the first capacitor is charged up to a voltage UC1=EP, engraved trigger is in the state of logical “0” (engraved through the second resistor is connected with a common bus), and the information input trigger is in the state (NX where NX is the inverse of X) and the second capacitor is charged up to a voltage UC2≈ EP (ili) at X=0 (or 1). By clicking on synchroscope trigger generates multiple pulses of contact bounce during the time of bounce tdrop=1-10 MS [5, s]).

On the first edge of the first pulse bounce the trigger enters the opposite state, about what onanii bounce first capacitor discharges until the voltage UC1≈ 0, and the second capacitor is charged to a voltage UC2≈ 0 In (or EP) at X=1 (or X=0). When the button is released it bounce does not affect the state of the trigger, because the first capacitor is discharged to 0 V, and at the end of the bounce of the first capacitor through the first resistance is charged to the source voltage UC1=EN. Thus, this device operates so that each button is pressed, the trigger enters the opposite state.

The main drawback of the device [8] is that it is relative hardware complexity performs only the function of the one-bit counter presses a button and it does not provide the function of forming a single pulse when switching supply. This limits the use of such technical solutions as even the simplest of devices forming pulses reset when creating the modern M-system.

A device [13], which contains two elements, And the delay element, the element is NOT, the regenerator pulse sequence (formed by series-connected element OR that element of the delay and the driver, perform the function of shortening the input signal in duration), OR a counter, a decoder, the inputs of which are connected to the outputs of the counter, the reset input of which is connected to the output of the first cell battery (included) is that, the inputs of which are connected to the outputs of the delay elements and element OR the input pulse sequence, which is connected with the first inputs of the regenerator and the OR element and is connected through the element, NOT to the first input of the second element And a second input connected to the input of the delay element and the output of the regenerator, the first pulse output connected to the output of the second element And the second input of the regenerator and counter input counter and the second pulse output which is the output of the decoder, which is connected to the second input of the OR element.

In the initial state, the counter is reset each input pulse with delay and shortening takes place at the exit of the regenerator and through the element does NOT prevent the second element And, in the event of a loss of momentum in the input sequence, the second element And passes the pulse from the output of the regenerator, i.e. generates a first output pulse corresponding to the lost. These pulses are counted by the counter and, if the number of skipped pulses reaches a threshold, then the decoder on the second output device generates a pulse through the OR element and the first element And resets the counter to the zero state.

The main drawback of the device [13] is that it is with considerable hardware complexity has limited capabilities when performing their function is, as it does not detect the loss of pulses during the “hang” of a single input device, as in this case, the output element OR the regenerator is formed of a permanent individual signal blocking regeneration.

Known technical solutions closest to the proposed principle of generating output pulses from the line-up is the device [14], which contains two resistors, the first output of the first of which is connected to the bus power supply device, a capacitor, a logical repeater CMOS technology (formed by two elements is NOT, the first of which is the input of the repeater, the output of which is the output of the second element, the input connected to the output of the first element), a closing button, the first contact which is connected to a shared bus device and the inverted output pulse signal connected to the output of the repeater and the first the output capacitor, the second terminal of which is connected to the input of the repeater and the first output of the second resistor, the second terminal of which is connected to the second contact button and the second output of the first resistor.

During operation of the device at the input of the repeater generates the voltage IU=UC+OU (where UC is the voltage on the capacitor, measured at the second output relative to its first output; OU - voltage is at the output of the repeater), and in the initial state when not pressed IU≈ Tu and OU≈ EP, which define an inverted digital signals INX=1 and ONX=1 at the input and output of the repeater, respectively. Thus, when not pressed, the device is zero in steady state (NUS) NUS={IU≈ Tu, UC≈ 0, U≈ Tu, INX=1, ONX=1}. When the button is pressed, the capacitor and the second resistor form shorten the circuit (output circuit connected to the input of the repeater and the input to the output of the repeater) and IU voltage begins to decrease as the capacitor begins to charge from the voltage U≈ EP via a second resistor and a loop button. If the time constant C· R2, where R2 and the capacitance of the capacitor and the resistance of the second resistor, respectively, is chosen large enough, then decreasing IU voltage reaches the threshold U(-) switch to the repeater from “1” to “0” after the termination of the bounce button in the circuit. At the moment IU(t)=U(-)≈ EP/2 repeater is in the area of amplification negative increment dIU(t)=IU(t)-U(-). So pop a negative increment dIU(t) causes increased tension OU that through the capacitor in the loop positive feedback causes, as in the Schmitt trigger, the abrupt change in voltage from OU OU≈ EP up OU≈ 0 with the transfer device in a single transition state (ENP)

ENP={U≈ UC≈ -EP/2, OU≈ 0 V, INX=0, ONX=0},

since (according to the first law of commutation [15, 20]) for any nite current, charging or discharge the capacitor, the voltage across it leap cannot be altered. Then after about time

T=3· [IR(-)+OR]

the capacitor is almost discharged, and the device enters a single steady state (EOS)

EUS={IU≈ UC≈ OU≈ 0 V, INX=0, ONX=0}, where

IR(-) - input internal protective impedance input of the repeater from the negative voltage IU<0 In;

OR - output internal resistance of the repeater.

When the button is released the serial connection of the first and second resistors (i.e., the resistor R with resistance R=R1+R2) and the capacitor form an integrating circuit (output circuit connected to the input of the repeater, and the entrance to the supply voltage EP) and the IU voltage begins to increase as the capacitor begins to charge from the voltage EP R open button. Since the time constant (C· R)>(C· R2), then increasing the voltage IU reaches the threshold U(+) switching repeater from “0” to “1” after the termination of the bounce button when open. At the moment IU(t)=U(+)≈ EP/2 repeater is in the area of strengthening positive increment dIU(t)=IU(t)-U(+). So that appears positive increment dIU(t) causes increased voltage increase OU to the / establishment, which through the capacitor in the loop positive feedback causes, as in Schmitt trigger, the abrupt change in voltage from OU OU≈ 0 V to OU≈ Tu with transition device in accordance with the first law of commutation, in the zero transition state (PS)

OPS={IU≈ Tu/2+Tu, UC≈ +EP/2, OU≈ Tu, INX=1, ONX=1},

and then after approximately time T=3· [IR(+)+OR] in the NCA is not pressed, where IR(+) - input internal protective resistance of the repeater from the input positive voltage IU>MB.

Thus, during operation of the device [14] with the elimination of chattering repeats the position of the button so that at its output when the button is formed of a digital inverse impulse ONX=0, the duration of which corresponds to the time of contact closure button, and the cut-off (switching from “1” to “0”) and front (switching from “0” to “1”) detained respectively, relative to the circuit and breaking of the contacts of the button.

The main drawback of the device [14] when applied, for example, to build the modern M-system information processing and management is limited functionality, for example it does not generate an output pulse when the power is turned on, and performs only the function of forming inverted output digital pulse ONX, which models the state of the button with the elimination of chattering.

The invention solves C the dacha complex functionality of the device due to the formation of the output pulse at power-up taking into account the constraints (1) and can be run on the device hardware watchdog timer when the resolution of formation of the output pulse taking into account the constraints (2) when skipping or “freeze” of the pulses of the input pulse signal input to the device, for example, from the microcontroller M-systems information processing and management.

To achieve this, the technical result in the apparatus for forming a pulse containing the first and second resistors, a closing button, the first contact which is connected to a shared bus device, the capacitor, the logical repeater CMOS technology, the bus voltage and the inverted output pulse signal connected to the output of the repeater and the first output capacitor entered the third resistor element AND the first and second elements And a combiner of signals on power and buttons, the first, second and third inputs of which are respectively connected to the bus voltage, the common bus and the second contact button, the detector pulse, pulse and setting the inputs of which are respectively connected to the outputs of the first and second elements, And the output of the detector is connected to the first output of the first resistor, the second terminal of which is connected to the second lead of the capacitor and the first output of the second resistor, the second terminal of which is connected to the input of the repeater, the input pulse signal, which is the first the m input of the first element And and the control input, which is connected through a third resistor to the bus voltage and the first input element AND IS NOT, a second input connected to the output of the shaper and the output element AND IS NOT connected to the first input of the second element And a second input connected to the second input of the first element And the output of the combiner.

Author unknown solutions containing characteristics equivalent to distinctive features (the introduction of the third resistor element AND-NOT two elements, the unifier signals power-on and off the button, the detector pulses of the input pulse signal and the control input) of the proposed device, which (compared with the prototype [14]) comprehensively extend the functionality of the device by generating a pulse at power-up and enable the execution device function hardware watchdog input pulse signal when the resolution of formation of the output pulse skipping or “freeze” of the pulses in the input pulse the signal received at the device, for example, from the microcontroller served or unserved M-system.

The drawing shows a functional diagram of the device for pulse shaping, containing three resistor 1-3, a closing button 4,the first contact which is connected to a shared bus device, the capacitor 5, the logical repeater 6 CMOS technology (made, for example, as an element, And the inputs of which are combined and are used as inputs of the repeater 6), bus voltage, the element 7 AND IS NOT, the first 8 and second 9 elements And a multiplexer 10 signals on power and buttons, the first, second and third inputs of which are respectively connected to the bus voltage, the common bus and the second contact button 4, the detector 11 pulses, pulse and setting the inputs of which are respectively connected to the outputs of the first 8 and second 9 elements, And the output the detector 11 is connected to the first output of the first resistor 1, the inverted output pulse signal connected to the output of the repeater 6 and the first output capacitor 5, the second terminal of which is connected to the second output of the first resistor 1 and the first output of the second resistor 2, the second terminal of which is connected to the input of the repeater 6, entry 12 pulse signal, which is the first input of the first element 8, And the control input 13, which is connected through the third resistor 3 bus supply voltage and the first input element 7 AND IS NOT, a second input connected to the output device and the output element 7 AND IS NOT connected to the first input of the second element 9 And a second input connected to the second input of the first element 8 And the output of the combiner 10.

The possibility of the hydrated version of the combiner 10 signals on power-up and button contains resistors 14-16, the capacitor 17, the element 18 And CMOS technology, the first input connected to the first terminals of the resistors 14 and 15, a second input connected to the first output capacitor 17, the second terminal of which is connected to the second output of the resistor 14 and the first output resistor 16, the second terminal of which is connected to the first input element 18 And a third input connected to the second output of the resistor 15 and the second input element 18, and the output, which is the output element 18 I.

It should be noted that when possible, use the import element base as a unifier 10 currently, it is advisable to use the chip type DS1233D-10 firm DALLAS Semicodactor, which is the driver of the inverse reset signal when the voltage deviation from nominal at +5 C. This deviation is in the range from 4.25 per to 4.49 In, and the chip includes a voltage divider with stable parameters in the operating temperature range (Vcc TOLERANCE AND BIAS), the voltage reference (I.E. REFERENCE), the comparator delay element (350 ms DELAY), a resistor, a MOS transistor, the input voltage connected with the first output resistor and is connected through a voltage divider with non-inverting input of the comparator inverting input connected to the output of the reference voltage, the input bus connected to the drain of the transistor, and the inverted output pulse is, connected to the second output resistor and a source of the transistor, the gate through which the delay element is connected with the comparator output.

Chip DS1233D-10 operates in the temperature range from -40° to +85° so that when the power supply voltage EP≤ 7 produces at the output the inverse of the reset pulse NRST=0 duration tRST0=250-450 MS, and then switches to “1” and continuously monitors the voltage level of the EP: the comparator compares the output voltage of the divider with a reference voltage of the reference voltage and through a delay element controls the state of the key - MOSFET. When injected voltage EP to the corresponding point of the range from 4.25 per to 4.49 In the signal NRST output chip switches from “1” to “0” for a time not greater than 100 NS, at the time, the duration of which is not less than tRST0=250-450 MS.

By using chips DS1233D-10 as a unifier 10 of its inputs connected to the bus voltage and the common bus, and the output of the chip is the output of the multiplexer 10, which is connected with the second contact buttons 4 and second inputs of the elements 8 and 9.

The detector 11 pulses can be implemented based on any of the previously mentioned devices of the third group (i.e. the pulse shaper, the envelopes of the series of pulses), and one of the possible variants of the detector 11 with the holding capacitors 19 and 20, the diodes 21, 22 and 23, resistors 24, 25 and 26, a pulse input connected to the first output capacitor 19, the second terminal of which is connected through a resistor 24 to the cathode of the diode 21 and the anode of diode 22, the input set, which is connected through resistor 25 to the anode of diode 23, and the output connected to the cathodes of the diodes 22 and 23 and the first terminals of the capacitor 20 and resistor 26, the latter findings are connected to the anode of diode 21 and a common bus.

The logical elements of the device are made in CMOS integrated circuits series 1554 (repeater 6 and the elements 8, 9 and 18 are implemented on a single chip LI1, containing four element 2, And element 7 AND is 0.25 chip MANHOLE containing four elements 2I-NOT), operating in the temperature range from -45° to +85° with a supply voltage EP from +2 to +6 V At a constant current at each output up to 24 mA input current for each input from -1 to +1 µa - see, for example, [16, p.15, p.21 table 3.1]. Also [16, p.16], chip series 1554 able to work with an output current of 75 mA and the output voltage is not less of 3.85 V At EP =5.5 V on the bus with an impedance of Zo=50 Ohm.

As diodes 21-23 detector 11 can be used, for example, diodes type DB or three of the eight diodes diode matrix DA.

Further description of the operation of the device is conducted using the terms, designations and settlement ratios, defined the in the following paragraphs.

1. When building containing devices, integrating (or decrease) the RC circuit, connected the output to the input of logic element associated with its output through the positive feedback circuit, the challenge is to estimate the response time of TCP. logic element when the signal change at the input circuit to 0 V to supply voltage EP or Vice versa from the EP to 0 C. the Time Tavg. is determined by the time constant T=C· R circuit and the threshold logic element, for which a CMOS element is close to half of the voltage EP power [9, p.58].

We denote the input logical repeater 6 (or on the first input element 18) thresholds trigger to enable or disable through U(+) U ( -), respectively, and

where dUy is a small interval of the voltage U(+) to U(-), in which the repeater 6 (or 18) is reinvestiruet amplifier input voltage changes with gain, many large units.

According to [15, 67, 68] and the proximity threshold (4) or (5) to the value of EP/2, the response time of TCP. is estimated by the formula

decisive for integrating (or decrease) circuit modification time of the output signal of the circuit from an initial level to a level which leaves half of the abrupt change in the input signal (or the active duration of the output pulse shorten the chain, measured at the level of half the amplitude).

2. Modified the description language of logic functions ABEL, in which the operators “And” and “NOT” are designated as “&” and “!” (or “N”), respectively.

3. The voltage between the second and first terminals of the resistor 1 denote by UR1, and the voltage on the capacitors 5, 17, 19 and 20 denote, respectively, by UC5, UC17, UC19 and UC20, and UC5 (or UC19) is measured on the second terminal of the capacitor 5 (19) relative to its first output, UC17 - on the second terminal of the capacitor 17 with respect to its first output connected to the common bus, UC20 - on the first terminal of the capacitor 20 relative to second its output connected to the common bus.

The digital signals at the inputs 12, 13, the connection point between the resistors 1, 2 and the capacitor 5 and the signals at the outputs of the elements 6, 7, 8, 9, and 18 denote by H, H, NIR2 and NOX6, NOX7, H, OH and NOX18, and the corresponding analog voltage denote by U12, U13, UIR2 and U6, U7, U8, U9 and U18 respectively, where a value of “0” or “1” of any digital signal is an analog voltage “≈ 0 In (UIR2<U(+)) or “≈ EP (UIR2>U(-)) respectively.

4. We denote the resistors 1-3, 14-16, 24-26 and capacitance of the capacitors 5, 17, 19 and 20 through R1-R3, R14-R16, R24-R26 and C5, C17, C19 and C20, respectively.

The resistor 2 (or 16) is designed to limit the discharge of the first capacitor 5 (or 14), flowing through protective diodes to the inputs of the element 6 And the repeater 6 (or the protective diode of the first input element 18 And the resistor 2 (or 16) at the beginning or end of the output pulse NOX6=0 (or when you turn off the power supply). The resistance of these resistors are chosen to be equal to R2=R16=300 Ω taking into account [16, 20, Fig. 3.12] protection schemes of electric discharge through the organization of input and output circuits CR with a protective pair of diodes on each input and output [16, s, is].

The resistors 24 and 25 are designed to limit the pulse current elements 8 and 9 respectively. The resistance of these resistors is chosen equal R24=R25=51 Ohms.

When not pressed button 4 to the second input element 18 is served logical signal “1” by connecting this input to the supply voltage through the resistor 15, the impedance of which is chosen equal to R15=2 kω.

Input 13 is technological (used only when debugging M-system from the stand), and in normal system mode input 13 is open and is able H=1 by connecting it to the supply voltage through the resistor 3, the resistance of which is chosen equal to R3=2 kω.

5. 8, the capacitor 19 and the diodes 21 and 22 are used only when the device is in the mode of the watchdog timer with the monitoring of the behavior in time of the input pulses H. At the steady state supply voltage EP is not pressed button 4 this mode is on OH=H when H=1 and the input 12 of the sequence of pulses H with the period T12=T+T, so H=0 (or 1) for T (or T).

6. Unifier 10 operates so that in it the element 18 And performs the logical function of an Association OR an inverse of the signal on power-up and down buttons 4 and generates an inverted output signal NOX18=0 when the power supply voltage EP, but after establishing a voltage EP at the output of element 18 is repeated digital position signal button 4, namely NOX18=1 and NOX18=0 when not pressed and the pressed button 4, respectively.

7. Using approved symbols of the logical operation elements 6-9 device described by the following formulas:

where the voltage UIR2 is determined by the formula

moreover, the monotonic change (increase to U(+) or reduction to U(-)) voltage UIR2(t) in the loop of positive feedback from the output voltage U6 through the capacitor C5 and the resistor 2 in the Schmitt trigger causes an abrupt switching of the digital signal NOX6 repeater 6 or from “0” to “1” when reaching the threshold U(+) when ascending or from “1” to “0” when reaching the threshold U(-) when the mind is icenii.

8. Under the front or cut any digital signal (direct or inverse) is the change of the logical state of the signal from “0” to “1” or from “1” to “0”, respectively.

Based on the above describe sequentially the operation of the device at the occurrence of each of the following three events: the power supply, the circuit button 4 with the subsequent opening operation, the detection of pass or “freezing” of the input pulse signal H when H=1, allows the operation of the device in the mode of the watchdog timer for the input pulse signal H.

Before turning on the power EP=UC5=UC17=UC19=UC20=0 and button 4 is open. With the power supply in a few tens of milliseconds while achieving the EP>2 In UC17<U(+) items 6-9, 18 begin to operate steadily and the device in NOX18=0 is recorded in accordance with expressions (7)-(12) in a single steady state power (AUSIT)

at time tOnthat is according to expression (6) is estimated by the expression

Over time (15) the capacitor 17 through the resistor 14 is charged to a voltage UC17=U(+) and the element 18 is in the area of dUy (5), in which he is reinvestiruet amplifier to increase the input voltage UC17 to gain a lot of Bo is isim units. Through time

transition zone dUy (5) the capacitor C17 is charged to a voltage UC17> U(-), in which the element 18 is stably produces an output signal NOX18=1. Digital signals NOX7=1 and NOX18=1 element 9 generates a digital signal OG=1, the voltage U9≈ EP which through the diode 23 quickly charging the capacitor 20 to a voltage UC20≈ Tu and the device is in a single transition state (ENP)

about the time

Over time (18) the capacitor 5, the voltage UC20≈ EP through the resistor 1 is charged to a voltage UC5≈ U(+) and UIR2=U(+) element 6 is in the area of dUy (5) strengthening further the positive increment of voltage UIR2 with gain, much larger units. This causes the positive feedback loop (through the capacitor 5 and the resistor 2) the closure of the output signal of the element 6 at its input and avalanche switching signal NOX6 from “0” to “1” transition of the device in the zero transition state (PS)

Thus, whenever the power output of the device is formed inverse impulse NOX6=0, the duration of which, taking into account the constraints (1), is estimated by the ratio

At the end of this pulse is Lisa about a time

the capacitor C5 is discharged, and when H=0 or when input 12 pulse signal H with the period T12, satisfying the condition detection pulses H (will be defined below), the device enters a zero steady state (NUS) unpressed button 4

If the device is in the NCA (22), then each time you press the button 4 it works as follows.

When the 4 button is pressed on the output element 18, a signal is generated NOX18 that repeats the digital position signal button 4, the duration of time tdropbounce which, according to [5, s] taking into account the expression (18), is determined by the ratio

After pressing 4 over time (23) the elements 18, 8 and 9 produce digital signals NOX18=OH=OH=0, the outputs of the elements 8 and 9 are produced voltage U8≈ U9≈ 0, the diodes 22 and 23 are closed, and the device goes to zero transition state of the pressed button (NPSN)

duration T which is estimated by the expression

The operation of the device in the condition (24) for T is the discharge of the capacitor C20 from voltage UC20(t=0)≈ Tu and the charge of the capacitor UC5(t=0)≈ 0 In such quantities that in time T monotonously voltage UIR2 reaches the threshold U(-)=UIR2=(UC20+UR1)=(UC5+U6)≈ (UC5+EP). Further, a continuous decrease of the voltage UIR2 through resistor R2 to the inputs is perceived by the follower 6 and causes its output an amplified voltage decreases U6. Started reduction of U6 in the loop of positive feedback through the capacitor C5 and the resistor R2 is transmitted to the inputs of the repeater 6 and causes an abrupt process of switching signal NOX6 from “1” to “0”and the device goes into a single transition state of the pressed button (EPSRC)

Since U8=U9≈ 0 B, then the operation of the device in the condition (26) is to discharge the capacitors 5 and 20. This process ends with a transfer device in a single stable state of the pressed button (EPNK)

When the button is released after time tdrop(23) the element 18 generates a digital signal NX18=1, and the device then functions as previously described transition when the power is turned on after the formation of the element 9 digital signal OG=1, namely, the voltage U9≈ EP through the diode 23 quickly charging the capacitor 20 to a voltage UC20≈ Tu, through which the device is sequentially transferred in the ENP (17) about the time T (18), PS (19) around time tbit5 (21) and NUSA (22), which is the original.

If the device is in the NCA (22), then p and H=NOX18=1 it is translated into the mode of the watchdog timer with the observation of the behavior in time of the input pulse signal H, a certain period T12=T+T repetition rate of his pulse.

Pulses H through the element 8 receives the pulse input of the detector 11 in the form of voltage pulses U8 such that during T (or T) voltage U8≈ 0 In (or EP). Therefore, from the beginning of each front signal H over time

the voltage U8≈ EP is the charge of the capacitors 19 and 20 via a resistor (R24+Rd) respectively to voltages UC19 and UC20 defined by the expression

where

Rd≈ (10-1000) Ω is the differential resistance of the diode 22;

UC20(t=0) - voltage UC20 at the time of the pulse H;

UD22≈ 0.2 V - voltage on the open diode 22 at the end of TK(28).

With the beginning of each recession signal at the input 12 (i.e. at U8≈ 0 and U9≈ 0) over time T there is a discharge of the capacitor 19 to approximately 0 V, and over time (T12-TK) be a discharge of the capacitor 20 voltage from (30) and changing (dynamic increase and decrease) the voltage UC5 through a resistance of 1 from the difference voltage [UC20(t)-U6])≈ [UC20(t)-Tu] with trend tracking voltage UIR2(t) (13) for changing the voltage UC20(t), which in each period T12 for the first time TK (28) is increasing, then for (T12-TK) is reduced. Voltage UIR2(t) at the OBN is royenii at the input 12 of the pulse signal H is always greater than the threshold U(-), and when UIR2(t)=U(-) the device detects the failure of one pulse in the input sequence X (or “hang”), marked by the formation of one pulse NOX6=0 (or transfer device mode oscillator) with the formation of the element 9 element 7 single signal OG=1 (i.e. the voltage U9≈ EP) installation of the detector 11 through the resistor 25 and diode 23 in the initial state UC20≈ EP detection pulse signal H.

Using expressions (7)to(13) above (see expression(25), (28)-(30)) formally describes the operation of the detector 11 pulse signal H at the input 12, the condition detection pulses OH=H is the ratio

and the condition detection failure or a freezing pulse H=H is the value.

From(25), (28)-(32) it follows that the stable operation of the device in the mode of the watchdog timer with the tracking pulse signal at the input 12 may be provided with a choice of values (T12-TK) and C19 with stock-based expressions

Given the above-mentioned operation mode of watchdog timer (observation of behavior in time of the pulses OH=H when IX13=NOX18=1), starting from some point in time of the well is of avago dynamic state of the detection pulses (NDSO)

can be described as follows.

With the beginning of each front signal OH=H during the time TK (28) voltage U8≈ En is the charge of the capacitors 19 and 20 via a resistor (R24+Rd) to stress UC19 (29) and UC20 (30), respectively. Then with the beginning of each recession signal OF over time T at U8≈ 0 occurs In the discharge of the capacitor 19 to approximately 0 V, and the discharge of the capacitor 20 from the initial voltage (30) occurs over time (T12-TK), i.e. during most of the period T12 of the pulse repetition rate OF=H. The change in voltage UIR2 occurs continuously with the tracking voltage UC20>U(-) for TK, and (T12-TK). In this regard, in this mode, the current value of the voltage UIR2(t) depending on time (T12-TK) is perceived by the inputs of the repeater 6 if the condition in (31) detection pulses OH=H as digital signal NIR2=1 (i.e. UIR2(t)>U(-))and if the condition (32) discovery pass (or “freezing”) of pulses OH=H, then at some point in time, the voltage UIR2(t) is reduced to the threshold voltage U(-), and through the capacitor 5 and the resistor 2 closed loop positive feedback signal NOX6 switches from “1” to “0”, and the device moves during T (18) in one state generators is tion (UGSS)

During the time T voltage UIR2(t) continuously increases due to the charge of the capacitor C5 from the voltage (UC20-U6)≈ EP through resistor 1, and at t=T6.1 voltage UIR2(t) becomes equal to U(+). Further increase in voltage UIR2(t) by the chain of positive feedback through the capacitor 5 and the resistor 2 causes the switching of the output signal ONX6 from “0” to “1” and return the device to NDSO (35). Further operation of the device is determined by the behavior of the signal H=H as a function of time, and when the “freeze” signal H (i.e. at a constant time signal H=0 or H=1) the device enters the mode of the oscillator. Mode oscillator is implemented as a rotation around the ring described processes of formation NOX6=0 for T and NOX6=1 for T, and

in accordance with the expressions (2), (18) and (25).

M-system output signal ONX6=0 perceives as the inverse of the reset pulse NRST=0, after which it is initialized, tested, and starts to perform its functions. After or during the initialization of the microcontroller UPA should start to programmatically generate a pulse signal H according to the constraint (33) to support the operation of the device in NDSO (35) when H=1. When the correct functioning of the UPA period T12 frequency is ladouanie pulses H must satisfy the conditions (31) and (33) reliable detection pulses OH=H the detector 11.

When H=0 mode the watchdog timer is disabled. This allows M-system debugging function, emulator MCU in step mode.

Directly from the description of the prototype [14] and this device is that, compared with the prototype of the proposed device, thanks to its essential features, has significantly enhanced due to the formation of the output pulse at power-up taking into account the constraints (1), implemented in the form of constraints (20)and enable (if H=1) run the device features a hardware watchdog timer, allowing you to “hang” M-system generating the output pulse taking into account the constraints (2), implemented in the form of constraints (18).

Literature

1. Oscar mathematical SCIENCES. Microprocessor devices in electronic equipment, Ed. Bravisimo - M.: Radio and communication, 1988. - 128. “The principles of microprocessors”, pp.5-12.

2. Brodin V.B. have been, Kalinin A.V. Systems on microcontrollers and BIS programmable logic. - M.: Publishing house ECOM, 2002 - 400 C.

3. Stalin CENTURIES and other digital devices Design on single-chip microcontrollers/ Tin, Avenoso, Ofemergency. - M.: Energoatomizdat, 1990. - 224 S.

4. Zeldin E.A. Digital integrated circuits and the data-measuring technique. HP: Energoatomizdat. Leningrad. separa-tion. 1986. - 280 S. “Impulse devices on a chip” - s-276.

5. Ugryumov, H.E. Digital circuitry. - SPb.: BHV-Petersburg, 2001. - 528 S.

6. A.S. No. 725209, N 03 To 3/78, USSR. The pulse shaper/ Wastediv. - Publ. 1980. Bull. No. 12.

7. A.S. No. 731562, N 03 To 3/286, USSR. Device to eliminate the effect of contact bounce/ Whakatutuki. - Publ. 1980. Bull. No. 16.

8. A.S. No. 1132353, N 03 To 5/01, USSR. The device suppress the bounce/ Ubogoe. - Publ. 1984. Bull. No. 48.

9. Biryukov S.A. Digital devices in MOS integrated circuits. - M.: Radio and communication, 1990. - 128 S.

10. Novikov YU.V. fundamentals of digital circuitry. Basic elements and circuits. Design methods. - M.: Mir, 2001. - 379 S. (Modern circuitry).

11. A.S. No. 599341, N 03 To 5/18. Device for controlling the sequence of pulses/ Vmichael and Maindroni. - Publ. 1978. Bulletin no.11.

12. A.S. No. 1020986, N 03 To 5/156, USSR. The pulse shaper, the envelopes of the series of pulses/ Amember and Equasion. - Publ. 1983. Bulletin no.20.

13. A.S. No. 1157670, N 03 To 5/13, 5/19, USSR. Device for detecting loss of momentum/ Abic and Astrakhanskiy. - Publ. 1985. Bulletin no.19.

14. Suppression of chattering the buttons with one pair of contacts - p.55, rise - delay on and off. In the book: Biryukov S.A. Digital devices in MOS integrated circuits. - M.: Radio and communication, 1990. - 128 S. the Prototype.

15. Erofeev YU. Impulse devices: Textbook. Manual for schools on special. “Radio engineering”. - M: The High. SHK. 1989. - 527 S.

16. ISi, Averille, Tan, Vstupali. Logical IP CR, CR. The Handbook. In two parts. Part 1. LLP “BINOM”, 1993. - 254 S.

Apparatus for forming pulses containing the first and second resistors, a closing button, the first contact which is connected to a shared bus device, the capacitor, the logical repeater CMOS technology, the bus voltage and the inverted output pulse signal connected to the output of the repeater and the first output capacitor, characterized in that it includes a third resistor element AND the first and second elements And a combiner of signals on power and buttons, the first, second and third inputs of which are respectively connected to the bus voltage, the common bus and the second contact button, the detector pulses pulse and setting the inputs of which are respectively connected to the outputs of the first and second elements, And the output of the detector is connected to the first output of the first resistor, the second terminal of which is connected to the second lead of the capacitor and the first output of the second resistor, the second terminal of which is connected to the input of the repeater, the input pulse signal, which is the first input of the first element And the control input, is connected through a third resistor to the bus voltage and the first input element AND-NOT a second input connected to the output device and the output element AND IS NOT connected to the first input of the second element And a second input connected to the second input of the first element And the output of the combiner.



 

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