Group delay time measuring unit

FIELD: measurement technology.

SUBSTANCE: measuring unit is used for measuring time shifts between output and input signals induced in real four-terminal networks, for example, in amplifiers of audio signals. Measuring unit can be used for measuring as random signals and determined monoharmonic signals. Measuring unit has two extremum selection units which have outputs connected with inputs of time shift measuring unit. Inputs of extremum selection unit have to be inputs of measuring unit. Measurement of time shifts between extreme of output and input signals allows to eliminate errors caused by shifts in signal zero line in four-terminal network and influence of non-linear distortions on shape of output signal.

EFFECT: reduced errors; reduced influence of non-linear distortions.

2 cl, 3 dwg

 

The invention relates to the field of radio and can be used for measuring a time offset that occurs in the real two-ports, such as audio amplifiers, between output and input signals, bearing both random and deterministic managementcase.

As a prototype, as the closest to the technical essence, the classic meter (phase meter)used to estimate the relative time shifts in the amplifying devices and contains two pulse shaper, block allocation time interval and the unit of measurement of time shifts, the output of which is the output of the meter, the delayed input signal is the input of the first driver, input-ahead signal is the input of the second driver, the outputs of the first and second shapers connected respectively to first and second inputs of the block selection time interval, the outputs of which are connected to the inputs of the unit of measurement of time shifts [Electric dimension / edited Aphreme and Emosia. - 5th ed., revised and enlarged extra - L.: Energy, 1980, str-244, Fig. 6.19 a, b].

In the prototype implemented widely known method of measuring the phase shift and group delay time based on the selection of the points of intersection signals zero line izmerenii time offset between the specified points the reference time stamp. To a significant shortcoming of the method and device, its implementing, should include the error due to not quite correct positioning timestamps of the same points as the input and output signals, between which and then measure the temporal delay. So, when you change the position of the zero line of the output signal generated by the above timestamps will also be displaced, which will lead to errors in the measurement of the time difference, and hence the group delay time. Moreover, the zero line is not only the amps DC or video amplifier, but in amps AC, such as audio amplifiers, as to such effect leads and a non-linear transformation with subsequent alignment (that is what happens in real amplifiers). At the nonlinear transformation in the spectrum of the output signal appears constant component, after removal of the resulting process at the load is shifted along the ordinate axis so that the area under the different half-waves was equal to - this leads to a shift in time moments form the timestamps. As a result, the increase of harmonic distortion increases the measurement error group delay time. Given that distortion usually increases the amplitude of the input signal, the estimate of the required time delay will also depend on the amplitude of the input signal, while the true value of group delay time is not changed.

Technical result achieved when using the present invention mainly consists in increasing the accuracy of the estimated group delay time at offset zero line and nonlinear distortions.

The technical result is achieved that the measuring group delay time, which includes the unit of measurement of time shifts, the output of which is the output of the measuring instrument according to the invention introduced two unit selection extremum, the input of the first of them is the delayed input signal, the input of the second block selection extremum is a sign of an advanced signal, the outputs of the first and second allocation unit extremum connected respectively to first and second inputs of the unit of measurement of time shifts.

To achieve a technical result, the block selection extremum contains analog-to-digital Converter, three cases, two comparator binary element And three delay elements, the information input of the analog-to-digital Converter serves as the input unit selection ekström is mA the output of which serves as the output element And the output of the analog-to-digital Converter connected to the information input of the first register, the output of which is connected to the information input of the second register, the output of which is connected to the information input of the third register, the output of the first register connected to the first input of the first comparator, the second input is connected to the output of the second register, the first input of the second comparator connected to the output of the third register and a second input of the second comparator is combined with the second input of the first comparator, the outputs of the first and second Comparators respectively connected to first and second inputs of the element, And a third input connected to the output of the first the delay element, the input of which is connected to the clock input of the block clock inputs of analog-to-digital Converter and the third register of the joint and also connected to the clock input unit, the clock input of the first register connected to the output of the second delay element, the input connected to the output of the third delay element, the input of which is connected to the clock input unit, the clock input of the second register is connected to the output of the third delay element.

The invention is illustrated graphic material. Figure 1 shows the functional diagram of the gauge group time sapas is ivania connected with the test amplifier. Figure 2 shows time diagrams explaining the principle of measurement. Figure 3 presents the functional block diagram highlighting extreme.

Functional diagram of figure 1 contains two blocks 1, 2 highlight extremum, block 3 dimensions of time shifts and test the amplifier 4 with the load RL. The output of the amplifier 4 is connected to the input of the delayed signal y(t) meter, which (input) serves as the input unit 1, the output of which is connected to the first input unit 3 measurement time shifts, a second input connected to the output of block 2, entrance to which is input an advanced signal x(t) meter and combined with the input of the test amplifier 4, the output τ* meter is the output of block 3.

Functional diagram (figure 3) unit 1 (2) allocation of extremum contains analog-to-digital Converter (ADC) 5, the registers 6, 7, 8, Comparators 9, 10, element 11 And the elements 12, 13, 14 delay. Information input x(t), y(t) ADC 5 serves as the input unit, the output of which serves as the output element And 11, the output of the ADC 5 is connected to the information input of the register 6, the output of which is connected to the information input of the register 7, the output of which is connected to the information input of the register 8, the output of the register 6 is connected to the input of the comparator 9, the entrance To which is connected to the output of the register 7, the input a of the comparator 10 is connected to the output of the register 8, and the entrance To to the paratore 10 is combined with the input In the comparator 9, the outputs of the Comparators 9, 10 are connected respectively to first and second inputs of the element And 11, a third input connected to the output of the delay element 14, the inlet of which is connected to the clock input CLK of the block clock inputs of the ADC 5 and the register 8 of the consolidated and are also connected to the clock input CLK of the block, the clock input of the register 6 is connected to the output of the delay element 12, an input connected to the output of the delay element 13, the inlet of which is connected to the clock input CLK of the block, the clock input of the register 7 is connected to the output of the delay element 13. The output of the ADC 5, information inputs and outputs of the registers 6, 7, 8, and inputs of the Comparators 9, 10 are multibit and are designed to work with parallel codes.

The timing diagram (figure 2) contain the input x(t) and output y(t) signals of the tested amplifier 4 on the assumption that the group delay time is zero (figa), and the amplifier 4 has the properties of non-linear four-terminal network; the input x(t) and output y(t) signals of the tested amplifier 4 on the assumption that the group delay time is not zero and is equal to τ (fehb), and the amplifier 4 has the properties of non-linear quadrupole.

The principle of operation of the meter (figure 1) on the functional level is quite simple and consists in the allocation of blocks 1, 2 of the extreme points of the input x(t) and output y(t) signals, and ZAT is m dimension in block 3 of the temporary shift τ between them. Measurement of phase shifts between extremes eliminates errors caused by fluctuations (offsets) the zero line and the influence of nonlinear distortion in the output waveform. From the graphs shown in figa, it is seen that the nonlinear amplification even in the complete absence of time-delay point of intersection of the zero line of the input x(t) and output y(t) signals are located in different places. As for the location of the extrema, they are insignificant when nonlinear distortions are not displaced, as well as by changing the position of the zero line. For these reasons, for measuring the group delay time or phase shifts is useful to distinguish the point of extremum and to measure the temporal distance between them, as shown for the case of modeling nonlinear amplification of a random process on figb.

One option unit selection extremum is a device (figure 3), highlighting the extremum in the range of positive values for the three related points.

Does such a device is as follows.

On the ADC input 5 is supplied subject to sampling and quantization of an analog signal, for example, x(t), which counts sequentially potato recorded in the registers 6, 7, 8. Through the first three quantum from the beginning the clocking of the ADC 5 in register 8 is náchod is, through the first sample x(t 1)register 7 - second countdown x(t2and in the case of 6 - third - s(t3). The obtained samples are compared in the Comparators 9 and 10. If you enter a comparison operator R, we can show that the Comparators 9, 10 are used to perform operations:

x(t1)Rx(t2) and x(t2)Rx(t3)

or in General

x(ti)Rx(ti+1) and x(ti+1)Rx(ti+2).

If the comparison process will be established that

x(ti)<x(ti+1) and x(ti+1)>x(ti+2),

then a decision is made available at the point ti+1extremum. At the outputs of the Comparators 9, 10 are set to the high logic levels and therefore the pulse at the output of the element And 11. As a comparator can be used chip 1564 SP1, representing a three-level discriminator which generates a sign “more”, “less” with the appropriate sign of the difference of the input operands [Avanesyan BORN, Bespalov A. Unipolar integrated circuits. Handbook - M.: Radio and communication, 2003, str-170].

To correct the record counts clock pulses in the registers 6, 7 served with some delay relative to the clock inputs of the ADC 5 and the register 8. Items 12, 13 delay allows sequentially within a single clock cycle to rewrite the information from the register 7 register 8, then from the register 6 register 7 and only the Les that record in the register 6 a new reference formed in this step at the output of the ADC 5. The delay elements 12, 13 is selected based on the performance of registers and conversion time tCRThe ADC. This should satisfy the condition T>t12+t13>tCR(T is the repetition period of the clock pulses at the input CLK, t12the time delay element 12; t13the time delay element 13). The delay element 14 is required to offset the issuance of the output pulse of the presence of an extremum at the time at which the information in the registers 6, 7, 8 will have to be updated, that is, the specified delay time must be less than T and about (10-20)% greater than the sum of t12+t13.

Implemented in the described block allocation extremum algorithm allows you to make a decision about the presence of an extremum and to determine the position of the extremum is not in the moment of its formation, but only after it was formed, approximately one clock cycle. However, this does not mean that the measurements will be a systematic error equal to about So there is no Error, because the pulses having a extreme shift at the same time, both input and output signals, so theoretically the relative displacement may not be. Of course, in practice, to minimize the relative displacement (misalignment) it is necessary to synchronously control the operation of the ADC in blocks 1, 2 and cu is IU, in these units the parameters of the elements 14 should be as similar as possible.

The application of the described meter can significantly reduce the error evaluation group delay time in real devices exhibiting nonlinear properties, as well as the output of which may be offset zero line. It is established that even when the harmonic distortion not exceeding 6%, the errors caused by incorrect allocation of the same reference points by widely used clipping, can reach tens of microseconds. In the device due to the replacement operation of the clipping on the allocation of extremum such errors were excluded on methodological level.

1. Measuring group delay time, which includes the unit of measurement of time shifts, the output of which is the output of the measuring device, characterized in that it introduced two unit selection extremum, the input of the first of them is the delayed input signal, the input of the second block selection extremum is a sign of an advanced signal, the outputs of the first and second allocation unit extremum connected respectively to first and second inputs of the unit of measurement of time shifts.

2. The meter according to claim 1, characterized in that the block allocation extremum contains analog-to-digital Converter, T. and case, two comparator binary element And three delay elements, the information input of the analog-to-digital Converter serves as the input unit selection extremum, the output of which serves as the output element And the output of the analog-to-digital Converter connected to the information input of the first register, the output of which is connected to the information input of the second register, the output of which is connected to the information input of the third register, the output of the first register connected to the first input of the first comparator, the second input is connected to the output of the second register, the first input of the second comparator connected to the output of the third register and a second input of the second comparator is combined with the second input of the first comparator, the outputs of the first and second Comparators respectively connected to first and second inputs of the element, And a third input connected to the output of the first delay element, the input of which is connected to the clock input of the block clock inputs of analog-to-digital Converter and the third register of the joint and also connected to the clock input unit, the clock input of the first register connected to the output of the second delay element, the input connected to the output of the third delay element, the input of which is connected to the clock input unit, the clock input of a second register connected to the output of t is its delay elements.



 

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