Codec for noise immune cyclic code

FIELD: communications engineering; data transfer, telemetering, and telecontrol systems.

SUBSTANCE: proposed codec has on sending end code-word data part shaper whose output and that of code-word synchronizing part shaper are connected to modulo two adder input; on receiving end it has binary filter whose code-word data part shaper output is connected to accumulator connected to synchronizing sequence decoder and to error connection unit whose outputs are connected to respective inverting inputs of code-word data part shaper; output of the latter functions as data output of device; output of binary-filter code-word synchronizing part is connected through switching unit to input of code-word data part shaping unit; synchronizing sequence decoder output is connected to control input of switching unit and to error correction unit input; on receiving end accumulator outputs are connected to inputs of code-word data part shift decoder whose output is connected to input of delay circuit whose output functions as second control input of switching unit and as synchronizing output of device.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

 

The invention relates to the field of communication technology and can be used in data transmission systems, and in systems, telemetering and telecontrol for the transmission of information without the prior phase.

The codec or encoder and the decoding device described in this application, is used for encoding and decoding linear error-correcting cyclic codes, as well as for frame synchronization of these error-correcting codes. In the proposed device to the communication channel to transmit the sequence of symbols is equal to the sum of symbol error correcting code and symbol synchronization sequence, and the sequence of characters produced by the summation symbols recurrent sequels error correcting code and symbol synchronization sequence. Cyclic synchronization is performed using a synchronization sequence imposed on the error-correcting code, and therefore, transmission of redundant additional symbols for synchronization purposes is not required.

After the establishment of synchronization error-correcting code, the synchronization sequence is removed from error-correcting code, not reducing the correcting ability of the code.

Most effectively the proposed device can be used in communication channels with grouping the errors, since the decoding is carried out in the sliding receive window, and outside the receive window, permit the occurrence of an arbitrary number of errors in the received sequence that does not lead to the transformation of the error correcting code. For example, the proposed device can be used in communication channels with multipath propagation of the signal. If this message is accepted, if the length of time between adjacent fading of the signal caused by the interference of rays of signal propagation, not less than the duration of the sliding receive window. Under a sliding receive window in this application is understood to be a sequence of n consecutive characters of error-correcting code, taking into consideration the cyclic permutations of code symbols, where n is a constant value equal to the block length error-correcting code.

The present invention aimed at solving the urgent problem of increasing the noise immunity of the reception of the cyclic code when working in communication channels with high noise level.

Known codec error correcting cyclic code, containing on the transmission side driver information part code word consisting of a shift register, connected to the modulo two, the clock shaper part of the code word and the modulo two parts of code words is, moreover, the outputs of the generators connected to the modulo two parts of the code words, and at the receiving side containing the binary filter information part code word consisting of a shift register, connected to the adders modulo two, and the decoder [1].

However, this device has a low immunity, so as to decode the error correcting code required undistorted reception symbols of the code.

Closest to the proposed device is a codec error correcting cyclic code (prototype), containing on the transmission side driver information part code word consisting of a shift register, connected to the modulo two information part code words, the clock shaper part of the code word and the modulo two parts of the code words, and the input of the shift register driver information part code word is an information input device, and the output of the shift register driver information part code word and the output of the shaper clock part of the code words are connected with the inputs of the modulo two parts of the code words, the output of which is connected to the channel communication at the receiving side containing the binary filter consisting of a shift register binary filter and connected the s to it modulo two clock part of the code word is a binary filter and modulo two the information part of the code word is a binary filter, the block forming information part code word consisting of a shift register block forming information part code words with connected modulo two blocks formation of the information part of the codeword, the decoder synchronizing sequence, the drive, the block error correction and the switch, while the drive is connected to the output of the modulo two the information part of the code word is a binary filter, the output drive is connected to the decoder synchronization sequence and the input of block error correction whose outputs are connected to respective inverting inputs of the shift register block forming information part code words, the output of which is an information output device, the input of the shift register block forming information part code word through a switch connected to the output of the modulo two clock part of the code word is a binary filter, the output of the decoder synchronizing sequence is connected with the control input of the switch and the input of block error correction [2].

A disadvantage of this device is a low noise immunity, because the reception of messages is possible only if the received sequence errors, the multiplicity of which is not above the COI is alausa ability of the code.

The purpose of the present invention is the increased robustness of reception of the message by introducing decoder shift information part code word and the delay element, which allows the decoding of error-correcting code in the sliding receive window, and outside of the moving window, you may experience any number of errors in the received sequence, including exceeding the correction capability of error-correcting code.

To achieve the goal proposed codec error correcting cyclic code, containing on the transmission side driver information part code word consisting of a shift register, connected to the modulo two information part code words, the clock shaper part of the code word and the modulo two parts of the code word. Moreover, the input of the shift register driver information part code word is an information input device, and the output of the shift register driver information part code word and the output of the shaper clock part of the code word are connected with inputs of modulo two parts of the code words, the output of which is connected to the communication channel at the receiving side containing the binary filter consisting of a shift register binary filter, and connected in parallel to it modulo two clock part of the code word is a binary filter and modulo two the information part of the code word is a binary filter, the block forming information part code word consisting of a shift register block forming information part code words with connected modulo two blocks formation of the information part of the codeword, the decoder synchronizing sequence, the drive, the block error correction and switch. When this drive is connected to the output of the modulo two the information part of the code word is a binary filter, the output drive is connected to the decoder synchronization sequence and the input of block error correction whose outputs are connected to respective inverting inputs of the shift register block forming information part code words, the output of which is information inverting inputs of the shift register block forming information part code words, the output of which is an information output device, the input of the shift register block forming information part code word through a switch connected to the output of the modulo two clock part of the code word is a binary filter, the output of the decoder synchronizing sequence is connected with the control the input of the switch and the input of block error correction. What's new is that on the receiving side entered desire the EOS shift information part code word and a delay element. Thus the outputs of the drive connected to inputs of decoder shift information part code words, the output of which is connected to the input of the delay element whose output is the second managing the switch input and synchronization output device.

The drawing shows a structural diagram of the device. On the transmitting side codec error correcting cyclic code (the encoder) contains driver information part code word 1, consisting of a shift register 2 is connected to the modulo two information part code word 3, modulo two information and clock parts code words 4 and the clock shaper part of the code word 5.

At the receiving side codec error correcting cyclic code (decoding device) contains the binary filter 6, consisting of a shift register binary filter 7 connected to the modulo two the information part of the code word is a binary filter 8 and modulo two clock part of the code word is a binary filter 9, a switch 10, a memory 11, a block error correction 12, block forming information part code word 13, consisting of a shift register block forming information part code words 14 connected with what Mataram modulo two block forming information part code word 15, the decoder synchronizing sequence 16, the decoder shift information part code word 17 and the delay element 18.

The proposed device operates as follows.

On the transmission side form the output sequence. To do this, the original message volume k symbols of the first code for error-correcting cyclic code. A coding information get the word error correcting cyclic code C(n,k)=a0,a1,...,an-1information whose length is k symbols and the block of n symbols. Since the code is cyclic, there is a recurrence relation, which allows you to get all validation code symbols

Then the word of the cyclic code C(n,k) are recurrently continue using the same ratio to the length of n1≥n and at the same time, due to the cyclic error-correcting code, receive sequence consisting of the same characters code

K(n1,k)=a0,a1,...,an-1, a0,a1,...,an-1,..., a0,a1that...,

i.e. get the code with repetition (double or multiple repetition). Property of such a code, unlike conventional code with repetition, is that any combination of characters in a sliding window of length n characters will be error-correcting word is th code C(n,k).

On the transmission side of the communication line, the word error correcting cyclic code obtained using the driver information part code word 1. To this end, in the feedback circuit of the shift register 2 enabled modulo two 3. The taps of the shift register 2 in modulo two 3 correspond to the nonzero coefficients of the test polynomial error-correcting cyclic code h(x) and the process shifts data in the shift register 2 carry out the calculation of the check character code in accordance with recurrent relation (1).

At the beginning of the codec k bits of the initial information received by the information input device, write k bit shift register 2. Then for n1clock cycles, where n1- the length of the output sequence, carry out the shift of this information. During the first k clock cycles at the output of the shift register 2 receive the characters input information in the next n-k cycles - checklist code symbols, and for the remaining n1-n tick - characters recurrent continuation code.

At the same time form a continuous cyclic synchronizing sequence of length n symbols. Such a sequence can be any sequence of suitable length with good timing properties, for example, posledovatelnosti.html length (code reed - Muller 1st order) with the check polynomial r(x). This sequence recurrently continue up to the length n1characters

D(n1)=d0d1,...,dn-1d0d1,...,dn-1,..., d0d1that...

The sync sequence is obtained from the clock shaper part of the code word 5. The clock shaper part of the code words 5 can be performed, for example, in the form of a shift register having n1discharge, in which the signal initial setup of a permanent record of the synchronizing sequence of bits of the shift register signal initial setup acquires a certain status).

The symbols of the output sequence on the transmitting side

B(n1)=b0b1,...,bn-1b0b1,...,bn-1,..., b0b1that...

get the addition modulo two characters cyclic error-correcting code with symbols synchronizing sequence:

bi=ci⊕dii=0...n-1

The summation symbol code characters synchronizing sequence is carried out modulo two information and clock parts code word 4. Output of this adder symbols of the output sequence are received in the communication channel.

At the receiving side adopted p the consistency, because of errors in the communication channel, in the General case differs from the transmitted sequence B(n1) and can be written in the form:

At the receiving side symbols of the received sequence is first fed to the input of the binary filter 6, which contains a shift register binary filter 7, modulo two the information part of the code word is a binary filter 8 and modulo two clock part of the code word is a binary filter 9. Modulo two the information part of the code word is a binary filter 8 is enabled in accordance with the check polynomial error-correcting code h(x), i.e. the taps of the shift register binary filter 7 for modulo two the information part of the code word is a binary filter 8 correspond to the nonzero coefficients of the test polynomial error-correcting cyclic code h(x). Similarly, modulo two clock part of the code word is a binary filter 9 is included in accordance with the check polynomial synchronizing sequence r(x). Thus modulo two the information part of the code word is a binary filter 8 calculates the syndrome of the error-correcting cyclic code, i.e. the sum modulo two of the test code symbols, calculated according to the information symbols the Lam, and received check symbols. When the input binary filter 6 error-free code word, the syndrome code is equal to zero, and the result of the calculation of the syndrome will be received and converted into a binary filter 6 is transmitted to the synchronization sequence. When the input binary filter 6 code words with errors will be calculated combination of a set of binary combinations, corresponding to the sum of the non-zero syndrome error correcting code and converted synchronizing sequence.

The converted synchronization sequence superimposed with the syndrome of error-correcting code from the output of the modulo two the information part of the code word is a binary filter 8 and then goes into the drive 11.

Similarly modulo two clock part of the code word is a binary filter 9 calculates the syndrome synchronizing sequence and, as a result, are symbols of error-correcting code, i.e. the information sequence with the imposed syndrome synchronizing sequence.

From the output of the modulo two clock part of the code word is a binary filter 9 this information sequence is supplied through the switch 10 to the input of the block forming information part to the new words 13. When this code symbols with a certain phase shift determined by the position of the sliding receive window in the received sequence, written in the shift register block forming information part code words 14.

The drive 11 is connected to the decoder synchronizing sequence 16 that is configured on the structure of the synchronizing sequence given syndrome code corresponding to a combination of errors allowable ratio. It is permissible number of errors is determined by correcting the error correcting ability of the code or the minimum code distance of error-correcting code. The selection of a subset of the decrypted error takes into account the propagation of channel errors caused by the passage through the binary sequence filter 6.

The operation of decoder synchronization sequence 16 indicates the reception of the synchronizing sequence with the maximum allowable number of errors. In the shift register block forming information part code words 14 will be, with a certain phase shift relative to the information symbols of the code symbols of error-correcting cyclic code.

The location of the error in the code symbols is localized block error correction 12 when determining the combination of the syndrome code tax the military synchronizing sequence. Block error correction 12 may be performed, for example, in the form of a persistent storage device (ROM), in which the recorded binary combinations of errors (error table). The address input of the ROM is a binary combination corresponding to the combination syndrome superimposed with the synchronization sequence, and the output is the corresponding binary combination of errors in the symbols of the code word.

This allows correction of erroneous characters in the shift register block forming information part code words 14. Correcting errors in the shift register block forming information part code word 14 is performed by inversion of the corresponding bits in the received code word.

At the same time the signal from the decoder synchronizing sequence 16 actuates the switch 10, and the output of modulo-two block forming information part code word 15 through the switch 10 is connected with the input of the shift register block forming information part code words 14. The block forming information part code word 13 is placed into the offline generation of information part of the code word.

Receiving symbols of the communication channel implementing a sliding window, so the symbols of the code word in the shift register unit creation is the information part of the code word 14 can have a phase shift relative to the information symbols of error-correcting code. The magnitude of this phase shift is determined by the magnitude of the shift converted synchronizing sequence, located in the memory 11. The drive 11 is connected to the decoder shift information part code word 17 preconfigured on the structure of the synchronizing sequence given syndrome code corresponding to a combination of errors allowable ratio. When triggered, the decoder shift information part code word 17, the magnitude of the phase shift from the output of the decoder is fed to the input of delay element 18 and specifies the time delay required to obtain the shift register block forming information part code words 14 information symbols of the code. Delay element 18 can be performed, for example, in the form of a reversible counter whose state is set by the output signal of the decoder shift information part code word 17. When you return the counter to its original state signal zero state of the counter will correspond to the delay time from the moment of installation of the meter signal from the decoder to the time of transition of the counter to the zero state.

At the time of occurrence of a signal from the output of the delay element 18, the shift register block forming information part code words 14 will be info the information symbols of error-correcting cyclic code. The output signal of the delay element 18 is a synchronizing signal, indicating that the decoded information from the output of the shift register block forming information part code word 14 is supplied to the codec output and can be read by the information recipient. This signal returns the switch 10 in the initial state of the receiving side codec ready to receive the next message.

Note that the imposition of a synchronizing sequence for a code word in the modulo two information and clock parts code word 4 gives the words of the error correcting code property samsungringtones and does not require the introduction of additional redundancy for the purpose of frame synchronization.

In the present invention, unlike the known device, the symbol error correcting cyclic code recurrently continue receiving code words carry a sliding window and sliding receive window allow the number of errors within the correcting ability of the code, and outside the window you may experience arbitrary number of errors in the received sequence that does not lead to the transformation of the error correcting code. Therefore, the proposed device allows you to receive messages in the communication channels with independent and gr is piyushimita errors at higher noise level.

Achievable technical result of the proposed codec error correcting cyclic code is to improve its noise immunity.

Sources of information:

1. USSR author's certificate No. 365033, CL N 03 To 13/04 was investigated, publ. 21.11.73.

2. USSR author's certificate No. 809550, CL N 03 To 13/04 was investigated, publ. 28.02.81.

Codec error correcting cyclic code, containing on the transmission side driver information part code words whose output and the output of the shaper clock part of the code word are connected with inputs of modulo two information and synchronize the parts of the code words, the output of which is connected to the communication channel, the input of the shaper information part code word is an information input device on the receiving side is a binary filter, the output data portion of the code word which is connected to the drive that is connected to the decoder synchronization sequence and a block error correction whose outputs are connected to respective inverting inputs of the processing unit of the information part of the code words, the output of which is the information output device output the synchronizing part of the code word is a binary filter through the switch connected to the input of the block forming information part Kodo is wow words the output of the decoder synchronizing sequence is connected with the control input of the switch and the input of block error correction, wherein at the receiving side entered the decoder shift information part code word and a delay element, with an output drive connected to inputs of decoder shift information part code words, the output of which is connected to the input of the delay element whose output is the second managing the switch input and synchronization output device.



 

Same patents:

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

The invention relates to the field of communication technology and can be used in data transmission systems, systems, telemetering and telecontrol

The invention relates to a coder/decoder in a communication system, and more particularly to a device for encoding/decoding of linear block codes by analyzing serial concatenated codes

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

FIELD: communications engineering; data transfer, telemetering, and telecontrol systems.

SUBSTANCE: proposed codec has on sending end code-word data part shaper whose output and that of code-word synchronizing part shaper are connected to modulo two adder input; on receiving end it has binary filter whose code-word data part shaper output is connected to accumulator connected to synchronizing sequence decoder and to error connection unit whose outputs are connected to respective inverting inputs of code-word data part shaper; output of the latter functions as data output of device; output of binary-filter code-word synchronizing part is connected through switching unit to input of code-word data part shaping unit; synchronizing sequence decoder output is connected to control input of switching unit and to error correction unit input; on receiving end accumulator outputs are connected to inputs of code-word data part shift decoder whose output is connected to input of delay circuit whose output functions as second control input of switching unit and as synchronizing output of device.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: communications engineering, in particular, engineering of data transfer systems for decoding cyclic interference-resistant codes without preliminary phasing.

SUBSTANCE: during decoding of cyclic interference-resistant code, range of presumed lengths of code combinations [nmin-nmax] is determined, and assumed phase of beginning of code combination f is set, from phase f in received code series several presumed code combinations Si are selected and pairs are formed from selected combinations in accordance to condition Si≠Sk, N of greatest common divisors, represented by polynomials, is calculated, and from calculated polynomials a polynomial of least order is selected, which is considered equal to original polynomial g(x) of cyclic interference-resistant code, if N of greatest common divisors is equal to "1", then length of proposed code combination n is increased by one, phase of proposed beginning of code combination is altered for one, if greatest common divisor, different from "1", is not found for all n∈[nmin-nmax], combinations of errors are determined in code word and selected code combinations are decoded.

EFFECT: development of method for decoding cyclic interference-resistant code under conditions of adaptation of interference-resistant code to quality of information transfer channel.

3 cl

FIELD: communications engineering, possible use in data transmission systems, for remote measurement, remote control, in radio-transmitting equipment of small spacecrafts and for deep space telemetry.

SUBSTANCE: in accordance to the invention, at transmitting side code words are generated by encoding information symbols using cyclic code without usage of synchronizing patterns, parameters of cyclic code are changed depending on level of interference, transferred information is accumulated at receiving side, thus creating a selection, then for phasing by code words limits of code word are determined, supposed length of code word is set, and in set window "sliding" symbol-wise discrete Fourier transformation is performed in Galois field for whole volume of selection being analyzed, while at each step of "sliding" discrete Fourier transformation in Galois field, selection of zero spectral components is performed as well as determining of quantity thereof together with building a function of number of zero spectral components at each step of "sliding" discrete Fourier transformation in Galois field, then decimation of given function is performed with step, equal to supposed length of code word, with building of a function estimate of mathematical expectation of number of zero spectral components, phasing moments reach maximum of mathematical expectation estimation function of number of zero spectral components, with consideration of resulting maximum, code words are selected, and then estimate of mathematical expectation of code word spectrums is performed and parameters of cyclic code are evaluated on basis of resulting code words, and then cyclotomic classes are determined, the generative polynomial of cyclic code is restored and code words are decoded.

EFFECT: increased interference resistance of cyclic code receipt, automatic adaptation of characteristics of transferred signal to interference intensity, increased speed of information transfer and accelerated phasing process during transfer of code words without synchronizing patterns.

4 dwg

FIELD: physics, communication.

SUBSTANCE: invention is related to the field of communication and may be used in devices for transmission of discrete information in communication line with interferences. Device contains memorising register, unit of error detection, unit of error correction, switching unit, which consists of two "AND" circuits, two registers of generator polynomial, two summators by module two, two decoders, programmable logical matrix, comparison unit, processor, inverter. Also method is disclosed for correction of two errors in cyclic code, which is realised by this device.

EFFECT: increase of communication channels equipment interference protection.

2 cl, 2 dwg, 1 tbl

FIELD: information technologies.

SUBSTANCE: invention is related to data transfer technology and may be used in systems with decision feedback for reception of information coded by cyclic code that permits majority decoding procedure. Decoder with detection and correction of errors comprises two OR elements, shift register, nine keys, syndrome calculator, summators, majority element, summator by module two, counter of corrections, shift counter, unit of discrete integration, counter of invalid symbols and buffer shift register. The novelty in decoder is introduction of discrete integration unit, counter of invalid symbols, the second OR element, two keys (eighth and ninth) and buffer shift register, and also change of connections between available elements of decoder. All that helped to increase noise immunity and accuracy of decoding of received discrete signals due to application of majority decoding principles.

EFFECT: improved noise immunity and accuracy of decoding.

1 dwg

FIELD: information technology.

SUBSTANCE: disclosed is a signal transmitting device comprising: a forward error correction (FEC) encoder which performs FEC coding of input data according to a Bose-Chaudhuri-Hocquenghem (BCH) coding scheme and a low-density parity check (LDPC) coding scheme; a first interleaver which interleaves FEC coded data; a symbol display unit which converts the interleaved data into data symbols; a second interleaver which interleaves data symbols; an encoder which codes data symbols interleaved by the second interleaver according to a multiple-input single-output (MISO) coding technique; a unit for inserting a pilot symbol into data frames which contains coded data symbols. At least the pilot symbol includes information for the type of transmission according to the MISO coding technique; and a transmitter for transmitting the data frame which includes the pilot symbol and data symbols.

EFFECT: high efficiency o using channel bandwidth, high rate of transmitting data and longer signal transmission distance.

15 cl, 35 dwg

FIELD: radio engineering, communications.

SUBSTANCE: device comprises a correction device, a circuit of bit quality identification, a demodulator, a circuit of symbol quality detection and selection of least valid symbols, a circuit of code cycle synchronisation with integrated soft and hard decisions, a circuit of error vectors generation for least valid symbols, a unit of summators by module two, a unit of decoders of a BCH code, a circuit for detection of least weight, a controller of PC code decoder.

EFFECT: increased validity of information reception in channels with high level of noise.

1 dwg

FIELD: radio engineering, communication.

SUBSTANCE: method for noiseless conversion of speech signals in a digital radio communication system through modification thereof into a digital form via delta modulation is characterised by determining the digital value ei of the next i-th speech reading using the difference between the input signal reading xi and the approximation of said reading yi, expressed by a given relationship, and subsequent redundant coding of the digital information with noise-immune cyclic or convolution code, wherein to improve noise-immunity of the digital signal, a convolution code sequence is used, pairs of readings xi,1 and xi,2 are coded simultaneously, which enables to maintain communication link data rate, which is equal to the analogue-to-digital conversion rate of the speech signal.

EFFECT: preventing increase of the data rate of a digital radio link.

3 dwg

FIELD: radio engineering, communication.

SUBSTANCE: device comprises a syndrome and pointer vector computing unit, a correction vector generating unit, an error vector initial element generating unit, a current syndrome and current pointer vector computing unit, a correction vector generation completion unit, an error vector continuation element generating unit, a correction unit, a unit for selecting the systematic portion of a codeword and random-access memory.

EFFECT: faster cyclic code decoding.

4 cl, 1 dwg

Up!