Parallel sign correlation meter

FIELD: computer science.

SUBSTANCE: device has first and second regenerators of random evenly spaced signals, second and first comparators, generator of short pulses, second and first binary counters, decoder, D-trigger, first and second RS-triggers, AND element, XOR element, reverse counter, clock pulse generator, divider with rebuilt division coefficient , pulse distributor, group of M synchronization blocks, group of M pulse distributors, N (M-10) - input elements R and N blocks for calculating ordinates of correlation function.

EFFECT: simplified construction and higher reliability .

2 cl, 4 dwg, 1 tbl

 

The invention relates to the field of computer engineering and can be used in measuring systems intended for the analysis of the characteristics of the stochastic correlation of random processes.

Known digital sign correlates for measuring correlation functions of stochastic processes with any probability distribution, containing two input devices, the inputs of which are the inputs of torrelamata, and outputs connected to first inputs of the first and second comparing device, the second inputs of which are connected respectively to the outputs of the first and second generators random equiprobable signals, the first and second outputs of the first comparing device connected to the zero and unit inputs the first trigger, direct and inverted outputs of which are connected with the first inputs of the first and second circuits coincidence, the second inputs of which are connected to first and second outputs of the second comparing device, the generator output pulse poll is connected via the start button with a single input of the second trigger, with the control input of the second comparing device and with the control input of the divider switch, a main input connected to the outputs of the first and second circuits overlap each channel output of the divider switch is connected to the input of the corresponding accounts is Chica pulses, control output of the divider switch connected to the control input of the first comparing device and to the signal input of the temporary selector, the output of which is connected through a frequency divider with a zero input of the second trigger, the direct output of which is connected with the control input of the temporary selector with control inputs of the first and second circuits matches, as well as with control inputs of the counters. The reading of the i-th pulse counter at the end of the measurement cycle corresponds to the i-th ordinate correlation (or cross correlation) function (A.S. USSR №304583, MKI G 06 F 15/34, bull. No. 17, 1971).

The disadvantage of this iconic correlate is the large statistical error in the limited duration of the implementation of the analyzed signals.

Known multi-iconic correlated, containing two blocks of the comparison, outputs of which are connected to the corresponding information unit accumulation through the block equivalence and distribution, a first control input connected to the output of the generator and with the control input of the second block of comparison, the random equiprobable signal, the output of which is connected to the first input of the first unit of comparison, a second input which is the first sign of torrelamata, one of the inputs of the block equivalence and distribution of soy is inen through the block of formation of zero of the ordinate and the first element And with their second Manager of the entrance, control output unit equivalence and distribution is connected to another input of the first element And a single input trigger control and through the element OR to the control input of the first unit of comparison, the output of the trigger control is connected with the control input of the switch unit processes and through the second element And with another input member OR the output of the pulse generator of the survey is connected to the zero input of the trigger control and to another input of the second element And the outputs of the switch unit processes connected to first and second inputs of torrelamata, and the output is connected to the information input of the second block of comparison, the second input is connected to the zero bus (A.S. USSR No. 538368, MKI G 06 F 15/34, bull. No. 45, 1976).

As in the previous case, in this multi-iconic correlate each cycle of calculation of the correlation function based on a continuous survey, only one of the units of comparison for a fixed survey of another block comparisons, which also leads to large statistical errors in the limited duration of the implementation of the analyzed signals. In addition, there is only one random equiprobable signal limits the class of distribution laws of random processes, for analysis which can be used this correlates.

It is known device is to determine the sign of the correlation function, contains two detector sign, two pulse shaper, two transducer time-code synchronization unit and the switch, and the inputs of the first and second detectors of the sign are the corresponding information input device, the outputs of the first and second detectors sign respectively connected to information inputs of the first and second pulse shapers, the outputs of which are respectively the first and the second input signal changes sign device, the information output of the first inverter, the time code is connected with the first information input of the switch, the output characteristic of the switching of which is connected to the inputs of the initial installation of the first and second pulse shapers and the first Converter, the time code clock input which is connected to the first output of the synchronization unit, the address switch input is a reference input numbers input device, information input switch is the output of the code length of the input signal, the gate input of the switch is by the entry permit reading the code length of the device, the information signal outputs limit the duration of the first and second converters time-code are respectively the outputs of the duration of the first and second signals of the device, that the preset inputs of the first and second converters, the time code is connected with the first output of the synchronization unit, the second and third outputs of which are connected to the reset inputs respectively of the first and second converters, time-code, the first and second inputs stop synchronization unit connected respectively to the outputs of the characteristic signal of the first output and the characteristic signal of the second output switch, the second information input of which is connected to the information output of the second inverter time code, input the initial installation which is connected to the output characteristic of the switching of the switch (AS the USSR №1628067, MKI G 06 F 15/336, bull. No. 6, 1991).

In this device, the process of computing the correlation function is divided into two stages: first write data on the studied signals, and then the subsequent processing of the recorded data. This reduces the operating speed of the device. Using pipeline processing mode, data at the parallel calculation of the ordinates of the correlation function requires compliance with the order of events associated with the number of calculations of the ordinates of the correlation function. With the increasing number of parallel computed ordinates of the correlation function increases the duration of a full cycle pipelined data processing. As a result, the time duration of a full cycle pipelined data processing may exceed the time interval between two pic is adulterinum events record the results of converting the analyzed signals, that leads to disruption of the sequence of events and does not allow to achieve optimal performance, calculation of the ordinates of the correlation function. In addition, this correlates allows you to analyze only the signals from the normal distribution.

The closest in technical essence of the present invention is a parallel symbolic correlates containing the first and second Comparators, the first and second generators of uniformly distributed random signal shaper short pulses, the first and second binary counters, a decoder, a group of M binary counters, the first and second RS-triggers, D-trigger element And the EXCLUSIVE OR element, a reversible counter, a clock, a divider with a configurable dividing ratio, the pulse distributor, the N groups, each of which consists of M code converters-N (M-1)-vchodove elements OR and N blocks compute y correlation (cross correlation) function. The first inputs of the first and second Comparators are respectively the first and second inputs of torrelamata, the outputs of the first and second generators of uniformly distributed random signals is connected with the second inputs respectively of the first and second Comparators, the output of the first comparator connect the first input of the EXCLUSIVE OR element and with the information input of each of N blocks compute y correlation (cross correlation) function, the output of the second comparator is connected to the input of the shaper short pulses, with the second input of the EXCLUSIVE OR element and with the D-input of D-flip-flop, the clock input of which is connected to the input “start” correlate, and a direct output connected to the input of the sign of the initial state of each of the N blocks compute y correlation (cross correlation) function, the output of the shaper short pulses is connected to the counting input of the first binary counter, the output of which is connected to the address input of the decoder, the first M output of which is connected to the enable inputs of the account corresponding to M binary counters of the group and to the inputs of the block corresponding M code converters the time of each of the N groups, the last (M+1)-th output of the decoder is connected to the reset input of the first RS-flip-flop, the input set which is connected to the input “start” correlate, and a direct output connected to the first input element And the enable input of the decryption decoder with enable inputs account of the first and second binary counters, the output of the generator of clock pulses is connected to the counting input of the divider with a configurable dividing ratio, with a counting inputs of the M binary counters group, with the second input element And, with a counting input of the second binary counter, with the accounts the inputs of the M transducers code each time the th of the N groups and with the counting inputs of N blocks compute y correlation (cross correlation) function, the output element And is connected to the counting input of the reversible counter, the control input counting direction of which is connected to the output of the EXCLUSIVE OR element, the inputs of resetting the first and second binary counters, entrance reset the reversible counter, the inputs of the zero M of the binary counter group, the inputs initial setup M code converters-each of the N groups and inputs the initial installation of all blocks compute y correlation (cross correlation) function of the joint and is connected to the input “start” correlate, the output of the second binary counter is one of the outputs of torrelamata and carries information about the duration of the measurement time, the output of the reversible counter is output evaluation of the zero ordinate correlation (cross correlation) function, the output of each binary counter group is connected with the information input of the corresponding inverter code-time, part of each of the N groups, set the input of the divider with a configurable dividing ratio is connected to the input “start” correlate, and the reference input division factor is the reference input step delay measurement correlation (cross correlation) function, the control input of the divider with a configurable dividing ratio and the control input of the pulse distributor joint is connected to the direct output of the second RS-flip-flop, the input set which is connected to the input “start” correlate, the output of the divider with a configurable dividing ratio is connected with the information input of the pulse distributor, the N outputs of which are connected with inputs of launch of the respective first code converters-each of the N groups and inputs trigger the appropriate N blocks compute y correlation (cross correlation) function, in each of the N groups of the previous output of the Converter code-time is connected to the input of the subsequent run of the Converter code-time, the output of the last M-th Converter code-time in each of the N groups is connected to the input of the termination of the account corresponding computing unit the ordinate correlation (cross correlation) function, the outputs of the first (M-1) code converters-each of the N groups are connected to the inputs of the corresponding (M-1)-Vodolaga element OR the output of which is connected to the input of the sign-change of the corresponding computing unit of the ordinate correlation (cross correlation) function, the output of the last M-th Converter code the time, part of the last N-th group, is connected with the reset input of the second RS-flip-flop, the outputs of the N blocks compute y correlation (cross correlation) function outputs are estimates of the corresponding ordinates correlation (cooperation is me correlation functions (U.S. Pat. No. 2174705 RF, MKI G 06 F 17/15, bull. No. 28, 2001).

The disadvantage of this correlate can be attributed to structural redundancy, as it contains N identical groups, each of which includes in its membership by M transducers code.

The technical result of the invention is to simplify the structure and improve the reliability of torrelamata.

The technical result is achieved by the fact that in parallel iconic correlated containing the first and second generators are random uniformly distributed signals, the outputs of which are connected with the second inputs respectively of the first and second Comparators, the first inputs of which are respectively the first and second inputs of torrelamata, the output of the first comparator connected to the first input of the EXCLUSIVE OR element and with the information input of each of N blocks compute y correlation (cross correlation) function, the output of the second comparator is connected to the input of the shaper short pulses, with the second input of the EXCLUSIVE OR element and with the D-input of D-flip-flop, the clock input of which connected to the input “start” correlate, and a direct output connected to the input of the sign of the initial state of each of the N blocks compute y correlation (cross correlation) function, the output of the shaper short pulses is connected to the counting input of the first binary counter, the output of which is connected to the address input of the decoder, the last (M+1)-th output of which is connected to the reset input of the first RS-flip-flop, the input set which is connected to the input “start” correlate, and a direct output connected to the first input element And the enable input of the decryption decoder with enable inputs account of the first and second binary counters, the output of the generator of clock pulses is connected to the counting input of the divider with a configurable dividing ratio, the second input element And, with a counting input of the second binary counter and the counting inputs of N blocks compute y correlation (mutual correlation) function, the output element And is connected to the counting input of the reversible counter, the control input counting direction of which is connected to the output of the EXCLUSIVE OR element, the inputs of resetting the first and second binary counters, entrance reset the reversible counter and inputs the initial installation of all N blocks compute y correlation (cross correlation) function of the joint and is connected to the input “start” correlate, the output of the second binary counter is one of the outputs of torrelamata and carries information about the duration of the measurement time, the output of the reversible counter is the exit assessment to the zero ordinate correlation (cross correlation) function is AI, installation input of the divider with a configurable dividing ratio is connected to the input “start” correlate, and the reference input division factor is the reference input step delay measurement correlation (cross correlation) functions correlate, the control input of the divider with a configurable dividing ratio and the control input of the pulse distributor United and connected to the direct output of the second RS-flip-flop, the input set which is connected to the input “start” correlate, the output of the divider with a configurable dividing ratio is connected with the information input of the pulse distributor, the N outputs of which are connected with inputs of launch of the respective N blocks compute y correlation (cross correlation) function, the last N-th output of the pulse distributor is connected to the reset input of the second RS-flip-flop, the outputs of the N (M-1)-vchodove elements OR connected to inputs of the sign-change of the respective blocks compute y correlation (cross correlation) function, which outputs outputs are estimates of the corresponding ordinates of the correlation (cross correlation) function, introduced the group containing M blocks synchronization, and a group containing M distributors pulses, with the first M outputs of the decoder are connected to the enable inputs account compliance is adequate M blocks synchronization group, the inputs of the task of the issuing period gate pulse M blocks synchronization group are United and connected to the reference input of the step delay measurement correlation (cross correlation) functions correlate, inputs the initial installation of M blocks synchronization group are United and connected to the input “start” torrelamata, counting input of the M blocks of the synchronization group are United and connected to the generator output clock, the first output of the pulse distributor is connected to the input of the start of the first block group is synchronized, the output of the sign of equality to zero of the previous synchronization unit group is connected to the input of the start of the subsequent synchronization unit group, the output of the sign of equality to zero of the last M-th block of the synchronization group connected to the input termination of the account of the first computing unit of the ordinate correlation (cross correlation) function, the outputs of the sign of equality to zero of the first (M-1) blocks of the synchronization group are connected to the inputs of the first (M-1)-Vodolaga element OR the output characteristic of the issuance of the gate pulse M blocks synchronization group is connected to the control inputs of the respective M distributors pulse group, and outputs the gate pulse M blocks synchronization group are connected to information inputs of the respective M distributors pulse g is uppy, n-e outputs (n=1, 2, 3,..., N-1) first (M-1) distribution pulse of the group are connected with the inputs of the (n+1)th (M-1)-Vodolaga element OR, (N-1)th output of each of the distributors pulse group is connected to the input termination of the corresponding block synchronization group, the n-th output (n=1, 2, 3,..., N-1) the last M-th pulse distributor group is connected to the input termination of accounts (n+1)-th computing unit of the ordinate correlation (cross correlation) function.

Each synchronization unit includes first and second elements OR the first and second RS-trigger, a demultiplexer, and a reversible counter, And a comparison circuit and a divider with a configurable dividing ratio, and the information input of the demultiplexer and the counting input of the divider with a configurable dividing ratio combined and are counting input of the synchronization unit, the first address input of the demultiplexer is an entry permit account of the synchronization unit, the first inputs of the first and second elements OR input reset the reversible counter and set the input of the divider with a configurable dividing ratio are combined and input the initial setup of the synchronization unit, the input set of the first RS-flip-flop is the input of the start of the synchronization unit, the second input of the second element OR an input termination block is and synchronization the reference input of the divider with a configurable dividing ratio is the reference input of the issuing period Gating pulses of the synchronization unit, the output of the first element OR is connected to the reset input of the first RS-flip-direct the output of which is connected with the second address input of the demultiplexer and the second input element And first and second outputs of the demultiplexer are connected respectively to the inputs of the forward and backward accounts reversible counter whose output is connected to the first input of the comparison circuit, the second input of which is the zero-code output of the comparison circuit connected to the first input element And the output of which is connected with the second input of the first element OR with the input set of the second RS-flip-flop and an output of the sign of equality to zero of the synchronization unit, the output of the second element OR is connected to the reset input of the second RS-flip-direct the output of which is connected to the control input of the divider with a configurable dividing ratio is the output characteristic of the issuance of the gate pulses of the synchronization unit, the output of the divider with a configurable dividing ratio is the output of the Gating pulses of the synchronization unit.

Figure 1 shows the block diagram of torrelamata; figure 2 - block diagram of the synchronization unit; figure 3 - structural and therefore the and computing unit of the ordinate correlation (cross correlation) functions; figure 4 - block diagram of the shaper short pulses and timing diagrams of the operation.

Correlated contains the first 1 and second 2 generators random uniformly distributed signals, the first 3 and second 4 Comparators, shaper 5 short pulses, the first 6 and 12 second binary counters, decoder 7, D-flip-flop 8, the first 9 and second 17 RS-triggers, the And gate 10, the EXCLUSIVE OR element 11, the reversible counter 13, the generator 14 clock pulses, the divider 15 tunable division factor, the pulse distributor 16, a group that includes M blocks 181-18Msynchronization group including M distributors pulses 191-19mN (M-1)-vchodove items OR 201-20Nand N blocks 211-21Ncalculate the y-correlation (cross correlation) function.

Each synchronization unit contains the first 22 and second 28 elements OR the first 23 and second 29 RS-triggers, the demultiplexer 24, and a reversible counter 25, the comparison circuit 26, the And gate 27 and the divider 30C tunable division factor.

Each computing unit of the ordinate correlation (cross correlation) function contains an element OR 31, RS-flip-flop 32, the And gate 33, the flip-flop 34, the first 35 and second 36 XOR and reversible counter 37.

Shaper short pulses contains elements is EXCLUSIVE OR 38, flip-flop 39.

The outputs of the first 1 and second 2 generators random uniformly distributed signals is connected with the second inputs respectively of the first 3 and second 4 Comparators, the first inputs of which are respectively the first and second inputs of torrelamata, the output of the first 3 of the comparator connected to the first input of the EXCLUSIVE OR element 11 and with the information input of each of N blocks 211-21Ncalculate the y-correlation (cross correlation) function, the output of the second 4 of the comparator is connected to the input of the shaper 5 short pulses, with the second input of the EXCLUSIVE OR element 11 and the D-input of D-flip-flop 8, the clock input of which is connected to the input “start” correlate, and a direct output connected to the input of the sign of the initial state of each of the N blocks 211-21Ncalculate the y-correlation (cross correlation) function, the output of shaper 5 short pulses is connected to the counting input of the first 6 binary counter, the output of which is connected to the address input of the decoder 7, the last (M+1)-th output of which is connected to the reset input of the first 9 RS-flip-flop, the input set which is connected to the input “start” correlate, and a direct output connected to the first input element And 10, with the entry permit decoding of the decoder 7 and enable inputs account of the first 6 and 12 second binary MF is tchikov, the output of the generator 14 clock pulses is connected to the counting input of the divider 15 tunable division factor, with the second input element And 10, with a counting input of the second 12 binary counter and the counting inputs of N blocks 211-21Ncalculate the y-correlation (cross correlation) function, the output element And 10 is connected to the counting input of the reversible counter 13, the control input counting direction of which is connected to the output of the EXCLUSIVE OR element 11, the inputs are zero the first 6 and 12 second binary counters, entrance reset the reversible counter 13 and inputs the initial installation of all N blocks 211-21Ncalculate the y-correlation (cross correlation) function of the joint and is connected to the input “start” correlate, the output of the second 12 binary counter is one of the outputs of torrelamata and carries information about the duration of the measurement time, the output of the reversible counter 13 is the exit assessment to the zero ordinate correlation (cross correlation) function, set the input of the divider 15 tunable division factor is connected to the input “start” correlate, and the reference input division factor is the reference input step delay measurement correlation (cross correlation) functions correlate, the control input of the divider 15 with the reorganizations is ivemy division factor and the control input the pulse distributor 16 are United and connected to the direct output of the second 17 RS-flip-flop, the input set which is connected to the input “start” correlate, the output of the divider 15 tunable division factor is connected with the information input of the pulse distributor 16, the N outputs of which are connected with inputs of launch of the respective N blocks 211-21Ncalculate the y-correlation (cross correlation) function, the last N-th output of the pulse distributor 16 is connected to the reset input of the second 17 RS-flip-flop, the outputs of the N (M-1)-vchodove items OR 201-20Nconnected to inputs of the sign-change of the respective blocks 211-21Ncalculate the y-correlation (cross correlation) function, which outputs outputs are estimates of the corresponding ordinates of the correlation (cross correlation) function, the first M outputs of the decoder 7 is connected to the enable inputs of the account corresponding to the M blocks 181-18Msynchronization group, the inputs of the task of the issuing period gate pulse M blocks 181-18msynchronization group are United and connected to the reference input of the step delay measurement correlation (cross correlation) functions correlate, inputs the initial installation of M blocks 181-18msynchronization group are United and connected to the input “start” torrelamata, counting input of the M blocks 181-18msynchronize the groups merged and connected to the output of the generator 14 clock pulses, the first output of the pulse distributor 16 is connected to the input of the start of the first block 181the group is synchronized, the output of the sign of equality to zero of the previous block 18msynchronization group is connected to the input of the start of the subsequent block 18m+1synchronization group (m=1, 2, 3,..., M-1), the output of the sign of equality to zero of the last M-th block 18Msynchronization group is connected to the input of the termination of the account of the first unit 211calculate the ordinate correlation (cross correlation) function, the outputs of the sign of equality to zero of the first (M-1) blocks 181-18m-1synchronization group are connected to the inputs of the first 201(M-1)-Vodolaga element OR the output characteristic of the issuance of the gate pulse M blocks 181-18msynchronization group is connected to the control inputs of the respective M distributors pulses 191-19mgroup outputs the gate pulse M blocks 181-18msynchronization group are connected to information inputs of the respective M distributors pulses 191-19mgroup, n-e outputs (n=1, 2, 3,..., N-1) first (M-1) distribution pulses 191-19M-1group connected to inputs of the (n+1)th 20n+1(M-1)-Vodolaga element OR, (N-1)th output of each of the distributors pulses 191-19mgroup is connected to the input termination is the appropriate unit 18 1-18Msynchronization group, the n-th output (n=1, 2, 3,..., N-1) the last N-th pulse distributor 19mgroup is connected to the input of the termination of the account (n+1)-th block 21n+1calculate the ordinate correlation (cross correlation) function.

Each synchronization unit of the information input of the demultiplexer 24 and the counting input of the divider 30 with tunable division ratio of the joint and are counting input of the synchronization unit, the first address input of the demultiplexer 24 is input resolution account synchronization unit, the first inputs of the first 22 and second 28 elements OR input reset the reversible counter 25 and the setting input of the divider 30 with tunable division factor are combined and input the initial setup of the synchronization unit, the input set of the first 23 RS-flip-flop is the input of the start of the synchronization unit, the second input of the second element 28 OR the input termination of the synchronization unit, the reference input division factor divider 30 with tunable division factor is the reference input of the issuing period Gating pulses of the synchronization unit, the output of the first element 22 OR connected to the reset input of the first 23 RS-flip-direct the output of which is connected with the second address input of the demultiplexer 24 and with the second input element And 27, per the first and second outputs of the demultiplexer 24 are connected respectively to the inputs of the forward and backward accounts reversible counter 25, the output of which is connected to the first input of the comparison circuit 26, to the second input of which is the zero-code output of the comparison circuit 26 connected to the first input element And 27, the output of which is connected with the second input of the first element OR 22, to the input of the second RS-flip-flop 29 is the output of the sign of equality to zero of the synchronization unit, the output of the second element 28 is connected to the reset input of the second RS 29-trigger direct the output of which is connected to the control input of the divider 30 with tunable division factor and is the output characteristic of the issuance of the gate pulses of the synchronization unit, the output of divider 30 with tunable division factor is the output of the Gating pulses of the synchronization unit.

Each computing unit of the ordinate correlation (cross correlation) function second input of the OR element 31, the reset input of the T flip-flop 34 and the input reset the reversible counter 37 are combined and input the initial setup of the unit, the counting input t of flip-flop 34 is the entrance sign-change unit, and a direct output connected to a second input of the first 35 of the EXCLUSIVE OR element, the first input which is the input of the sign of the initial state of the block, and the output is connected to a second input 36 of the second element EXCLUSIVE OR of the first input by the information input unit, and the output connection is replaced with a control input the counting direction of the reversible counter 37, the first input of the OR element 31 is input termination of the account unit, and the output connected to the reset input of the RS-flip-flop 32, the input set which is the starting block, and a direct output connected to the second input element And 33, the first input of which is counter input unit, and the output connected to the counting input of the reversible counter 37, the output of which is the output of the block.

Correlates can measure the correlation RXX(τ) and cross correlation Rxy(τ) function centered random signalsand. Its work is based on the iconic method of measurement estimatesandthese functions using auxiliary signals ξ1(t) and ξ2(t).

Auxiliary signals ξ1(t) and ξ2(t) are independent relative to each other and relative to the analyzed signalsand. Instantaneous values of these signals are distributed uniformly within the interval from-a to +a and from-V to +V, respectively, i.e. their probability density functions have the form

The values a and b must satisfy the following conditions

where- the maximum possible absolute value, which can accept signals respectivelyand.

Algorithms that directly underlie the work of torrelamata are the following

where sgn{...} operator functions the iconic conversion; Δτ - step delay measurement correlation (cross correlation) function; Np- the total number of samples for the time interval measurement; T0the repetition period of the clock pulses (pulse survey); n=0, 1, 2, 3,..., N is the number of evaluations of the ordinate correlation (cross correlation) function.

Step delay Δτ measurement of correlation (cross correlation) function sets multiple of the period T0the sequence of clock pulses, that is Δτ=kT0where k=1, 2, 3,....

Correlates works as follows.

When measuring the mutual correlation function Rxy(τ) investigated centered random signalsandcome respectively into the first and second inputs of torrelamata, that is, the first inputs, respectively, of the first 3 and second 4 Comparators, the second inputs of which will otuput signals ξ 1(t) and ξ2(t) outputs, respectively, of the first 1 and second 2 generators random uniformly distributed signals.

As auxiliary signals ξ1(t) and ξ2(t) use linearly varying periodic signals (see Mir GY Characteristics of stochastic relations and their measurement): Energoizdat, 1982. S). In particular, it is possible to use signals of a triangular form, the schema generator triangular form, see the book: the Use of precision analog circuits / Agilista, Eaaaat, Geesteranus. - M.: Radio and communication, 1985. - S, RIS).

The first 3 and second 4 Comparators perform comparison operation signalsignal ξ1(t) and a signalsignal ξ2(t). The result of these operations will have the signals z1(t) and z2(t), which are significant signals

Since, in practice, the comparison circuit always fix a null value coded signals with equal probability either “-1”or “+1”when the measurement is usually used symbolic function that takes the values “-1” and “+1” (see Mir GY Characteristics of stochastic relations and their measurement - the.: Energoizdat, 1982. S). In accordance with the expressions (6) and (7) can be written in the following form

When the technical implementation of torrelamata as the first 3 and second 4 Comparators, you can use the integrated Comparators (see A.V. nefiodov Integrated circuits and their foreign counterparts: a Handbook. V.5. - M.: Goblet-a, 1997. - P.113-119). In this case, the logic unit outputs the first 3 and second 4 Comparators will match the value “+1” sign signals z1(t) and z2(t), and the levels of the logic zero at the outputs of these Comparators will correspond to the value “-1” of coded signals z1(t) and z2(t).

The signal z2(t) with the release of the second part 4 of the comparator is fed to the input of the shaper 5 short pulses. In moments of time corresponding to the transition signal values z2(t) from a logical zero to a logical unit or logical unit in the logical zero at the output of the shaper 5 short pulses are produced by short pulses. Shaper 5 short pulses may have different circuit designs, it is only necessary that he'd carried out their function. One of possible variants of such a driver and timing his work is represented in figure 4. In donnaslut it is based on the use of the EXCLUSIVE OR element 38, one input of which is the input of the shaper, and an output connected to the counting input T of the flip-flop 39 is the output of the shaper, direct T-flip-flop 39 is connected to the second input of the EXCLUSIVE OR element 38.

The pulses from the output of the shaper 5 short pulses arrive at the counting input of the first 6 binary counter.

In the initial state of torrelamata on direct outputs of the first 9 and second 17 RS-triggers are logic zero.

A logic level zero with the direct output of the first 9 RS-flip-flop is supplied to the enable inputs of the account of the first 6 and 12 second binary counters and prohibits them by pulses on their counter inputs respectively from the output of the shaper 5 short pulses and the output from the generator 14 clock pulses. A logic level zero with the direct output of the first 9 RS-flip-flop is supplied also to the input resolution decode decoder 7 and prohibits him from decoding data received at its address input from the output of the first 6 binary counter. The outputs of the decoder 7 will be logic zero. The logic zero from the first M outputs of the decoder 7 is coming to the enable inputs of the account corresponding to the M blocks 181-18Msynchronization group and forbid them by pulses on their counter inputs with output General the RA 14 clock pulses. In addition, a logic level zero with the direct output of the first 9 RS-flip-flop is supplied to the first input element And 10 and block the passage of pulses from the output of the generator 14 clock pulses to the counting input of the reversible counter 13.

A logic level zero with direct access 17 second RS-flip-flop is fed to the control inputs of the divider 15 tunable division factor and the pulse distributor 16 and blocks their action.

Blocks 181-18Msynchronization group, distributors of pulses 191-19Ngroups and blocks 211-21Ncalculate the y-correlation (cross correlation) functions do not operate.

Start correlate by a signal “start”. The signal “start” is a short pulse. Time steps of this signal determines the start of the measurement process and corresponds to the time t0which is assumed to be zero, i.e. t0=0.

The signal “start” in torrelamata takes the following position:

the first 6 and 12 second binary counters, and a reversible counter 13 are set to zero;

- on direct outputs of the first 9 and second 17 RS-triggers set the level of logical units;

- an integer value k of the division factor is recorded in the divider 15 tunable coefficient fact, the Oia.

The signal “start” is also supplied to the clock input of D-flip-flop 8, the D-input of which receives the signal z2(t). If at time t0action signal “start” signal z2(t) is the level of logical units (this means that), the D-flip-flop 8 is written to logical unit, and on its direct output level is set to a logical unit. If at time t0action signal “start” signal z2(t) has a logic level zero (this means that), the D-flip-flop 8 is written logic zero, and the direct current output is a logic level zero. Practically, this means that in the moment of a start signal, that is, at time t0corresponding to the beginning of the measurement process, in the D-flip-flop 8 is written to the initial value of z2(t0signal z2(t).

In addition, a start signal is supplied to the inputs of the initial installation of the blocks 181-18Msynchronization group and to the inputs of the initial installation of the blocks 211-21ncalculate the y-correlation (cross correlation) functions (see figure 2 and 3).

In each of the blocks 181-18Msynchronization group a start signal is supplied to the first inputs of the first 22 and second 28 OR and their outputs are fed to the inputs with the dew respectively of the first 23 and second 29 RS-triggers on direct outputs of which are logic zero. At the same time a start signal is fed to the input of reset the reversible counter 25 and setup the input of the divider 30 with tunable division factor. The result is zeroing reversible counter 25, and an integer value k of the division factor from the reference input of the issuing period gate pulse block is written to the divider 30 with tunable division factor. A logic level zero with the direct output of the first 23 RS-flip-flop is supplied to the second input element And 27 and closes it, i.e. at the output of the sign of equality to zero of the block is set to logic level zero.

Block diagram and working of blocks 211-21Ncalculate the y-correlation (cross correlation) function is completely the same as the units included in the device-prototype (U.S. Pat. No. 2174705 RF, MKI G 06 F 17/15. Bull. No. 28, 2001). In each of the blocks 211-21Ncalculate the y-correlation (cross correlation) function signal “start” is supplied to the second input of the OR element 31, to the reset input of the T flip-flop 34 and to the input of the reset reversible counter 37. The result is zeroing reversible counter 37, and to direct the output of the T flip-flop 34 is set to a logic level zero. The signal start is with the output element OR 31 is supplied to the reset input of the RS-flip-flop 32, and on his direct output is a logic level zero, which is supplied to the second input element And 33 and prevents the passage of clock pulses to the counting input of the reversible counter 37 is supplied to the counting input block output from the generator 14 clock pulses. Thus, in the reversible counter 37 at the initial measurement will be stored zero code.

That's all the initial setup is completed, and starts the process of measuring the mutual correlation function Rxy(τ).

Significant signals z1(t) and z2(t) are respectively the first and second inputs of the EXCLUSIVE OR element 11, which performs the function of the sign of the multiplier. If the logic levels of the signals z1(t) and z2(t) coincide, the output of the EXCLUSIVE OR element 11 will be a logic level zero. This means that the sum of these signals is equal to “+1”. If the logic levels of the signals z1(t) and z2(t) are opposite, then the output of the EXCLUSIVE OR element 11 will be the level of logical units. This means that the sum of these signals is equal to “-1”. The output signal from the EXCLUSIVE OR element 11 is supplied to the control input of the counting direction of the reversible counter 13. When a logic level zero on this is the entrance will determine the direct expense of the reversible counter 13 (summation mode), and the level of the logic unit determines the count in reversible counter 13 (subtract mode). (As a reversible counter 13 can be used, for example, the reversible counter CIE. Cm. Nefedov AV Integrated circuits and their foreign counterparts: a Handbook. V.5. - M.: Goblet-a, 1997. P.168).

The level of logical units with direct access to the first 9 RS-flip-flop is supplied to the first input element And 10 and permit the passage of clock pulses to its second input to the counting input of the reversible counter 13. Depending on the level of the signal at the control input of the counting direction of the reversible counter 13 will work or summation mode input sequence of clock pulses, or in the subtraction mode.

The level of logical units with direct access to the first 9 RS-flip-flop is supplied also to the input resolution decoding of the decoder 7 and the enable inputs account of the first 6 and 12 second binary counter and enables operation of these elements. This 12 second binary counter performs the expense of clock pulses at its counting input from the output of the generator 14 clock pulses. In turn, the first 6 binary counter provides a pulse count from the counter input from the output of the shaper 5 short pulses. Taking into account that the signal “start” determines the time t corresponding to the beginning of the measurement process, we will have that short pulses to the counting input of the first 6 binary counter, correspond to the moments of time t1, t2, t3,..., in which the signal z2(t) changes its value on the opposite after a signal “start”.

The decoder 7 depending on the binary code received at its address input from the output of the first 6 binary counter, consistently produces pulses at their outputs (as a decoder, you can use chips CIJ or KID and a pattern similar to them on purpose. Examples of schemes include decoder and to use them, see, for example, Zeldin E.A. Digital integrated circuits in information-measuring equipment. - L.: Energoatomizdat. Leningrad. separa-tion, 1986. S-118). Initially the contents of the first 6 binary counter is equal to zero. Therefore, the time duration of the signal “start”, that is, at time t0the pulse appears at the first output of the decoder 7. After the arrival of the first pulse from the output of the shaper 5 short pulses in the time t, the contents of the first 6 binary counter becomes equal to the unit, and a pulse appears at the second output of the decoder 7, etc. While the pulse duration at the m-th output of the decoder 7 is equal to tm-tm-1where m=1, 2, 3,..., M, and is going to be determined by the time during which the signal z2(t) does not change its value, that is, remains constant. The pulses from the first M outputs of the decoder 7 are sequentially received at the enable inputs of the account corresponding to the M blocks 181-18Msynchronization group. The pulse duration of tm-tm-1arriving at the entrance permit account m-th 18mthe synchronization unit group goes to the first address input of the demultiplexer 24 (see figure 2). Recall that the second address input of the demultiplexer 24 receives a logic level zero with the direct output of the first RS-flip-flop 23. The truth table of the operation of the demultiplexer 24 is presented below. As a result, the pulses coming from the output of the generator 14 clock pulses to the counting input of the m-th 18mthe synchronization unit of the group and, consequently, to the information input of the demultiplexer 24, during the time tm-tm-1will be held at the entrance of direct calculation reversible counter 25.

0
Table

the truth of the operation of the demultiplexer
InputsOutputs
The first addressThe second addressInformationFirstSecond
00/100
100/10/10
010/100/1
110/100

(Block diagram, which can be taken as a basis of simple demultiplexer, see, for example, Analog and digital electronics (Full course): Textbook for universities / Uppage, Oppugn, AiGuru; edited Oppugning. - M.: Hot line - Telecom, 1999. - S. Is. As a reversible counter 25 can be used, for example, the reversible counter CIE. Cm. Nefedov AV Integrated circuits and their foreign counterparts: a Handbook. V.5. - M.: Goblet-a, 1997. Pp.163).

Thus, in the reversible counter 25 blocks 181-18Msync group will be accumulated number in binary code η1thatη2thatη3,...,ηMcorresponding to the time intervals (t1-t0), (t2-t1), (t3-t2)...,(tM-tM-1), during which the signal value z2(t) is not changed.

You can write that

where m=1, 2, 3,..., M, and T0the repetition period of the clock pulses.

The momentum from the last (M+1)-th output of the decoder 7 will occupait to the reset input of the first 9 RS-flip-flop., which is on the leading edge of this pulse sets a logic level zero at its direct output. In the result, the first 6 and 12 second binary counters stop by pulses on their counting input, and the decoder 7 terminates the procedure interpretation and installs on all its outputs logic zero. To this point in time in the second 12 binary counter accumulates a number that specifies the total number of samples Np.

A logic level zero output of the first 9 RS-flip-flop is supplied to the first input element And 10 and prevents the passage of clock pulses to the counting input of the reversible counter 13. In the end, in the reversible counter 13 will be accumulated number of Sxy(0), which determines the scorezero ordinate mutual correlation function of the signalsand. Taking into account the constant coefficientincluded in the expression (5), assessment ofzero ordinate mutual correlation function of the signalsandequal to

As was shown above, the signal “start” to direct the output of the second 17 RS-flip-flop is also set to a logic level of a single who Itza, which is fed to the control inputs of the divider 15 tunable division factor and the pulse distributor 16 and allows them to work. In this case, the signal “start” in the divider 15 tunable division factor is entered integer value k of the division factor, which specifies the step Δτ delay measurement of the mutual correlation function

where T0the repetition period of the clock pulses from the output of the generator 14 clock pulses; k=1, 2, 3,....

The output of the divider 15 tunable division factor will have a sequence of pulses with a repetition period Δτ=kT0. These pulses will correspond to points in time (t0+Δτ), (t0+2Δτ),..., (t0+NΔτ). (As a divider 15 tunable division factor can be used, for example, the well-known integral programmable timer CVI or its analogs. Mode 2 this timer provides a period of output pulses of the timer is equal to k periods of the input pulses, where k is the initial contents of the timer counter. Cm. Alexenko A.G., Galitsin A.A., Ivannikov A.D. Designing electronic equipment for microprocessors: Programming, standard solutions, debugging techniques. - M.: Radio and communication, 1984. S-72). The pulses from the output of the divider 15 tunable division factor act on the information input of the pulse distributor 16 and consistently pass on its outputs. And the first pulse passes to the first output. The second pulse passes to the second output, etc. of the Last N-th pulse passes to the N-th output. (Pulse distributor may be based on a decoder and a binary counter. In particular, as the decoder can be used chips KID or KID and a pattern similar to them on purpose. Examples of schemes include decoder and to use them, see, for example, Zeldin E.A. Digital integrated circuits in information-measuring equipment. - L.: Energoatomizdat. Leningrad. separa-tion, 1986. S-118).

Pulses with N outputs of the pulse distributor 16 are received at the inputs of the start of the corresponding N blocks 211-21Ncalculate the y-correlation (cross correlation) function.

The pulse from the first output of the pulse distributor 16 through time Δτ=kT0after signal “start”, that is, at time (t0+Δτ), to the input of the launch of the first 181the synchronization unit group and in this block is fed to the input of the installation of the first 23 RS-flip-flop (see figure 2). To direct the output of the first 23 RS-trigger level is set to logical edit the Itza, which is supplied to the second address input of the demultiplexer 24. If Δτ≥(t1-t0), this time on the entry permit account of the first 181the synchronization unit of the group will be a logic level zero, which is supplied to the first address input of the demultiplexer 24. Then, according to the truth table operation, pulses from the information input of the demultiplexer 24 will be held at the entrance of the count in reversible counter 25. If Δτ<(t1-t0), this time on the entry permit account of the first 181the synchronization unit of the group will have to present the level of logical units, which is supplied to the first address input of the demultiplexer 24. In this case, according to the truth table operation, pulses from the information input of the demultiplexer 24 will not pass any input direct account or login count reversible counter 25. This situation is equivalent to the simultaneous operations of the forward and backward accounts reversible counter 25 (its content is not changed). Once on the entry permit account of the first 181the synchronization unit group will be a logic level zero, the pulses from the information input of the demultiplexer 24 will begin to enter the input of the inverse accounts is as reversible counter 25. The supply of pulses to the input count up / down counters 25 leads to the fact that its content is reduced. The output of the reversible counter 25 is connected to the first input of the comparison circuit 26, to the second input of which is the zero code. In time, when the content of the reversible counter 25 becomes zero, the output of the comparison circuit 26 sets the level of logical units. This time will be equal to (t1+Δτ). (As schemes can be used for comparison, for example, the chip CSP and its analogues. Cm. Digital integrated circuits: a Handbook / Mijajlovic, Ingel, Saurina and others - 2nd ed., revised and enlarged extra - Mn.: Belarus, Flame. S. RIS and 2.191). The level of logical units from the output of the comparison circuit 26 is supplied to the first input element And 27, to the second input of which receives the level of logical units with direct output of the first 23 RS-trigger. Thus at the output of the element And 27 level is set to a logical unit, which is supplied to the second input of the first element 22 OR next to the reset input of the first 23 RS-trigger. As a result, the direct output of the first 23 RS-flip-flop is set to logic level zero, which leads, naturally, to establish logic level zero and the output element And 27. All this leads to the output element And 27 and followed the Sabbath.) at the output of the sign of equality to zero of the first 181block synchronization at time (t1+Δτ) is a short pulse. Within the first 181the synchronization unit group short pulse from the output element And 27 is fed to the input of 29 installation of a second RS-flip-flop, and on its direct output level is set to a logical unit, which is supplied to the control input of the divider 30 with tunable division factor and allows him a job. This leads to the fact that at the output of divider 30 with tunable division factor will have a sequence of pulses with a repetition period Δτ=CT0. These pulses will correspond to points in time (t1+2Δτ), (t1+3Δτ), (t1+4Δτ)... the Pulses from the output of the divider 30 with tunable division factor arrives at the exit gate pulses of the first 181block synchronization group. The level of logical units with direct access 29 second RS-flip-flop is supplied also to the output characteristic of the issuance of the gate pulses of the first 181block synchronization group.

A short pulse from the output of the sign of equality to zero of the first 181a block group is synchronized to the input of the start of the second 182block synchronization group. The second 182and subsequent blocks 18 3-18Msynchronization group is similar to the first 181block synchronization group with the only difference that their enable inputs account connected to the corresponding outputs of the decoder 7. This leads to the fact that the outputs of the sign of equality to zero of the blocks 182-18Msynchronize a group of short pulses appear respectively at time (t2+Δτ), (t3+Δτ),..., (tM+Δτ). In accordance with this output the gate pulses of the second 182block synchronization group will have a sequence of pulses with a repetition period Δτ=kT0that will match the moments of time (t2+2Δτ), (t2+3Δτ), (t2+4Δτ)... output the gate pulses of the third 183block synchronization group will have a sequence of pulses with a repetition period Δτ=kT0that will match the moments of time (t3+ 2Δτ), (t3+3Δτ), (t3+4Δτ)... In the General case, the output gate pulse m-th 18mblock synchronization group will have a sequence of pulses with a repetition period Δτ=kT0that will match the moments of time (tm+2Δτ), (tm+3Δτ), (tm+4Δτ),..., hdem=1, 2, 3,..., M

The pulses from the outputs of the sign of equality to zero of the first (M-1) blocks 181-18M-1synchronization group are received at the respective inputs of the first 201(M-1)-Vodolaga OR. As a result, the output of the first 201(M-1)-Vodolaga item OR will have a serial stream of pulses, which correspond to the moments of time (t1+Δτ), (t2+Δτ),(t3+Δτ),..., (tM-1+Δτ). These pulses arrive at the input of the change of sign of the first 211the computing unit of the ordinate correlation (cross correlation) function.

The outputs of the sign of the issuance of the gate pulses and outputs the gate pulse M blocks 181-18msynchronization group are connected respectively to the inputs of the control and information inputs of the respective M distributors pulses 191-19mgroup. The structure of distribution pulses 191-19mgroup identical to the pulse distributor 16. The work of each of M distributors pulses 191-19mthe same group. Therefore, consider the operation in the example of the m-th 19m(m=1, 2, 3,..., M) of the pulse distributor group. The level of logical units from the output of the sign of the issuance of the gate pulse m-th 18mthe synchronization unit group arrives at the control input of the IHO 19 mthe pulse distributor group and allows him a job. This leads to the fact that the pulses received at time (tm+2Δτ), (tm+3Δτ), (tm+4Δτ),... output Gating pulses m-th 18mblock synchronization group on information input m-th 19mthe pulse distributor group, consistently pass on the outputs of the pulse distributor group. The first pulse corresponds to the time (tm+2Δτ), passes to the first output. A second pulse corresponding to the time (tm+3Δτ), passes to the second output, and so the Last (M-1)-th pulse corresponding to the time (tm+NΔτ)goes to (N-1)-th output. The last (N-1)-th pulse from the (N-1)-th output of the m-th 19mdistributor pulse group is received at the input termination of the m-th 18mblock synchronization group, where he and the second input of the second element 28 OR fed to the reset input of the second 29 RS-flip-flop and sets on its direct output logic level zero, which is supplied to the control input of the divider 30 with tunable division factor and forbids him a job. Thus, at the output of gate pulses and the output characteristic of the issuance of the gate pulse m-th 18mblock synchronization set is the same as a serviceable logical zero. A logic level zero output characteristic of the issuance of the gate pulse m-th 18mthe synchronization unit group arrives at the control input m-th 19mthe pulse distributor group and forbids him a job.

Pulses with n-x outputs (n=1, 2, 3,..., N-1) first (M-1) distribution pulses 191-19M-1the group arrives at the inputs of the (n+1)th 20n+1(M-1)-Vodolaga OR. As a result, the output of the (n+1)th 20n+1(M-1)-Vodolaga item OR receive a sequence of pulses corresponding to the time points (t1+(n+1)Δτ), (t2+(n+1)Δτ), (t3+(n+1) Δτ),..., (tM-1+(n+1)Δτ). So at the output of the second 202(M-1)-Vodolaga item OR will have a sequence of pulses corresponding to the time points (t1+2Δτ), (t2+2Δτ), (t3+2Δτ),..., (tM-1+2Δτ). The output of the third 203(M-1)-Vodolaga item OR will have a sequence of pulses corresponding to the time points (t1+3Δτ), (t2+3Δτ), (t3+3Δτ), ..., (tm-1+3Δτ). The output of the last N-th 20N(M-1)-Vodolaga item OR will have a sequence of pulses corresponding to the time points (t1+NΔτ), (t2+NΔτ), (t3+NΔτ),..., (tM-1+NΔτ).

In affect, the, the output of the n-th 20n(M-1)-Vodolaga element OR (n=1, 2, 3,..., N) we have a sequence of pulses, which determines the signal z2(t), delayed by the value of nΔτ. This sequence of pulses is fed to the input of the sign-change of the n-th block 21ncalculate the ordinate correlation (cross correlation) function.

Now consider the blocks 211-21Ncalculate the y-correlation (cross correlation) function.

The pulse from the first output of the pulse distributor 16 simultaneously with the input of the launch of the first 181the synchronization unit receives and to the input of the launch of the first 211the computing unit of the ordinate correlation (cross correlation) function. This impulse to direct the output of the RS-flip-flop 32 is set to the level of logical units, which is supplied to the second input element And 33 and permit the passage of clock pulses from the first input to the counting input of the reversible counter 37. Control the counting direction of the reversible counter 37 is the output 36 of the second element EXCLUSIVE OR. Consider the formation of this signal. The pulses from the output of the first 201(M-1)-Vodolaga element OR at time (t1+Δτ), (t2+Δτ), (t3+Δτ),..., (tM-1+Δτ) is fed to the input with the modern character of the first 21 1the computing unit of the ordinate correlation (cross correlation) function and, therefore, arrive at the counting input t of flip-flop 34. (As a T-flip-flop 24 can be used, for example, a trigger CTV. Cm. Nefedov AV Integrated circuits and their foreign counterparts: a Handbook. V.5. - M.: Goblet-a, 1997. - s). Recall that after the action of a start signal to direct the output of this trigger level is set to logical zero. At time (t1+Δτ), (t2+Δτ), (t3+Δτ),..., (tM-1+Δτ) is a sequential state transition T-flip-flop 24. The signal from the direct output of this trigger is supplied to the second input of the first 35 of the EXCLUSIVE OR element, the first input through the input characteristic of the initial state of the block is connected to the direct output of D-flip-flop 8, which stores the initial value of the signal z2(t), i.e. z2(t0). As a result, the output of the first 35 of the EXCLUSIVE OR element will have a signal corresponding to the output signal z2(t) 4 second comparator, but the detainee on the value Δτ, so this will be the signal z2(t-Δτ). The signal z2(t-Δτ) from the output of the first 35 of the EXCLUSIVE OR element is supplied to the second input 36 of the second element EXCLUSIVE-OR, at the first input of which receives the signal z1(t) output p is pout of the comparator 3. The second element 36 EXCLUSIVE OR performs the function of symbolic multiplication of signals z1(t) and z2(t-Δτ). If the signs of the signals z1(t) and z2(t-Δτ) coincide, the output 36 of the second element EXCLUSIVE OR will be a logic level zero. This means that the sum of these signals is equal to “+1”. If the signs of the signals z1(t) and z2(t-Δτ) are opposite, then the output 36 of the second element EXCLUSIVE OR will be present at the level of logical units. This means that the sum of these signals is equal to “-1”. The output signal 36 of the second element EXCLUSIVE OR fed to the control input of the counting direction of the reversible counter 37. When a logic level zero on this input will determine the direct expense of the reversible counter 37 (summation mode), and the level of the logic unit determines the count in reversible counter 37 (subtract mode). At time (tM+Δτ) pulse from the output of the sign of equality to zero of the last 18Ma block group is synchronized to the input termination of the account of the first 201the computing unit of the ordinate correlation (cross correlation) function and then to the first input of the OR element 31, with which it is supplied to the reset input of the RS-flip-flop 32. As a result, the direct output is de RS-flip-flop 32 is set to a logic level zero, which is supplied to the second input element And 33 and block the passage of clock pulses from the first input to the counting input of the reversible counter 37. To this point in time in the reversible counter 37 will have accumulated the number of SHu(Δτ), which determines the scorethe first ordinate mutual correlation function of the signalsand. Taking into account the constant coefficientincluded in the expression (5), assessment ofthe first ordinate mutual correlation function of the signalsandequal to

Work blocks 212-21ncalculate the y-correlation (cross correlation) function is similar to the work of the first 211the computing unit of the ordinate correlation (cross correlation) function. It should be noted only that the pulses at the inputs of the termination of the account blocks 212-21Ncalculate the y-correlation (cross correlation) function comes from the corresponding outputs of the last M-th pulse distributor 19mgroups, respectively, at time (tM+2Δτ), (tM+3Δτ),..., (tM+NΔτ). In the General case, in re erevnon the counter 37 of the n-th 21 nthe computing unit of the ordinate correlation (cross correlation) function accumulates the number of Sxy(nΔτ) in the binary code, which determines the scoren-th ordinate mutual correlation function of the signalsand. Taking into account the constant coefficientincluded in the expression (5), assessment ofn-th ordinate mutual correlation function of the signalsandequal to

The momentum from the last N-th output of the pulse distributor 16 is also fed to the reset input of RS flip-flop 17 and sets on its direct output logic level zero, which disables the operation of the divider 15 tunable division factor and the pulse distributor 16. The process of measuring the mutual correlation function Rxy(τ) completes.

The procedure for measuring the correlation function Rxx(τ) similar to the above process of measuring the mutual correlation function Rxy(τ). The difference lies only in the fact that the investigated centered random signalis supplied to both inputs of torrelamata, i.e. the input is, I can pay tithing 3 and 4 second Comparators. In the reversible counter 13 and in the reversible counters 37 blocks 211-21Ncalculate the y-correlation (cross correlation) function will be accumulated in the binary code, respectively, the number of Sxx(0) and Sxx(Δτ), Sxx(2Δτ), Sxx(3Δτ), ..., Sxx(NΔτ), which determine respectively the evaluationzero ordinate and evaluation,,,...,the next N y of the correlation function signal. Taking into account constant coefficient ofincluded in the expression (4), in the General case evaluationthe ordinate of the correlation function signalwill be equal to

where n=0, 1, 2, 3,..., N.

From the above description it is seen that compared with the device-the prototype of the proposed device has a simpler structure. The main operations are procedures for distributing pulses.

Technically, the proposed device is implemented on standard elements, widely known and used in modern technology. Moreover, at the present level of the development of the sociology of production of integrated circuits such device or its separate blocks (blocks synchronization distributors pulses and blocks compute y correlation (cross correlation) function), it is advisable to realize in the form of large-scale integrated circuits.

1. Parallel symbolic correlates containing the first and second generators are random uniformly distributed signals, the outputs of which are connected with the second inputs respectively of the first and second Comparators, the first inputs of which are respectively the first and second inputs of torrelamata, the output of the first comparator connected to the first input of the EXCLUSIVE OR element and with the information input of each of N blocks compute y correlation (cross correlation) function, the output of the second comparator is connected to the input of the shaper short pulses, with the second input of the EXCLUSIVE OR element and with the D-input of D-flip-flop, the clock input of which is connected to the input “start” torrelamata, and a direct output connected to the input of the sign of the initial state of each of the N blocks compute y correlation (cross correlation) function, the output of the shaper short pulses is connected to the counting input of the first binary counter, the output of which is connected to the address input of the decoder, the last (M+1)-th output of which is connected to the reset input of the first D-flip-flop, the input set which is connected to the input “start” KOR is lumetra, and a direct output connected to the first input element And the enable input of the decryption decoder with enable inputs account of the first and second binary counters, the output of the generator of clock pulses is connected to the counting input of the divider with a configurable dividing ratio, the second input element And, with a counting input of the second binary counter and the counting inputs of N blocks compute y correlation (cross correlation) function, the output element And is connected to the counting input of the reversible counter, the control input counting direction of which is connected to the output of the EXCLUSIVE OR element, the inputs of resetting the first and second binary counters, input reset reverse counter inputs and initial installation of all N blocks compute y correlation (cross correlation) function of the joint and is connected to the input “start” correlate, the output of the second binary counter is one of the outputs of torrelamata and carries information about the duration of the measurement time, the output of the reversible counter is the exit assessment to the zero ordinate correlation (cross correlation) function, set the input of the divider with a configurable dividing ratio is connected to the input “start” correlate, and the reference input division factor is the reference input step delay measurement the Oia correlation (cross correlation) functions correlate, the control input of the divider with a configurable dividing ratio and the control input of the pulse distributor United and connected to the direct output of the second RS-flip-flop, the input set which is connected to the input “start” correlate, the output of the divider with a configurable dividing ratio is connected with the information input of the pulse distributor, the N outputs of which are connected with inputs of launch of the respective N blocks compute y correlation (cross correlation) function, the last N-th output of the pulse distributor is connected to the reset input of the second RS-flip-flop, the outputs of the N (M-1)-vchodove elements OR connected to inputs of sign change of the corresponding blocks calculate the y-correlation (cross correlation) function, which outputs outputs are estimates of the corresponding ordinates of the correlation (cross correlation) function, characterized in that it introduced the group containing M blocks synchronization, and a group containing M distributors pulses, with the first M outputs of the decoder are connected to the enable inputs of the account corresponding to the M blocks of the synchronization group, the inputs of the task of the issuing period gate pulse M blocks synchronization group are United and connected to the reference input of the step delay measurement correlation (cross correlation) is uncle of torrelamata, inputs initial setup of the M blocks of the synchronization group are United and connected to the input “start” torrelamata, counting input of the M blocks of the synchronization group are United and connected to the generator output clock, the first output of the pulse distributor is connected to the input of the start of the first block group is synchronized, the output of the sign of equality to zero of the previous synchronization unit group is connected to the input of the start of the subsequent synchronization unit group, the output of the sign of equality to zero of the last M-th synchronization unit group is connected to the input of the termination of the account of the first computing unit of the ordinate correlation (cross correlation) function, the outputs of the sign of equality to zero the first M-1 blocks synchronization group connected to inputs of the first (M-1)-Vodolaga element OR the output characteristic of the issuance of the gate pulse M blocks synchronization group is connected to the control inputs of the respective M distributors pulse group, and outputs the gate pulse M blocks synchronization group are connected to information inputs of the respective M distributors pulse group, n-e outputs (n=1,2,3,...,N-1) the first M-1 distributors pulse groups are connected with the inputs of the (n+1)th (M-1)-Vodolaga element OR, (N-1)-th output each of the distributors pulse group is connected to the input termination servant whom you are corresponding synchronization unit group, n-th output (n =1,2,3,...,N-1) the last M-th pulse distributor group is connected to the input of the termination of the account (n+1)-th computing unit of the ordinate correlation (cross correlation) function.

2. Parallel symbolic correlated according to claim 1, wherein the synchronization unit includes first and second elements OR the first and second RS-trigger, a demultiplexer, and a reversible counter, And a comparison circuit and a divider with a configurable dividing ratio, and the information input of the demultiplexer and the counting input of the divider with a configurable dividing ratio combined and are counting input of the synchronization unit, the first address input of the demultiplexer is an entry permit account of the synchronization unit, the first inputs of the first and second elements OR input reset the reversible counter and set the input of the divider with a configurable dividing ratio are combined and input the initial installation the synchronization unit, the input set of the first RS-flip-flop is the input of the start of the synchronization unit, the second input of the second element OR an input termination of the synchronization unit, the reference input of the divider with a configurable dividing ratio is the reference input of the issuing period Gating pulses of the synchronization unit, the output of the first e is ementa OR connected to the reset input of the first RS-flip-flop, direct the output of which is connected with the second address input of the demultiplexer and the second input element And first and second outputs of the demultiplexer are connected respectively to the inputs of the forward and backward accounts reversible counter whose output is connected to the first input of the comparison circuit, the second input of which is the zero-code output of the comparison circuit connected to the first input element And the output of which is connected with the second input of the first element OR to the input of the second D-flip-flop and an output of the sign of equality to zero of the synchronization unit, the output of the second element OR is connected to the reset input of the second RS-flip-flop, direct which is connected to the control input of the divider with a configurable dividing ratio is the output characteristic of the issuance of the gate pulses of the synchronization unit, the output of the divider with a configurable dividing ratio is the output of the Gating pulses of the synchronization unit.



 

Same patents:

FIELD: specialized information extracting means.

SUBSTANCE: device has displacement registers, comparator block, XOR element, multiplexer, triggers, counter, AND elements.

EFFECT: simplified construction.

1 dwg

The invention relates to the field of computer engineering and can be used to process a random process

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The invention relates to the field of computer engineering and can be used for analysis of random processes

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FIELD: specialized information extracting means.

SUBSTANCE: device has displacement registers, comparator block, XOR element, multiplexer, triggers, counter, AND elements.

EFFECT: simplified construction.

1 dwg

FIELD: computer science.

SUBSTANCE: device has first and second regenerators of random evenly spaced signals, second and first comparators, generator of short pulses, second and first binary counters, decoder, D-trigger, first and second RS-triggers, AND element, XOR element, reverse counter, clock pulse generator, divider with rebuilt division coefficient , pulse distributor, group of M synchronization blocks, group of M pulse distributors, N (M-10) - input elements R and N blocks for calculating ordinates of correlation function.

EFFECT: simplified construction and higher reliability .

2 cl, 4 dwg, 1 tbl

FIELD: the invention refers to the technique of detection of a target and determination of the direction at a target.

SUBSTANCE: the mode is realized by way of receiving of ultra wideband impulses reflected from the target, of delaying them on various time multitude in various channels of surveillance and multi channel processing. In the first variant of the current mode variation of the form of receiving impulses on a great number of discrete time positions are carried out by way of averaging-out by channels of surveillance at known direction of incoming reflected impulses in a beforehand designed control sector and then found valuation of the form of receiving impulse is used as a base signal in multi channel correlation processing. In the second variant valuation of magnitude of receiving impulse is formed in concrete moment of time for each base direction in beforehand given angular sector of control, valuation of the form of the receiving impulse is found according to formed valuations of magnitude 0f the receiving signal for various discrete moments of time; found valuation of receiving impulse is used as a base signal in multi channel correlation processing; out of multitude of results of correlation processing correlation maximum is chosen. This maximum is used as preliminary threshold decision statistics in the procedure of detection of the target; the direction of incoming reflected impulses with the help of interpolating valuation of the position of the correlation maximum in the environs of that base direction for which the largest result of multi channel correlation processing.

EFFECT: the use of this invention at location of a target with the help of ultra wideband impulses allows to receive signals incoming not only from in advance chosen base directions.

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FIELD: data processing in broadband radio communications and radio navigation.

SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.

EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.

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FIELD: engineering of specialized devices, meant for determining correlation functions of random processes.

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EFFECT: increased precision of multi-channel polar correlator, expanded functional capabilities of correlator due to introduction of mode for determining mutual correlation function of two signals.

1 dwg

FIELD: navigation techniques.

SUBSTANCE: when forming an image of a surface, on which a sensor is moving, components of the image with spatial wavelength less than twice the size of the optical cell are destroyed, before calculation of shift between the reference and the current frames on the discrete set of numbers Arefij and Acurij, stored in the first and second memory buffers. Initial continuous functions Aref(x,y), Acur(x,y) are restored, and then the shift between the frames is calculated by comparing the restored continuous functions.

EFFECT: increased accuracy and resolution capacity of calculating shift.

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FIELD: physics; radio-technology.

SUBSTANCE: invention pertains to radio-technology, and particularly to optimum receiving of pseudonoise signals. The technical outcome is the increased resistance to interference of the output signal. According to the method, the radio frequency oscillation is converted to the video frequency range. The signal envelope is separated, sampled on time and amplitude on two levels, "1" and "0". The obtained code is recorded in an n-bit shift register of a discrete matched filter, matched by a direct code, and a discrete matched filter, matched by an inverse code. The automatic correlation function of the received signal is generated by removing the constant component from the result of adding output signals of the indicated discrete matched filters. The device which implements the method consists of a multiplier (1), low-pass filter (2), bidirectional limiter (3), cascade for coinciding with "1" (4), cascade for coinciding with "0" (8), inverter (7), n-bit shift registers (5,9), n-input adders (6,10), dual input adder (11), device for removing constant component (12), polling clock pulse source (T). At the first n-bit shift register and the first n-input adder there is discrete filter, matched by a direct signal code, and at the second n-bit shift register and the second n-input adder there is a discrete filter, matched by an inverse signal code.

EFFECT: increased resistance to interference of the output signal.

2 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: invention can be used for detection of complex signals in those radio-technical systems which are not capable to change signal phase quickly. Method for detection of Barker signal in matched filter which signal is modified by substitution "-1" elements for "0" elements consists in following. Received signal is filtered in auxiliary filter matched relatively to one signal position, delayed in time-delay circuit where delay between it's branches is equal to duration of one signal position. Corresponding elements of received signal code and elements of reference code are added one-by-one by modulo 2. Results of additions are inverted, summed, and in accordance with summing results the decision about detection is made.

EFFECT: possibility to process complex signals with constant phase.

2 dwg

FIELD: education.

SUBSTANCE: method consists in the following: placing on the monitor of a control question and versions of the answer to the given question, a choice of one, preferable trained, a version of the answer by means of moving of the manipulator cursor to the location of its indicator and the subsequent definition of correctness of the answer on a final cursor position; after placing of indicators of versions of answers in the range from the moment of the cursor movement beginning till the moment of fixing of its final position form a file trajectory parametres of its movement on the monitor, determine autocorrelation function of the obtained array of trajectory parametres and determine level of confidence of the trained person in the obtained knowledge by position of a maximum of function at which arrangement within the set error of decision-making in the beginning of co-ordinates gives the conclusion about the confident or uncertain motivation of the answer.

EFFECT: increase of reliability and accuracy of the control of obtained knowledge level.

5 dwg

FIELD: physics; computer facilities.

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EFFECT: provision of fault-free object following at occurrence of sudden failures in the correlator at the expense of identification of failure of tracing by the correlator and automatic transmission to the given situation of priority of a number system of coordinates.

1 dwg

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