Noise-immune cyclic code codec

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

 

The invention relates to the field of communication technology and can be used in data transmission systems, and in systems, telemetering and telecontrol for the transmission of information without the prior phase.

Codec or encoder and the decoding device described in this application, is used for encoding and decoding linear error-correcting cyclic codes, as well as for frame synchronization of these error-correcting codes. In the proposed device to the communication channel to transmit the sequence of symbols is equal to the sum of symbol error correcting code and symbol synchronization sequence. Cyclic synchronization is performed using a synchronization sequence imposed on the error-correcting code, and therefore, transmission of redundant additional symbols for synchronization purposes is not required.

After the establishment of synchronization, the synchronization sequence is removed from error-correcting code, without reducing the correcting ability of the code.

Currently, digital communication channels ultrashortwave and UHF ranges, in particular satellite channels, characterized by large amounts of transmitted information. Moreover, the speed of information processing in the newly introduced lines is 120 Mbit/s and more. Information in the temporary systems, using computers, can be transmitted on the data bus in parallel code that places high demands on the performance of the codec error correcting codes.

When the codec error correcting cyclic code group paths multichannel communication systems and methods polybasic modulation, in which each channel symbol corresponds to several bits of information messages are also passed in parallel code and must provide high speed processing of information on transmitting and receiving sides of the line.

In this regard, the main task is to create a codec error correcting cyclic code with high performance and does not require a large number of operations for encoding and decoding messages, and also for establishing frame synchronization.

Known codec error correcting cyclic code, containing on the transmission side driver information part code word consisting of a shift register, connected to the modulo two, and the clock shaper part of the code word, and outputs shapers connected to the modulo two parts of the code words, and at the receiving side containing the binary filter information part code with the ova, consisting of a shift register, connected to the adders modulo two, and the decoder (ed. St. USSR №365033, CL N 03 To 13/04 was investigated, publ. 1973).

However, this device has a low performance due to the fact that the message encoding error-correcting code requires a large amount of shifts of the input information, equal at least to the number of check symbols in the code word, and for decoding error-correcting code, the number of shifts shall be not less than the number of symbols in error correcting code.

Closest to the proposed device is a codec error correcting cyclic code (prototype), containing on the transmission side driver information part code word consisting of memory elements of the shift register and modulo two driver information part code words, the clock shaper part of the code word and the modulo two information and synchronize the parts of the code words, and the inputs of the memory elements of the shift register are information input device, the output of the last memory element of the shift register and the output of the shaper clock part of the code word are connected with inputs of modulo two information and synchronize the parts of the code words, the output of which is connected with link the output of the adder modulo two driver information part of the code word is connected to the input of the first memory element of the shift register, at the receiving side containing the binary filter consisting of memory elements of the shift register binary filter and modulo two binary filter, the shift register information part of the codeword, the decoder, the memory and the block error correction, while the drive is connected to the output of the modulo two binary filter, the output drive is connected to the decoder and the input of block error correction, the output of the decoder is connected to the input of block error correction and is output synchronization device, the input of the first memory element of the shift register binary filter is connected to the communication channel and the input of the modulo two binary filter, the output of the last the memory element of the shift register binary filter connected to the input of the shift register information part code words, the output of which is an information output device (ed. St. USSR №809550, CL N 03 To 13/04 was investigated, publ. 1981).

A disadvantage of this device is poor performance, due to the fact that information when encoding and decoding the messages are in sequential code, and one cycle of the operating frequency of the devices can process a single bit of data or one bit of word error correcting code.

The purpose of the present invention is to improve performance of the device due to the CSOs, what input and output are in series-parallel code for one cycle of the operating frequency of the devices can process a group of m(m>1) bit input encoding or decoding device.

To achieve the goal proposed codec error correcting cyclic code, containing on the transmission side driver information part code word consisting of memory elements of the shift register and modulo two driver information part code words, the clock shaper part of the code word and the modulo two information and synchronize the parts of the code words, and the inputs of the memory elements of the shift register are information input device, the output of the last memory element of the shift register and the output of the shaper clock part of the code word are connected with inputs of modulo two information and synchronize the parts of the code words, the output of which is connected to the communication channel, the output of the adder modulo two driver information part of the code word is connected to the input of the first memory element of the shift register at the receiving side containing the binary filter consisting of memory elements of the shift register binary filter and modulo two binary filter, case, SD is the yoke of the information part of the code word, decoder, the memory and the block error correction, while the drive is connected to the output of the modulo two binary filter, the output drive is connected to the decoder and the input of block error correction, the output of the decoder is connected to the input of block error correction and is output synchronization device, the input of the first memory element of the shift register binary filter is connected to the communication channel and the input of the modulo two binary filter, the output of the last memory element of the shift register binary filter connected to the input of the shift register information part code words, the output of which is an information output device. What's new is that on the transmission side put blocks calculate validation parts of the error-correcting code driver information part code words whose inputs are connected to outputs of the memory elements of the shift register and the outputs of blocks calculate validation parts of the error-correcting code driver information part code words are connected with the inputs of the modulo two driver information part code word, at the receiving side put blocks calculation of the test pieces of error-correcting binary code of the filter unit forming the synchronizing part of the code words and blocks adders on fashion what Yu two, moreover, the inputs of blocks calculation of the test pieces of error-correcting binary code of the filter is connected to the outputs of the memory elements of the shift register binary filter, the outputs of blocks calculation of the test pieces of error-correcting binary code of the filter are connected to the inputs of the modulo two binary filter, the output of the decoder is connected to the input processing unit clock part of the code words whose outputs are connected to first inputs of blocks adders modulo two, the second inputs of which are connected to the outputs of block error correction, the outputs of blocks adders modulo two is connected with the inverting inputs of the shift register information part code word.

The drawing shows a structural diagram of the device.

On the transmitting side codec error correcting cyclic code (the encoder) contains driver information part code word 1, consisting of memory elements of the shift register 2, blocks calculate validation parts of the error-correcting code driver information part code word 3 connected to the modulo two driver information part code word 4, modulo two information and clock parts code words 5 and the clock shaper part of the code word 6.

At the receiving side codec error correcting cyclic code (decoding device) contains the binary filter 7, consisting of a modulo two binary filter 8, blocks, computing a test parts of the code word is a binary filter 9 connected to the memory elements of the shift register binary filter 10, the shaping unit synchronizing part of the code word 11, a memory 12, a block error correction 13, blocks adders modulo two 14, the shift register information part code word 15, a decoder 16.

The proposed device operates as follows.

On the transmission side form the output sequence. To do this, the original message volume k symbols of the first code for error-correcting cyclic code. A coding information get the word cyclic code C(n,k)=C0with1,...,n-1information whose length is k symbols and the block of n symbols.

The number of memory elements of the shift register 2 in the driver information part code word 1 in the device corresponds to the number of symbols k in the original information sequence, for which an error correcting code. The number of bits in each memory element in the shift register 2 is equal to m and the total number of memory elements of the shift register 2 p is the set s=k/m.

First, the original information sequence of k characters, comes in parallel to the input device, and the characters of this information sequences are written in the memory elements of the shift register 2.

To describe the operation of the device will present background information in the form of an information polynomial f(x), the coefficients of which are the information symbols.

Check the part of r(x) word error correcting cyclic code in polynomial notation can be written in the form

where g(x) is the generating polynomial of the error-correcting cyclic code of degree n-k.

Information part of the error correcting code in accordance with the procedure of recording it in the shift register 2, consisting of s m bit groups of memory elements may be represented in the form

where fi(x) is the i-th m-bit component information part code written in the corresponding i-th m-bit memory element of the shift register 2, s is the total number of memory elements of the shift register 2 (k=m× s).

Substituting equation (2) in (1), we obtain a test portion of the error correcting code in the form

and the first (senior) m bits of the test parts of the code will be equal to

where [ ]mdenotes the first m bits of the polynomial.

Calculate the check character error-correcting code in the driver information part of the codeword of the coding device is carried out in accordance with the equation (4).

To do this, each group of characters that are in the memory elements shift register 2, i.e. the i-th m-bit component information part code fi(x) applied to the inputs of the i-th computing unit test parts of the error-correcting code driver information part code word 3.

Each computing unit test part of the error correcting code of the driver information part code word 3 can be made in the form of a storage device, such as the permanent storage device (ROM). The inputs of the blocks calculate the test part of the code word 3 are address inputs of the ROM outputs - ROM contents located at this address.

In the i-th computing unit test part of the code word 3 define the i-th summand [fi(x)n-kmod g(x)]mthat is part of the equation (4). In the i-th computing unit test part of the code word 3 (in ROM) is one and the same information, and it contains a table consisting of 2mrows. The address input of the ROM is the i-th m-bit component information part code i(x), and the contents of the cells of the ROM with this address will be [fi(x)xn-kmod g(x)]m.

The corresponding contents of the ROM form in advance by rule

fi(x)→ [fi(x)xn-kmod g(x)]m

and the output of the ROM is the i-th m-bit component test parts of the code, which is included in equation (4).

After calculation blocks calculation of the test parts of the error-correcting code driver information part code word 3 tables, the ROM, all components of the test part of the error-correcting code [fi(x)xn-kmod g(x)]m, i=1... s, carry out the determination of the first m bits of the test parts of the code. For this purpose, in accordance with equation (4) components of the test part of the error correcting code generated at the outputs of blocks calculate the test part of the code word 3 summarize the modulo two driver information part code words 4.

At the same time form a continuous cyclic synchronizing sequence of length n symbols. Such a sequence can be any sequence of suitable length with good timing properties, such as the sequence of maximal length code (reed-Muller 1-th order) form a polynomial r(x)

D(n)=d0d1,... ,dn-1

Synchronizing follow etelnost get in the clock shaper part of the code word 6. The clock shaper part of the code words 6 can be performed, for example, in the form of a ROM, in which recorded continuous synchronization sequence.

The symbols of the output sequence on the transmitting side

In(n)=b0b1,... ,bn-1

get the addition modulo two characters cyclic error-correcting code with symbols synchronizing sequence:

bi=Cidi, i=0... n-1

The summation symbol code characters synchronizing sequence is carried out modulo two information and clock parts code word 5. Output of this adder symbols of the output sequence are received in the communication channel.

At the receiving side adopted a sequence of errors in the communication channel may be different from the transmitted sequence B(n).

At the receiving side symbols of the received sequence are received first in a series-parallel code groups m symbols at the input of the binary filter 7. The characters of the received sequence is written in the first memory element of the shift register binary filter 10. Blocks calculation of the test parts of the code word is a binary filter 9 and the modulo two binary filter 8 are similar to the corresponding blocks and the sum of the ROS driver information part code word 1 of the transmitting side codec. Modulo two binary filter 8 calculates the syndrome of the error-correcting cyclic code, i.e. the sum modulo two of the test code symbols, calculated according to the information symbols, and the received check symbols. Upon receipt of error-free code word, the syndrome code is zero and the result of the calculation of the syndrome will be received and converted into a binary filter 7 is transmitted to the synchronization sequence. Upon receipt of the input words with errors will be calculated combination of a set of binary combinations, corresponding to the sum of the non-zero syndrome error correcting code and converted synchronizing sequence.

The converted synchronization sequence with the imposed syndrome from the output of the modulo two binary filter 8 and then goes into the drive 12.

At the same time from the output of the last memory element of the shift register binary filter 10 of the information sequence received at the input of the shift register information part code word 15.

The drive 12 is connected to the decoder 16 that is configured on the structure of the synchronizing sequence given syndrome code corresponding to a combination of errors allowable ratio. It is permissible number of errors is determined by correcting ability is the institutional capacity of error-correcting code or the minimum code distance of error-correcting code. The selection of a subset of the decrypted error takes into account the propagation of channel errors caused by the passage through the binary sequence filter 7.

The operation of decoder 16 indicates the reception of the synchronizing sequence with the maximum allowable frequency error and a certain phase shift. In the shift register information part code word 15 will be with the same phase shift information symbol error correcting cyclic code.

The location of the error in the code symbols is determined by the (localized) block error correction 13 in recognition of the correct combination of syndrome code imposed by a synchronization sequence. Block error correction 13 can be performed, for example, in the form of a persistent storage device (ROM)in which is recorded the errors table. The address input of the ROM is a binary combination corresponding to the combination syndrome superimposed synchronization sequence and a given phase shift, and the output of the ROM, the corresponding binary combination of errors in the information symbols of the code word.

This allows correction of erroneous characters in the shift register information part code word 15.

Simultaneously, the outputs of the decoder 1 is fed to a forming unit which synchronizes part of the code words 11. With the release of this block synchronization sequence with a certain phase shift arrives at the inputs of blocks summation modulo two 14, to the other inputs of which the output of block error correction 13 served binary combination corresponding to the location of errors in the information symbols of the code word.

Correcting errors in the shift register information part code word 15 and removing the synchronizing sequence is controlled by signals from the outputs of blocks adders modulo two 14 by inversion of the corresponding bits in the received code word.

At the moment of appearance of the signal output from the decoder 16 in the shift register information part code word 15 will be information symbols error-correcting cyclic code. Therefore, the output signal from the decoder 16 is a synchronizing signal, indicating that the decoded information from the output of the shift register information part code word 15 is supplied to the codec output and can be read by the information recipient.

Note that the imposition of a synchronizing sequence for the code word gives the words of the error correcting code property samsungringtones and does not require the introduction of additional redundancy in the error-correcting code for alacyclovir synchronization.

The proposed device can be implemented as hardware and hardware-software means. In the latter case, the use of a separate computer elements (adders, memory, registers) allows you to get a significant benefit in the amount of equipment used.

In the proposed invention, unlike the known device, information processing is carried out in a series-parallel code, and for one step is processed one symbol error correcting cyclic code, as in the prototype, and a group of m (m>1 characters, which increases the operating speed of the device is approximately m times.

Achievable technical result of the proposed codec error correcting cyclic code is to improve its performance.

Codec error correcting cyclic code, containing on the transmission side driver information part code word consisting of memory elements of the shift register and modulo two driver information part code words, the clock shaper part of the code word and the modulo two information and synchronize the parts of the code words, and the inputs of the memory elements of the shift register are information input device, the output of the last memory element of the shift register and the output of the shaper clock part of the code word are connected with inputs of modulo two information and synchronize the parts of the code words, the output of which is connected to the communication channel, the output of the adder modulo two driver information part of the code word is connected to the input of the first memory element of the shift register at the receiving side containing the binary filter consisting of memory elements of the shift register binary filter and modulo two binary filter, the shift register information part of the codeword, the decoder, the memory and the block error correction, while the drive is connected to the output of the modulo two binary filter, the output drive is connected to the decoder and the input of block error correction, the output of the decoder is connected to the input of block error correction and is output the synchronization device, the input of the first memory element of the shift register binary filter is connected to the communication channel and the input of the modulo two binary filter, the output of the last memory element of the shift register binary filter connected to the input of the shift register information part code words, the output of which is an information output device, characterized in that on the transmission side put blocks calculate validation parts of the error-correcting code driver information part code words whose inputs are connected to outputs of the memory elements of the shift register and the outputs of blocks in which the calculations of the test parts of the error-correcting code driver information part code words are connected with the inputs of the modulo two driver information part code words, at the receiving side put blocks calculation of the test pieces of error-correcting binary code of the filter unit forming the synchronizing part of the code words and blocks adders modulo two, and the inputs of blocks calculation of the test pieces of error-correcting binary code of the filter is connected to the outputs of the memory elements of the shift register binary filter, the outputs of blocks calculation of the test pieces of error-correcting binary code of the filter are connected to the inputs of the modulo two binary filter, the output of the decoder is connected to the input processing unit clock part of the code words whose outputs are connected to first inputs of blocks adders modulo two, the second inputs of which are connected to the outputs of block error correction, and outputs blocks adders modulo two is connected with the inverting inputs of the shift register information part code word.



 

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