Flip-flop device


H03K3/286 - PULSE TECHNIQUE (measuring pulse characteristics G01R; mechanical counters having an electrical input G06M; information storage devices in general G11; sample-and-hold arrangements in electric analogue stores G11C0027020000; construction of switches involving contact making and breaking for generation of pulses, e.g. by using a moving magnet, H01H; static conversion of electric power H02M; generation of oscillations by circuits employing active elements which operate in a non-switching manner H03B; modulating sinusoidal oscillations with pulses H03C, H04L; discriminator circuits involving pulse counting H03D; automatic control of generators H03L; starting, synchronisation, or stabilisation of generators where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
H03K3/037 - PULSE TECHNIQUE (measuring pulse characteristics G01R; mechanical counters having an electrical input G06M; information storage devices in general G11; sample-and-hold arrangements in electric analogue stores G11C0027020000; construction of switches involving contact making and breaking for generation of pulses, e.g. by using a moving magnet, H01H; static conversion of electric power H02M; generation of oscillations by circuits employing active elements which operate in a non-switching manner H03B; modulating sinusoidal oscillations with pulses H03C, H04L; discriminator circuits involving pulse counting H03D; automatic control of generators H03L; starting, synchronisation, or stabilisation of generators where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flops 1, 2 built around NOR gates 22, 23, 26, 27, and also NOR gates 4, 5, control device 3, diodes 10, 11, resistors 12 - 17, capacitors 6 - 9, memory elements 18, 19 built around rectangular hysteresis loop cores each incorporating write winding and read winding, at least one input bus 20, and common bus 21. Newly introduced in device are RS flip-flop 2, diodes 10, 11, and capacitors 8, 9).

EFFECT: enhanced immunity to persistent intensive noise.

1 cl, 2 dwg

 

The invention relates to a pulse technique and can be used in computer equipment and control systems.

Known trigger device (see USSR author's certificate No. 1753919 from 05.10.90, MKI: N 03 To 3/037 "Trigger device", the authors LB Egorov, G.I. Shishkin, publ. 10.09.97, bull. No. 25), containing the first and second memory elements, magnetic cores, the outputs of the windings reading which is connected with the common bus, the input windings record connected respectively with direct and inverse outputs of the element "Exclusive OR", the first and the second input of which is connected to the input bus and the output of the RS-flip-flop, respectively, the inputs set and reset which are connected respectively through first and second resistors to the input windings of the read first and second memory elements, respectively. The first control unit is connected to the input bus, the second and third inputs of the control unit are connected respectively with direct and inverse outputs of the element "Exclusive OR", and the first and second outputs of the control unit respectively through the third and fourth resistors connected to the outputs of the windings recording respectively the first and second memory elements.

The disadvantage of this trigger device is a relatively low immunity under the influence of high-intensity e is krichesky interference long duration, induced by chains of communication.

Known trigger device (see RF patent №2106742 from 16.08.95, MKI: N 03 To 3/286 " Trigger device", the authors Eyiah, Geesken, publ. 10.03.98, bull. No. 7), which is the closest to the technical nature of the claimed object and selected as a prototype, containing RS-trigger inputs set and reset which are connected with the first pins of the first and second resistors, respectively, and respectively through the first and second capacitors with a common bus, and direct and inverted outputs connected to first inputs respectively of the first and second elements of the "Exclusive OR", second input which is connected to the input bus trigger device, and outputs connected to inputs of the windings recording respectively the first and second memory elements, magnetic cores, an input winding of reading which are connected to a common bus, the first and second elements, the third and fourth elements of the "Exclusive OR", third, fourth, fifth and sixth resistors. RS-trigger executed on the elements. The outputs of the first and second elements of the "Exclusive OR" is connected with the first inputs respectively of the third and fourth elements of the "Exclusive OR", the outputs of which respectively through third and fourth resistors connected to the outputs of the windings recording respectively the first and the second e is the memory elements, the outputs of the windings reading through which respectively the fifth and sixth resistors connected to the first inputs respectively of the first and second elements AND whose output is connected with the second pins respectively of the second and first resistors and second inputs, respectively, the third and fourth elements of the "Exclusive OR". The second inputs of the first and second elements AND IS NOT incorporated and is connected to the input bus trigger device.

The disadvantage of the prototype is relatively low immunity under the influence of high-intensity electrical noise long duration induced by chains of communication. The memory elements on the magnetic cores provide a trigger device, the property of independence, however, such a triggering device is resistant to electrical noise induced by chains of communication, the duration of which does not exceed the time of magnetization reversal cores. When performing memory elements in acceptable dimensions specified time is small (less than 10-20 microseconds), therefore, the trigger device will stray from disturbances pulses of greater duration.

The problem solved by the claimed invention is to increase the noise immunity of the trigger device in conditions of high-intensity electric is a mini-interference long duration.

This technical result is achieved in that the trigger device containing the first RS-flip-flop, a control device with at least three inputs and three outputs, the first and second inputs of the control devices connected respectively with the forward and inverse outputs of the first RS-flip-flop, a third input from the input bus and the first output with the first inputs of the first and second points of convergence, the second inputs of which are connected with the first pins respectively of the first and second resistors, first and second capacitors, the first conclusions which are connected to a common bus, the first and second the memory elements on magnetic cores with rectangular hysteresis loop, each of which has a coil account and winding of reading, and the input windings of the first and second memory elements are connected with the first conclusions of the third and fourth resistors, respectively, the input windings of the read first and second memory elements are United and connected to the shared bus, fifth and sixth resistors, what is new is the introduction of the first and second diodes, the third and fourth capacitors, a second RS-trigger, and reset inputs of the installation which are connected respectively with the second and third outputs of the control device, a direct output connected to the output winding of the second recording the memory element with the which the output of the third resistor and the first output of the fifth resistor, inverted output is connected to the output winding of the first memory element with the second output of the fourth resistor and the first output of the sixth resistor, the output winding of reading the first memory element is connected to the cathode of the first diode and the third capacitor to the second output of the fifth resistor and the second output of the second resistor, the output winding of the second reading of the memory element is connected to the cathode of the second diode and a fourth capacitor to the second output of the sixth resistor and the second output of the first resistor, the second the findings of the first and second capacitors are connected with the second pins of the first and second points of convergence, respectively, the outputs of which are connected respectively to the inputs of the reset and setup of the first RS-flip-flop, the anodes of the first and second diodes connected to a common bus, the first and second points of convergence in the form of elements OR NOT.

This set of essential features can improve the noise immunity of the trigger device by storing its state using the optional capacitive memory elements, and then recover.

Figure 1 shows the circuit diagram of a trigger device controlled by one input bus (counting trigger device). Figure 2 presents principalin the I electric circuit controlling device, allows you to organize RS-trigger device, controlled by two input buses. Counting the trigger device (1) includes RS-triggers 1 and 2, the control device 3, the logical elements 4 and 5 OR NOT, capacitors 6, 7, 8 and 9, the diodes 10 and 11, resistors 12, 13, 14, 15, 16 and 17, the elements 18 and 19 memory on magnetic cores with rectangular hysteresis loop (BCP), each of which includes the winding of the recording and the coil read input bus 20 and bus 21. The reset inputs (R input) and installation (S input) RS-flip-flop 1 is connected respectively to the outputs of the elements 4 and 5 OR NOT. Direct (Q) and inverse () outputs RS-flip-flop 1 is connected respectively with the first and second inputs of the control unit 3, a third input connected to the input bus 20, the first output is connected with the first inputs of the elements 4 and 5 OR NOT, and the second and third outputs respectively connected to the reset inputs and an RS-flip-flop 2. The second input element 4 through the condenser 6 is connected to the common bus 21 and through a resistor 13 with the connection point of resistor 17 and capacitor 9. The second input element 5 through a capacitor 7 is connected with the common bus 21 and through a resistor 12 with the connection point between the resistor 15 and capacitor 8. Direct (Q) output RS-flip-flop 2 is connected to the output winding of the recording element 19 memory with the free output resistor 15 and one of the conclusions of easistore 14, the other output of which is connected to the input winding of the recording element 18 of the memory. Inverse () output RS-flip-flop 2 is connected to the output winding of the recording element 18 memory with the free output resistor 17 and to one of the terminals of the resistor 16, the other output of which is connected to the input winding of the recording element 19 memory. The free lead of the capacitor 8 is connected to the cathode of the diode 10 and the output winding of the read element 18 of the memory. The free lead of the capacitor 9 is connected to the cathode of the diode 11 and the output winding of the read element 19 memory. The anodes of the diodes 10 and 11 and the input windings of the read elements 18 and 19 memory combined and connected to the common bus 21.

RS-trigger 1 contains elements 22 and 23 OR NOT, the first inputs of the elements 22 and 23 are respectively reset inputs and an RS-flip-flop 1, the outputs of the elements 22 and 23 are respectively the direct and inverse outputs RS-flip-flop 1, the second inputs of the elements 22 and 23 are connected respectively to the outputs of the elements 23 and 22. The control device 3 includes items 24 and 25 of the "Exclusive OR", the first inputs of the elements 24 and 25 are respectively the first and second inputs of the control device 3, the second inputs of the elements 24 and 25 are combined and the third input and the first output control unit 3, and the outputs of the elements 24 and 25 are respectively in the verge and the third output control unit 3. RS-trigger 2 contains elements 26 and 27 OR NOT, the first inputs of the elements 26 and 27 are respectively reset inputs and an RS-flip-flop 2, the outputs of the elements 26 and 27 are respectively the direct and inverse outputs RS-flip-flop 2, the second inputs of the elements 26 and 27 are connected respectively to the outputs of the elements 27 and 26.

The control unit 3 allowing to organize RS-trigger device, includes (2) items 28, 29, 30 and 31 OR NOT, the element 32 "Exclusive OR", while the input elements 28 and 29 are respectively the first (33) and second (34) inputs of the control unit 3, and outputs connected respectively to the first inputs of the elements 30 and 31. The second input element 29 is connected with the second input element 30, with the first input element 32 and is third (35) of the input control device 3 that performs in the trigger device role R input. The output element 32 is the first (36) output control unit 3. The outputs of the elements 30 and 31 are, respectively, the second (37) and third (38) of the outputs of the control unit 3. The second input element 31 is connected with the second inputs of the elements 28 and 32 and is the fourth (39) input control device 3 that performs in the trigger device, the role of S-log.

The trigger device in the counting mode works as follows. At power-up (power circuit logic element is 4, 5, 22, 23, 24, 25, 26 and 27 for simplicity not shown) of the trigger device will be set to the state corresponding to the state of the elements 18 and 19 of the memory that they have acquired in the previous cycle. Consider the case where the memory elements 18 and 19 were magnetized in the state "log.0"that corresponds to the direction of current flow in the coil of the write element 18 memory from the beginning to the end, and the winding of the recording element 19 memory from the end of the winding to its beginning. The input windings on the drawing marked with (*). In the storage of information on the input bus 20 is supported signal "log.0". If after power RS-trigger 1 was set in the zero state, in which its direct (Q) output signal "log.0", and the inverted output signal "log.1″on the second (37) and second (38) the outputs of the control unit 3 and respectively R and S inputs of the RS-flip-flop 2 is set signals respectively "log.0" and "log.1″establishing in one state of the RS-trigger 2, with direct (Q) output signal "log.1"inverse (the output signal "log.0". Through the resistor 14 and the coil of the write element 18 memory current flows, confirming the status of the element 18, at the output winding of the reading of this element can be formed short pulse interference of negative polarity, which will be sotirova the diode 10 and will not pass to the input of the element 5. Through the winding of the recording element 19 of the memory and the resistor 16 current flows, confirming the status of the item 19 memory at the output winding of the reading of this element can be formed short pulse interference of positive polarity, which is passed through a differentiating circuit composed of a capacitor 9 and a resistor 17, but will be suppressed integrating circuit composed of resistor 13 and capacitor 6. In the process of charging of the capacitor 8 through the resistor 15 at both entrances of the elements 4 and 5 are supported signals "log.0", in the R and S inputs of the RS-flip-flop 1 are signals "log.1"direct (Q) and inverse () outputs RS-trigger 1 - signals "log.0", the state of the RS - flip-flop 2 is not changed. After the charge of the capacitor 8 to the output element 5 and on the S-input of the RS flip-flop 1 will set the signal "log.0", on the R input of RS flip-flop 1 continues to hold the signal "log.1". The result confirms the initial zero state of the RS-flip-flop 1, therefore, the state of the trigger device will be stable.

If after power RS-trigger 1 are set to "log.1" (output Q signal "log.1"), RS-trigger 2 will be set in the zero state (Q output signal "log.0", outputthe signal "log.1"). In this case, through the winding of the recording element 18 is of Amati current flows from the end to the beginning, the memory element 18 will begin to paramagnetically in the opposite position, with the coil of the reading of the memory element 18 is formed a pulse of positive polarity, the duration of which is equal to the time of magnetization reversal of the core element 18 of the memory. The resistance of the resistors 14 and 16, and the ratio of the number of turns in the windings of the read and write elements 18 and 19 of the memory are selected so that when a complete reversal magnetization of the cores of the elements 18 and 19 of the memory of the amplitude of the pulse in the winding of the recording was approximately equal to half the supply voltage circuit (S/2), and the amplitude of the pulse at the output winding of the reading was equal to about that is Specified pulse is transmitted through capacitor 8 and an integrating circuit composed of resistor 12 and capacitor 7 (time constant of this circuit is chosen much smaller than the pulse duration at full magnetization reversal of the core), and causes pulse "log.0" on the S-input of the RS flip-flop 1. Simultaneously, through the winding of the recording element 19 memory current flows from the beginning to the end, the memory element 19 will begin to paramagnetically in the opposite position, with the coil of the reading of the memory element 19 is formed a pulse of negative polarity, which device is activated will open diode 11 and will not pass to the input of the element 4. At the output of the element 4, a signal will appear"log.1", which will switch RS-trigger 1 in the zero state. Following this, the RS-flip-flop 2 will switch to "log.1", the direction of currents in the windings of the recording elements 18 and 19 will be reversed, this will be confirmed by the initial state of their magnetization. Further, transients trigger device associated with the charge of the capacitor 8 through the resistor 15, as described above, during the charge time of the capacitor 8 and R - and S-inputs of the RS-flip-flop 1 are held signals "log.1", after the charge of the capacitor 8 RS-trigger 1 will return to the state "log.0". So will restore the state of the trigger device in accordance with the state of the elements 18 and 19 of the memory and, as was shown above, this condition trigger device is stable. Similarly trigger the device when power takes the state "log.1"if the elements 18 and 19 of the memory have been pre-magnetized state "log.1".

To switch the trigger device on the input bus 20 is supplied clock signal with the level "log.1". This same signal is applied to the inputs of the elements 4 and 5 OR NOT, their outputs will always hold signals "log.0", ensuring the presence of RS-flip-flop 1 in the state that it had before receipt of the clock signal. The elements 24 and 25 begin to work the mode inverters, providing switching RS-flip-flop 2 in the state opposite to that which he had before entering the clock signal. For example, in the initial state RS-triggers 1 and 2 were in the States respectively "log.0" and "log.1" (zero state trigger device). When applying the clock signal on the input bus 20 from the outputs of the elements 24 and 25 will receive signals respectively "log.1" and "log.0", RS-trigger 2 will be switched to the zero state (signal "log.0" at the output Q and the signal "log.1" output). Under the action of currents flowing through the winding elements 18 and 19 of the memory, these elements paramagnetically in the state "log.1", while the pulses appearing at the outputs of the windings of the read elements 18 and 19 of the memory, the outputs of the elements 4 and 5 are not, as the latter is blocked by the signal "log.1" from the output 36 of the control device 3. Therefore, the state of the RS-flip-flop 1 in the process steps of the clock signal is not changed. The duration of the clock signal should be sufficient to complete the alternating magnetization of the core elements 18 and 19 and recharge capacitors 8 and 9 through resistors 15 and 17, respectively, in accordance with the new state of the RS-flip-flop 2. After the clock signal on the bus 20, the signals at the outputs 37 and 38 of the control unit will change to the opposite, as a consequence, the S-trigger 2 switches in one state, will change the direction of the currents in the windings of the recording elements 18 and 19 of the memory. The output winding of the read element 18 of the memory will appear on the pulse of negative polarity, the amplitude of which is limited to an open diode 10, so it will have no impact on item 5 (on both inputs of the element 5 - signal "log.0", the output element 5 - signal "log.1"). The output winding of the read element 19 will receive a pulse of positive polarity with an amplitude and duration sufficient to switching element 4 in the state with "log.0" output. As a result, RS-trigger 1 will switch to "log.1", RS-trigger 2 will switch to "log.0", in the winding elements 18 and 19 of the memory will be restored directions of the currents corresponding to the magnetization their status to "log.1". Short pulse interference of positive polarity appearing at the output winding of the read element 18 memory due to nepryamougolnoy of the hysteresis loop of the core and partial demagnetization its core, is depressed integrating circuit composed of resistor 12 and capacitor 7, therefore, will not affect the state of the circuit. This process of switching the trigger device ends, it goes into a new stable state. Similarly, the process of switching trigger another device clock is ignalum of the state "log.1" state "log.0".

Organization of work of the RS-trigger device by using device management 3 presented in figure 2. In the storage of information on R-entrance (entry 35) and on the S-input (input 39 of the control device 3 signals "log.0", therefore, the signals from input 33 to the output 37 from the inlet 34 to the outlet 38 of the control device are transmitted in the mode of repeaters on the output of the element 32 "Exclusive OR" and at the output 36 of the device control 3 signal "log.0". In the trigger device in the mode information storage behaves exactly as described above. If you need to set the trigger device in one state on its input bus 40 signal "log.1", the output element 32 a signal "log.1"blocking elements 4 and 5 with the States with "log.0" on their outputs; the output of element 30 and the output 37 of the control unit 3 a signal "log.1"arriving at the R-input of the RS flip-flop 2; output element 31 a signal "log.0"arriving at the S-input of the RS flip-flop 2. RS-trigger 2 will be set in the zero state, while in the winding elements 18 and 19 memory will flow currents corresponding to the magnetization of the cores of these elements in the state "log.1". Simultaneously with the magnetization switching elements 18 and 19 of the memory will be re-charging of the capacitors 8 and 9 (if the trigger device n is accounted in "log.1"), the duration of the signal on bus 40 should be sufficient to complete these processes. After removal of the signal installation bus 40 RS-trigger 1 are set to "log.1" signal "log.0"generated at the output circuit composed of resistor 15 and capacitor 8, after overcharging of the capacitor 8. This condition trigger device is stable.

If you need to set the trigger device in the zero state at its input bus 20 signal "log.1". As a result, the output of the element 32 "Exclusive OR" error signal "log.1"blocking elements 4 and 5 in States with "log.0" on their outputs, the output of element 30 (exit 37) a signal "log.0", the output element 31 (exit 38) signal "log.1". RS-trigger 2 switches in one state, while in the winding elements 18 and 19 memory will flow currents corresponding to the magnetization of the cores of these elements in the state "log.0". Simultaneously with the magnetization switching elements 18 and 19 of the memory is re-charging of the capacitors 8 and 9 (if the trigger device was in a state of "log.0"). After removing the reset signal from the bus 20 RS-trigger 1 are set to "log.0" signal generated at the output circuit composed of resistor 17 and capacitor 9, after overcharging of the capacitor 9. This condition trigger device is also the tsya stable.

Restoring the state of trigger devices in the storage of information in case of its failure under the effect of the interference is performed by pulses from outputs of the respective windings are read in accordance with the States of the elements 18 and 19 of the memory, and in fault duration exceeds the time alternating magnetization of the core elements 18 and 19 memory - due to the energy accumulated in the capacitors 8 and 9. The duration of the permissible interference in this case is determined by the constant time circuits composed of resistors 15 and 17 and capacitors 8 and 9.

Thus, as follows from the description of the operation of the trigger device, it automatically restores information in the conditions of influence of electrical noise, the duration of which exceeds the time of magnetization reversal of items 18 and 19 of the memory, therefore, that the trigger device has a higher noise immunity.

Testing laboratory layout trigger device confirmed the feasibility and practical value of the claimed device.

The trigger device containing the first RS-flip-flop, a control device with at least three inputs and three outputs, the first and second inputs of the control devices connected respectively with the forward and inverse outputs of the first RS-flip-flop, a third input - the input bus, and the first output with the first inputs of the first and second points of convergence, the second inputs of which are connected with the first pins respectively of the first and second resistors, first and second capacitors, the first conclusions which are connected to a common bus, the first and second memory elements on magnetic cores with rectangular hysteresis loop, each of which has a coil account and winding of reading, and the input windings of the first and second memory elements are connected with the first conclusions of the third and fourth resistors, respectively, the input windings of the read first and second memory elements are United and connected to the shared bus, fifth and sixth resistors, characterized in that the input of the first and second diodes, the third and fourth capacitors, a second RS-trigger, and reset inputs of the installation which are connected respectively with the second and third outputs of the control device, a direct output connected to the output winding of the recording of the second memory element with the second output of the third resistor and the first output of the fifth resistor, the inverted output is connected to the output winding of the first memory element with the second output of the fourth resistor and the first output of the sixth resistor, the output winding of reading the first memory element is connected to the cathode of the first diode and the third capacitor with the second in what Bodom fifth resistor and to the second output of the second resistor, the output winding of the second reading of the memory element is connected to the cathode of the second diode and a fourth capacitor to the second output of the sixth resistor and the second output of the first resistor, the second the findings of the first and second capacitors are connected with the second pins of the first and second points of convergence, respectively, the outputs of which are connected respectively to the inputs of the reset and setup of the first RS-flip-flop, the anodes of the first and second diodes connected to a common bus, the first and second points of convergence in the form of elements OR NOT.



 

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SUBSTANCE: proposed flip-flop device has RS flip-flop 1, EXCLUSIVE OR gates 2,3, NOR gates 4, 5, inverters 6, 7, 8, diodes 15, 16, resistors 9 through 12, capacitors 13, 14, memory items 17, 18 built around magnetic cores with rectangular hysteresis loop and single coil, input bus 19, and common bus 20. Combining write and read coils of memory items 17 and 18 makes it possible to increase coil number of write and read coils by 1.5 times, in each of half-coils of memory items 17 and 18, which reduces magnetizing current through cores of memory items 17 and 18 by approximately 1.5 times due to enhancing ratings of limiting resistors 11 and 12.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Flip-flop device // 2248663

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flop 1, EXCLUSIVE OR gates 2,3, NOR gates 4, 5, inverters 6, 7, 8, diodes 15, 16, resistors 9 through 12, capacitors 13, 14, memory items 17, 18 built around magnetic cores with rectangular hysteresis loop and single coil, input bus 19, and common bus 20. Combining write and read coils of memory items 17 and 18 makes it possible to increase coil number of write and read coils by 1.5 times, in each of half-coils of memory items 17 and 18, which reduces magnetizing current through cores of memory items 17 and 18 by approximately 1.5 times due to enhancing ratings of limiting resistors 11 and 12.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Flip-flop device // 2248662

FIELD: pulse engineering, computer engineering, and control systems.

SUBSTANCE: proposed device has RS flip-flop 1, two NAND gates 2, 3, EXCLUSIVE OR gate 4, inverter 5, four resistors 6 through 9, capacitor 10, memory item 11 built around magnetic core with rectangular hysteresis loop that carries write and read coils, two diodes 12, 13, control input 14, and common bus 15.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

FIELD: digital pulse engineering.

SUBSTANCE: proposed device designed for shaping pulses of desired length for each of three events during power turn-on in response to off-operation button signal incorporating provision for chatter elimination in case of skip or stop of changes in input pulses on detection enabling has first and second monostable restart multivibrators 1, 4, off-operation button 2, flip-flop 3, shaper 5 of signal responding to button-provided power turn-on which is built around capacitor 12, resistors 13, 14, diode 15 and two NAND gates 6,7, as well as AND gate 8, controllable pulse generator 9, logical 1 input, pulse signal input 10, and control input 11. Controllable pulse generator 9 is built around AND gate 16, NAND gate 17, resistors 18, 19, and capacitor 20. Device can shape input pulse during power turn-on period and function as hardware watch timer implemented in the course of forward and backward automatic interaction with system microcontroller.

EFFECT: enlarged functional capabilities of device.

1 cl, 1 dwg

FIELD: measurement technology; pulse stream generators.

SUBSTANCE: proposed Poisson pulse stream generator has k + 1 memory devices, comparison unit, k digital-to-analog converters, control circuit, register, counter, selector, k bell-shaped pulse generators, adder, voltage-to-current converter, and clock generator.

EFFECT: enlarged generation range of pulses adequate to ionization chamber signals.

1 cl, 2 dwg

The invention relates to a means for information transfer and remote control systems on their basis

The invention relates to a device for charging rechargeable batteries of the network through the converters and can be used to charge energy storage in various automation devices and computing

FIELD: measurement technology; pulse stream generators.

SUBSTANCE: proposed Poisson pulse stream generator has k + 1 memory devices, comparison unit, k digital-to-analog converters, control circuit, register, counter, selector, k bell-shaped pulse generators, adder, voltage-to-current converter, and clock generator.

EFFECT: enlarged generation range of pulses adequate to ionization chamber signals.

1 cl, 2 dwg

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