Field-effect nanotransistor

FIELD: nanoelectronics and microelectronics.

SUBSTANCE: proposed nanotransistor that can be used in microelectronic and microelectromechanical systems as fast-response amplifier for broadband digital mobile communication means and also for building microprocessors, nanoprocessors, and nanocomputers has semiconductor layer incorporating conducting channel, thin insulator layer disposed on semiconductor surface, gate made on thin insulator surface, drain, and source contacts; semiconductor layer is disposed on bottom insulator layer that covers semiconductor substrate functioning as bottom gate; conducting channel is nano-structured in the form of periodic grid of quantum wires; thin insulator layer encloses each quantum wire of conducting channel on three sides; gate is made in the form of nanometric-width metal strip and encloses each quantum wire of conducting channel on three sides; thin insulator has windows holding drain and source metal contacts connected to channel. Silicon can be used as semiconducting material and thermal silicon dioxide, as insulator.

EFFECT: enhanced degree of integration, reduced size, eliminated short-channel effects, enhanced transconductance, radiation resistance, and environmental friendliness of device manufacture.

4 cl, 2 dwg

 

The invention relates to nano-electronics and microelectronics, and can be used in microelectronic and microelectromechanical systems as high-speed amplifiers for money broadband digital mobile communication, as well as to build micro-nanoprocessors and nanocomputers.

Known field nanotransistor (Emegasim, .Yoshimura, Y.Goto, S.Kimura, "Gate length scalability of n-MOSFET''s down to 30 nm: comparison between LDD and non-LDD structures", IEEE Transactions on Electron Devices, Vol. 47, No. 4, pp.835-840 (2000)), containing a layer of semiconductor material, which is made conductive channel layer of a thin dielectric located on a surface of a semiconductor material, the shutter is performed on the surface of the thin dielectric contacts the drain, source, representing two electrical contact to the conducting channel, made in the form of closely spaced electron-hole transitions, while the gate is made of polycrystalline semiconductor material and located above and between source and drain.

The disadvantages of the known devices include the following.

First, low slope (less than 0.05 mxim) in small currents (subthreshold region). This disadvantage is due to the fact that the conductive channel of the field nanotransistor is in the weak inversion and field nanotransistor works as bipola the hydrated n-p-n transistor in signalground semiconductor.

Secondly, korotkokanal effects, limiting the minimum size of the channel magnitude is not less than 30 nm. When the channel size is less than this value it will be smaller than the space-charge regions of electron-hole transitions of the source and drain, and on the surface of a semiconductor in the field of a conducting channel, the electric field reaches such high values that the conductive channel will be warming up charge carriers, the saturation drift velocity of charge carriers, the injection of hot carriers in the thin layer of gate dielectric and impact ionization in the region of the flow.

Thirdly, the low degree of integration. Known field nanotransistor characterized by high dissipation due to large leakage currents on the surface (boundary) of electron-hole transitions and shutter, which limits the maximum number of nanotransistors on a single chip (the degree of integration of circuits).

Fourth, high radiation sensitivity due to degradation of electron-hole transitions and accumulation of charge in the gate dielectric.

Fifth, low environmental mass production of nanotransistors due to the use of phosphorus and boron as an alloying materials in the formation of electron-hole transitions in silicon.

The closest set of features and purpose to the claimed technical solution is field nanotransistor (.Doyle, R.Arghavani, D.Barlage, S.Datta, M.Doczy, J.Kavalieros, A.Murthy and R.Chau, "Transistor elements for 30 nm physical gate lengths and beyond", Intel Technical Journal, Vol. 6, No.2, pp.42-61 (2002)), containing a layer of semiconductor material, which is made conductive channel layer of a thin dielectric located on a surface of a semiconductor material, the shutter is performed on the surface of the thin dielectric contacts the drain, source, representing two electrical contact to the conducting channel, made in the form of closely spaced electron-hole transitions, while the conducting channel is made on the surface of the semiconductor material so that the plate body of the transistor is not in a horizontal plane, as it were, set on edge, the gate of the polycrystalline material made by both sides and in the plane of the channel and located between the inlet and the outlet (so-called dvuhstvornyh FinFET, in which the channels are induced voltage on the gates along both sides of such plate or field nanotransistor performed with a fully depleted semiconductor substrate.

And for field nanotransistor mode with a fully depleted silicon layer is necessary to reduce the thickness of the silicon up to about the Noah-thirds of the length of the shutter.

The disadvantages of this technical solution is the following.

First, the low slope in the subthreshold region (0,1 mxim for surround channel and 2 mxim field nanotransistor with a fully depleted semiconductor substrate). This drawback is due to the need to use signalisierung semiconductor.

Secondly, korotkokanal effects, because they limit the minimum size of the channel to a value of not less than 30 nm. When the channel size is less than this value it will be smaller than the space-charge regions of electron-hole transitions of the source and drain, and on the surface of a semiconductor in the field of a conducting channel, the electric field will reach such enormous value that a conducting channel will be warming up charge carriers, the saturation drift velocity of charge carriers, the injection of hot carriers in the thin layer of gate dielectric and impact ionization in the region of the flow.

Thirdly, the low degree of integration. Known field nanotransistor characterized by high dissipation due to large leakage currents on the surface (boundary) of electron-hole transitions and shutter, which limits the maximum number of nanotransistors on a single chip (the degree of integration of circuits).

the fourth, high radiation sensitivity due to degradation of electron-hole transitions and accumulation of charge in the gate dielectric.

Fifth, low environmental mass production due to the use of phosphorus and boron as an alloying materials in the formation of electron-hole transitions in silicon.

Sixth, high quality requirements and the minimum thickness of silicon (less than one-third the length of the shutter), which is the channel field nanotransistor caused due to heavy doping of the semiconductor and, accordingly, the small thickness of the space charge region around the inversion channel.

The technical result of the invention is:

- increase the degree of integration, reducing the size of the field nanotransistor;

exception korotkokanal effects of field nanotransistor;

- the increase slope of the field nanotransistor;

- increase the radiation resistance of field nanotransistors;

- more environmentally friendly production of products.

The technical result is achieved in that field nanotransistor contains a layer of semiconductor material, which is made conductive channel layer of a thin dielectric located on a surface of a semiconductor material, the shutter is performed on a surface is STI thin dielectric, contacts the drain, a source, and a layer of semiconductor material is located on the lower layer of dielectric is performed on the semiconductor substrate, which is the lower gate conductive nanostructured channel in the form of periodic arrays of quantum wires, a thin layer of dielectric around each quantum wire conductive channel on three sides, and the gate is made in the form of metal strips nanometer width and grabs each quantum wire conductive channel on three sides, a thin dielectric contains a window which is made of metal contacts the drain and the source connected to the conducting channel.

In the field nanotransistor as a semiconductor material using silicon.

In the field nanotransistor as dielectric use of thermal silicon dioxide.

In the field nanotransistor as a semiconductor substrate using a substrate of silicon.

The invention is illustrated in the following description and the accompanying drawings. Figure 1 shows the image field nanotransistor above, obtained using atomic force microscope, where 1 - drain 2 - gate 3 - source 4 - lower insulator. Figure 2 shows the image channel field-effect transistor to form the upper gate (a) and after the formation of the upper C is down (b), as well as a schematic representation of the cross-section of the gate region of the field nanotransistor (C) and the image of the top view of the FET (d), where 1 - drain 2 - gate 3 - source 4 - lower insulator, 5 - channel, 6 - lower bolt, 7 - thin gate dielectric. Figure 3 shows the sealing characteristics of the field nanotransistor mode hole channel, where 8 - volt-ampere characteristic (VAC) field nanotransistor when the voltage on the lower gate line 100, 9 - WAH field nanotransistor when the voltage on the lower gate - 70, 10 - WAH field nanotransistor when the voltage on the lower shutter 50 In the mode e channel-11 - WAH field nanotransistor when the voltage on the lower shutter +50 V, 12 - WAH field nanotransistor when the voltage on the lower shutter + 25, 13 - WAH field nanotransistor when the voltage the lower shutter + 10 C.

The channel field nanotransistor is located in the silicon layer of nanometer thickness on dielectric (thermal silicon dioxide), in the form of nanostructured quantum wires, covered on three sides with a thin dielectric of thermal silicon dioxide and surrounded on three sides by a metal shutter. Electrical contact to the channel field nanotransistor made of metal.

The concentration and type of charge carriers in the channel is controlled and pin airwest application of an electric field on the bottom of the shutter, made in the form of the silicon substrate below the dielectric (thermal silicon dioxide).

Design features perform field nanotransistor ensure the absence of korotkokanal effects, allows to increase radiation resistance, to achieve a high slope field nanotransistors, to increase the degree of integration and sustainability of mass production. Achievement of the above results is provided mainly by changing the design of the field nanotransistor. The functioning of the proposed design field nanotransistor based on the presence of the induced channel in a semiconductor with ohmic contacts to the channel in the form of a multilayer metal. The concentration and type of charge carriers is set and controlled by the lower shutter (substrate structure of silicon-on-insulator (SOI structure)). To control conductivity of the channel used three-dimensional metallic top gate, bow nanometer narrow channel on three sides. The use of pure semiconductor (not specially doped) allows you to raise the mobility of charge carriers in the conductive channel of the field nanotransistor and to work on both electrons and holes (in the same field nanotransistor).

In this field of nantra is SISTORE disclaimer contact to the conducting channel in the form of electron-hole transitions and transition to the main media induced channel allowed to exclude korotkokanal effects, in the result it was possible reduction of the sizes of the channel to units of nanometers and, therefore, increase the degree of integration of circuits by increasing their radiation resistance.

The use of three-dimensional upper metal shutter nanometer width allowed clasp nanometer channel on three sides and raise the slope of the field nanotransistor to theoretical limit.

The exception is the use of boron and phosphorus in the creation of products by replacing the electron-hole transitions of the source and drain multi-layer metal contacts to the channel field nanotransistor increases the sustainability of mass production.

Replacement bulk silicon field nanotransistor on silicon nanometer thickness of the SOI-structure means the reduction of the volume of the semiconductor, in which a charge of radiation-induced or thermogenerators media. Accordingly, the stability field of nanotransistors in relation to radiation and ablolutely impacts. The consequences of the accumulation of radiation-induced charge in the lower dielectric compensated voltage to the bottom gate due to the linear dependence of the threshold voltage of the field nanotransistor from the voltage on the lower bolt.

Field nanotransistor contains drain 1, shutter , the source 3, the lower insulator 4, a conductive channel 5, the lower shutter 6, a thin gate dielectric 7 (1, 2).

On a silicon substrate, performing the functions of the lower shutter (b) field nanotransistor deposited dielectric layer, performing the functions of the lower insulator (4), the surface of which is a layer of pure silicon nanometer thickness, in which the channel (5) field nanotransistor nanometer width, nanostructured in the form of periodic arrays of quantum wires, covered, in turn, the upper thin continuous layer of silicon oxide repeating the relief of a periodic grating, which is a thin gate dielectric (7), over which is applied in the form of a strip by a continuous layer of metal gate (2). The shutter (2) as a thin gate dielectric around each quantum wire conductive channel of the field nanotransistor on three sides and repeats the relief of the periodic lattice. Contacts the source (3) drain (1) to channel (5) field nanotransistor made of metal, are in boxes in the top thin layer of silicon oxide, which is a thin gate dielectric (7)on both sides of the shutter (2) (figure 2 (C) and (d)).

As a conducting channel (5) field nanotransistor use a layer of pure silicon (not alloyed special is but for example, the brand KDB-40) nm thickness, for example, 44 nm, located on the lower dielectric (4) of silicon dioxide of a thickness of 350 nm and oxidized top thermal method for forming a thin gate dielectric (7) thickness of, for example, 10 nm after nanostructuring in the form of periodic arrays of quantum wires, the period which is, for example, 400 nm, and the width of the silicon quantum wire 150 nm.

As the lower shutter (6) field nanotransistor used a silicon substrate structure of silicon-on-insulator (SOI), which is the basis from which to create the field nanotransistor.

The electric field applied by the lower shutter controls how the concentration and type of mobile charge carriers in the channel field nanotransistor.

As the shutter (2) use metal electrode nanometer width, clasping each quantum wire channel (5) field nanotransistor from three sides at once.

As electrical contacts to the conducting channel (5) field nanotransistor use a metal layer applied in window pre-opened at the top of thermal oxide thin gate dielectric (7) over the channel field nanotransistor.

Field nanotransistor works as follows.

the ri application of voltage to the lower shutter (6) field nanotransistor in the channel (5) field nanotransistor are formed due to the effect of field mobile charge carriers, either electrons or holes, depending on the polarity of the applied voltage. Field nanotransistor mode induced conductive channel. When a voltage is applied to the contacts of the source (3) drain (1) in the channel (5) electric current flows, the magnitude of which varies under the influence of a gate voltage (2). 3 shows the volt-ampere characteristics (VAC): according to current flow (1) from the gate voltage (2) at different voltage on the lower cover (6). There is a high steepness of the sealing characteristics of the field nanotransistor in the absence of the effects of short channel and leakage of the shutter and contacts the source (3) drain (1). High steepness of the bolt WAH (more than 12 mxim when converted to 10 μm channel width) allows to obtain a large change in current flow (1 µa) at small change in gate voltage (0.1 V).

No korotkokanal effects is confirmed by the high slope of the CVC field nanotransistors when working on electronic and hole-induced channels. The increasing slope of the CVC field nanotransistor is achieved through the use of clean, not specially doped silicon nanometer thickness in SOI structures and three-dimensional metal shutter covering the conducting channel on three sides over the thin upper pojat REGO dielectric.

The advantages of this field nanotransistor should include not only the lack of effects of a short channel, but the low capacity of the three-dimensional, essentially, the top bolt on the ground, the high slope of the CVC field nanotransistor and the possibility of further reducing the size of the field of nanotransistors to units of nanometers, while significantly improving their performance, reduced power consumption due to the reduction of leakage to improve the degree of integration of devices, micro - and nanoelectronics at the same time decreasing the cost and improving the environment of their production.

The positive effect of this invention is to nanoinitiative field nanotransistors on silicon, which leads to improved reliability, sensitivity, speed and degree of integration.

1. Field nanotransistor containing a layer of semiconductor material, which is made conductive channel layer of a thin dielectric located on a surface of a semiconductor material, the shutter is performed on the surface of the thin dielectric contacts the drain, source, characterized in that the layer of semiconductor material is located on the lower layer of dielectric is performed on the semiconductor substrate, which is the bottom gate, a conductive channel in the form of nanostructured Perry is legal lattice quantum wires, a thin layer of dielectric around each quantum wire conductive channel on three sides, and the gate is made in the form of metal strips nanometer width and grabs each quantum wire conductive channel on three sides, and a thin dielectric contains a window which is made of metal contacts the drain and the source connected to the channel.

2. Field nanotransistor according to claim 1, characterized in that the semiconductor material is silicon.

3. Field nanotransistor according to claim 1 or 2, characterized in that a dielectric used for thermal silicon dioxide.

4. Field nanotransistor according to any one of claims 1 to 3, characterized in that a semiconductor substrate is used, the substrate of silicon.



 

Same patents:

FIELD: nanoelectronics and microelectronics.

SUBSTANCE: proposed nanotransistor that can be used in microelectronic and microelectromechanical systems as fast-response amplifier for broadband digital mobile communication means and also for building microprocessors, nanoprocessors, and nanocomputers has semiconductor layer incorporating conducting channel, thin insulator layer disposed on semiconductor surface, gate made on thin insulator surface, drain, and source contacts; semiconductor layer is disposed on bottom insulator layer that covers semiconductor substrate functioning as bottom gate; conducting channel is nano-structured in the form of periodic grid of quantum wires; thin insulator layer encloses each quantum wire of conducting channel on three sides; gate is made in the form of nanometric-width metal strip and encloses each quantum wire of conducting channel on three sides; thin insulator has windows holding drain and source metal contacts connected to channel. Silicon can be used as semiconducting material and thermal silicon dioxide, as insulator.

EFFECT: enhanced degree of integration, reduced size, eliminated short-channel effects, enhanced transconductance, radiation resistance, and environmental friendliness of device manufacture.

4 cl, 2 dwg

Field transistor // 2358355

FIELD: physics, radio.

SUBSTANCE: invention is to find application in microelectronics. Concept of the invention is as follows: the proposed field transistor is composed of a source electrode, a drain electrode, a gate insulator, a gate electrode and an effective layer; the effective layer contains an amorphous oxide with an electronic media concentration less than 1018/cm3 and the electronic mobility increasing proportional to the electronic media concentration. Of the source, drain and gate electrodes at least one is visual light translucent with the current flowing between the source and the drain electrodes never exceeding 10 mA unless there is a voltage applied to the gate electrode.

EFFECT: development of a transistor enabling improvement of at least one of the following properties: translucency, thin film transistor electrical properties, gate insulation film properties, leakage current prevention and adhesiveness between the effective layer and the substrate.

21 cl, 12 dwg

FIELD: physics.

SUBSTANCE: invention relates to an amorphous oxide, used in the active layer of a field-effect transistor. The amorphous oxide, which contains at least one microcrystal and has concentration of electron carriers from 1012/cm3 to 1018/cm3, contains at least one element, chosen from a group consisting of In, Zn and Sn, and the boundary surface of the grains of the said microcrystal is coated with an amorphous structure.

EFFECT: obtaining an amorphous oxide which functions as a semiconductor for use in the active layer of a thin-film transistor.

6 cl, 8 dwg

FIELD: electrical engineering.

SUBSTANCE: proposed invention relates to field transistor with oxide semiconductor material including In and Zn. Atomic composition ratio expressed as In/(In+Zn) makes at least 35 atomic percent and not over 55 atomic percent. With Ga introduced into material, aforesaid atomic composition ratio expressed as Ga/(In+Zn+Ga) makes 30 atomic percents or smaller.

EFFECT: improved S-characteristic and drift mobility.

9 cl, 25 dwg

Field transistor // 2390072

FIELD: electricity.

SUBSTANCE: in field transistor, comprising active layer and gate-insulating film, active layer comprises a layer of oxide, comprising In, Zn and Ga, amorphous area and crystalline area. At the same time crystalline area is separated from the first surface of interface, which is surface of interface between a layer of oxide and gate-insulating film, distance of 1/2 of active layer thickness or less, and it within the limits of 300 nm from surface of interface between active layer and gate-insulating film or is in point condition in contact with this surface of interface.

EFFECT: production of field transistor with high drift mobility.

4 cl, 4 dwg, 2 ex

FIELD: chemistry.

SUBSTANCE: amorphous oxide compound having a composition which, when said compound is in crystalline state, has formula In2-xM3xO3(Zn1-YM2YO)m, where M2 is Mg or Ca, M3 is B, Al, Ga or Y, 0 ≤ X ≤ 2, 0 ≤ Y ≤ 1, and m equals 0 or is a positive integer less than 6, or a mixture of such compounds, where the said amorphous oxide compound also contains one type of element or several elements selected from a group consisting of Li, Na, Mn, Ni, Pd, Cu, Cd, C, N, P, Ti, Zr, V, Ru, Ge, Sn and F, and the said amorphous oxide compound has concentration of electronic carriers between 1015/cm3 and 1018/cm3.

EFFECT: amorphous oxide which functions as a semiconductor for use in the active layer of a thin-film transistor.

6 cl, 8 dwg

FIELD: physics.

SUBSTANCE: in a field-effect transistor which includes an oxide film as a semiconductor layer, the oxide film has a channel part, a source part and a drain part, and concentration of one of hydrogen or deuterium in the source part and in the drain part exceeds that in the channel part.

EFFECT: invention enables to establish connection between the conducting channel of a transistor and each of sources and drain electrodes, thereby reducing change in parameters of the transistor.

9 cl, 13 dwg, 6 ex

FIELD: electricity.

SUBSTANCE: amorphous oxide the composition of which changes in direction of the thickness of layer contains the compound the composition of crystal state of which is presented with formula In2-XM3XO3(Zn1-YM2YO)m , where M2 - element of group II with atomic number which is less than that of Zn (for example Mg or Ca), M3 - element of group III with atomic number which is less than that of In (for example B, Al, Ga or Y), x is within the range of 0 to 2, y is within the range of 0 to 1 and m is 0 or natural number which his less than 6, and at that, amorphous oxide has concentration of electron carriers of not less than 1012/cm3 and less than 1018/cm3 and has electron mobility which increases with increase of concentration of electron carriers.

EFFECT: amorphous oxide operates as semi-conductor to be used in active layer of transistor.

7 cl, 10 dwg

FIELD: physics.

SUBSTANCE: in a memory element which comprises a substrate with deposited thin layers of ceric and silicon oxide and metal electrodes for recording and deleting information is made from glass which is pre-cleaned with acetone and isopropyl alcohol, on which a ceric oxide layer is deposited at temperature higher than 600°C and thickness of more than 3 nm and a silicon film with thickness of 50-100 nm.

EFFECT: invention prolongs information storage period, simplifies the manufacturing technology and reduces production expenses.

4 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: method of manufacturing of an enhancement/depletion (E/D) inverter having a number of thin-film transistors on the same substrate with channel layers consisting of an oxide semiconductor containing at least one element selected from In, Ga and Zn, involves the stages to form a first transistor and a second transistor; a channel layer thickness of the first and second transistors is mutually different; at least one of the channel layers of the first and second transistors are thermally treated.

EFFECT: expansion of the facilities allowing to manufacturer an inverter with oxide semiconductor thin-film transistors of various threshold voltages, simplified method of manufacturing of the inverter with such characteristics, cost reduction.

13 cl, 18 dwg

Up!