Method for non-destructive data reading and device for realization of said method

FIELD: memory devices.

SUBSTANCE: first device for comparing phases has signal generator for feeding two or more reading signals with given phases to memory cell, phase-sensitive detector, support signal source, discrimination/logic contour. Second device for comparing phases has signal generator for feeding first periodical signal, applied to second periodically reading signal of lesser frequency, phase-sensitive detector/discriminator. Method describes operation of said devices.

EFFECT: higher reliability.

3 cl, 15 dwg

 

The technical field to which the invention relates.

The present invention relates to a method of determining a logical state of a memory cell in a memory device. The specified cell stores data in the form of a status of the electrical polarization of the capacitor containing polarizable material. This material is able to maintain stable electrical polarization in the absence of external voltage supplied to the capacitor and to generate a current in response to the applied voltage. This current response contains linear and nonlinear components. The invention relates also to the first and second devices for matching phases in the implementation of the method according to the present invention.

More specifically, the present invention relates to non-destructive read the contents of memory cells containing polarizable material with hysteresis, preferably such as are known from the prior art electret or ferroelectric materials.

The level of technology

In recent years demonstrated the storage of data in the electrically polarizable medium consisting of thin films of ceramic or polymer ferroelectric materials. The main advantage of such materials is that they retain their polarization without a constant supply to them elektricheskoi energy, i.e. data storage is non-volatile.

Were created storage device (storage device)belonging to two main groups, in which the logic state of the individual memory cell is represented by a vector direction of polarization of the ferroelectric thin film in the cell. In both cases, the data is written into the cell through the polarization film in the desired direction by applying a correspondingly oriented electric field is more intense than the coercive field in ferroelectric. However, the architecture of the devices has fundamental differences.

In the devices belonging to the first class, each memory cell comprises at least one transistor. In General, the memory architecture of this type matches the type of the active matrix. Its main advantage compared to traditional devices such as SRAM and DRAM is the independence of the logical state stored in the ferroelectric.

A large subclass of such ferroelectric memory devices, usually referred to as FeRAM or FRAM (copyrights to this term belongs to the company symetrix equipment Corp.), described in detail in the technical and patent literature, and is now commercially produced by a number of companies in different countries of the world. In its simplest Faure is e (architecture 1T-1C) each FeRAM memory cell contains a single transistor and a capacitor, as shown in figure 1. The capacitor includes a ferroelectric, which can be polarized in one direction corresponding to a logical "0"or in the other direction corresponding to a logical "1". The record in this memory cell, i.e. giving to the given direction of polarization ferroelectric capacitor, is produced by applying appropriate voltages to the control line (numeric bus), the data line (bit bus), and transmitting line (driveline)serving the cell. Reading is performed by disconnecting the data line from the power source and the positive voltage to the transmitting line, while the control line is energized specified level. Depending on the polarization direction in the capacitor, i.e, it is not known whether this memory cell logic "0" or logical "1", the charge carried in the described process to the charging line will be either significant or small. Thus, the logical state of the cell can be determined by registering the value of this charge. Since the read operation is destructive, in order to avoid permanent loss of stored information, you will then need to re-write data.

In different ways the concept of FeRAM was issued a large number of patents, including Chi is Le U.S. patent No. 5539279, 5530668, 5541872, 5550770, 5572459, 5600587, 5883828. In these patents are treated as different architecture and materials; there are also complex problems that delay the practical use of ferroelectric memory devices since their conceptual development a few decades ago. Thus, the destructive nature of reading in known storage devices contributes to the development of fatigue used in ferroelectric materials, which limits their service life and, as a consequence, the suitability for a wide class of applications.

As a result of intensive development has helped to improve and modify some materials (for example, PZT and SBT) so that they could withstand a large number of switching cycles (1010up to 1014)acceptable to the most demanding applications, and have sufficient resistance to interference. However, these optimized materials require annealing at high temperatures, sensitive to the effects of hydrogen and other factors. As a rule, they create costly and complex problems in relation to their use in large-scale production based on well-developed technology for devices based on silicon. In addition, because they require heat treatment, these materials are non-recognition is odni for subsequent integration into electronic devices based on polymers. Some patents reflect efforts to circumvent the problems of drift and the manufacturing tolerances through the use of more complex architectures. Such architecture may include a memory cell containing two ferroelectric capacitor and two transistors (design 2C-2T) in order to use reference cells and circuits, as well as more complex pulse protocols. In this connection it may be noted that all currently released ferroelectric memory devices use the architecture 2C-2T. This is because the materials used under load do not yet possess sufficient stability in relation to time, temperature and number of cycles of the supply voltage (D.Hadnagy. "Making ferroelectric memories", The Industrial Physicist, pp. 26-28 (December 1999)).

In another subclass of devices using one or more transistors in each memory cell, the resistance between the drain and source of the transistor present in the cell, directly or indirectly controlled by the polarization state of the ferroelectric capacitor in the same cell. The idea underlying this approach is not new (see, for example, Noriyoshi Yamauchi. "A metal-insulator-semiconductor (MIS) device using a ferroelectric polymer thin film in the gate insulator", Jap. J. Appl. Phys., 25, pp. 590-594 (1986); Jun Yu et al. "Formation and characteristics of Pb(Zr,Ti)O3buffer layer", Appl. Phys. Lett. 70, pp. 490-492 (1997); Si-Bei Xiong and Shigeki Sakai. "Memory properties of SrBi2Ta2O9thin fils prepared on SiO 2/Si substrates", Appl. Phys. Lett. 70, pp. 1613-1615 (1999)). In U.S. patent No. 5592409 described non-volatile memory based on ferroelectric film, which is polarized in one direction or the other, which corresponds to a logical "0" or "1". Polarized ferroelectric creates a bias on the gate field-effect transistor, thereby providing a control current of this transistor. The obvious advantage of this management option is that you can read the logical state of the memory cell basestructure, i.e. without inverting the polarization state of the ferroelectric capacitor.

A similar concept is described in U.S. patent No. 5070385. It is based on the use of semiconductor material, which are in tight contact with the ferroelectric. In this case, the resistance of a semiconductor material depends on the polarization state in the ferroelectric. Unfortunately, for all of the above concepts remain very serious problems of material and technological nature (see, for example, D.Hadnagy. "Making ferroelectric memories", The Industrial Physicist, pp. 26-28 (December 1999)). Therefore, their industrial development in the foreseeable future is doubtful.

For both considered subclasses need one or more of the transistors in each cell represents a serious drawback from the point zren the I complexity and reduce the density of the data record.

In the devices belonging to the second class and special interest in the context of the invention, a memory cell used in a passive matrix architecture, in which two sets of mutually orthogonal electrodes form sets kondensatoprovodov structures in areas of crossing electrodes. As shown in figure 2, each memory cell can be formed very simply by using strip electrodes, which, crossing, forming an area of overlap type of sandwich on the basis of the polarizable material enclosed between the planes of the electrodes. Possible alternative capacitor structure in which an electric field that interacts with the polarizable material, are major components directed parallel to the substrate, and not perpendicular to it. Such "cross" architecture next will not be considered, since the particular choice of the architecture of the cell in the context of the present invention is not of great importance.

In accordance with the prior art, the reading of data from the individual memory cells by application to the material of each corresponding cell in the electric field sufficient to overcome the effect of hysteresis and to Orient the electric polarization in the cell in the direction of the electric the CSO field. If the material has already been polarized in this direction up to the application to him of the field, no invert polarization does not occur and flows through the cell, only a small transient current. However, if the material was polarized in the opposite direction, is the inversion of the polarization, which leads to flow much more transient DC. Thus, the logical state, i.e. the direction of the electric polarization in the individual memory cell is determined by the application thereto of an electric field, the intensity of which is sufficient to overcome the coercive field in ferroelectric, and detecting the resulting current.

Compared with devices based on active matrix, passive matrix devices can be manufactured with a much higher density of memory cells; however, the matrix memory is less complex. However, the known process of reading from such a matrix is destructive, i.e. leading to loss of content in the cell from which you are reading. As a consequence, the data that must be read, must again be written to the storage device, if you want to continue saving data. A more serious consequence of the polarization switching is fatigue, i.e. gradually the th loss of the ability to switch polarization. Generally, this phenomenon is accompanied by the necessary application to the cell of a higher voltage for the purpose of inverting polarization. Fatigue limits the number of read cycles that can withstand the particular memory cell. Thereby limited and the range of applications. In addition, fatigue leads to slower response times and higher requirements to the device supply voltage. What if this is a gradual change in performance for individual memory cells in a particular device cannot be predicted a priori. Therefore, the design and operation should be based on the "worst case", which leads to suboptimal modes.

Attempts were made to find solutions to make non-destructive elucidation reading from the memory based on ferroelectric while maintaining a simple architecture of a memory cell. So, Brennan (.J.Brennan) in U.S. patentsâ„–â„–5343421; 5309390; 5262983; 5245568; 5151877 and 5140548 describes the ferroelectric capacitor of the cell and their associated elementary modules for reading data storage devices. By sensing capacitance using weak signals with simultaneous application to the ferroelectric moderate fields offset, i.e. fields that do not lead to the creation of the memory cell at the time please take the of peak voltages, exceeding the coercive field in ferroelectric, is the determination of the direction of spontaneous polarization in the capacitor and, as a consequence, the logical state of the memory cell. However, for practical application of the methods and devices described in these patents requires very specific conditions that lead to the phenomena associated with the accumulation on the electrodes of space charge. These phenomena are directly dependent on the materials used in the electrodes, as well as from adjacent ferroelectric. Reading data associated with the assessment of the space charge, which can be obtained in the time scale that is compatible with the specified charge accumulation. In addition, these patents do not explain how to implement the timing and correlation of the small signal voltage and offset relative to each other, which is essential for use in real conditions.

In the above U.S. patent No. 5140548 described a device that does not require the filing of a bias voltage from an external source, forming internal displacement on the basis of the contact potential difference between the electrodes, covering the ferroelectric core. This solution, while elegant in principle, suffers from serious shortcomings if his IP is of use in real devices. So, you have to sacrifice predictability and controllability, which can be achieved through an external bias source, by switching to a fixed offset, which explicitly depends on the purity of the materials used and their processing, as well as the operating temperature. Unipolar and permanent displacement generated by the internal leads to imprint in ferroelectric, well known and highly undesirable phenomenon in ferroelectric memory devices. Finally, a fixed offset is not of great value when using the correlation of the strategies contained in this description.

Japanese patent publication JP-A-06275062 and JP-A-05129622 describe non-destructive elucidation reading in a passive matrix ferroelectric memory device. The polarization state of individual memory cells is determined by recording the phase of the second harmonic current response of the memory cell excited by a small periodic voltage signal. In addition, the publication of JP-A-06275062 describes the application of a bias voltage to set the position of the operating point on the hysteresis curve near the point of maximum curvature for one of the logic States, thereby increasing the amplitude of the second harmonic.

U.S. patent No. 5666305 describes non-destructive elucidation is CityLine in passive matrix ferroelectric memory by feeding pulses disturbing voltage level, lying significantly below the coercive voltage.

In U.S. patent No. 3132326 disclosed non-destructive elucidation read from the ferroelectric memory cell produced in the same way, using a pulse voltage lower than the coercive voltage for sensing the current response of the memory cell.

U.S. patent No. 5262982 describes the use of a positive unipolar pulse with simultaneous detection of the current response with the goal of determining the average slope of the hysteresis curve to the right of the axis of polarization with further negative unipolar pulse, similarly sounding curve hysteresis. After this is determined by the difference between the results obtained when applying each pulse.

The last five mentioned patent documents have in common that they all implement non-destructive elucidation read by feed readers or probe pulse with a voltage that is substantially less than the coercive voltage, and then base the definition of the logical state of some parameter of the current response. In one case, for detection use the second harmonic response. In General, the methods have inherent weaknesses relating to reliable determine the logical state of the memory cell in the least because the use of a single readout signal will not allow you to apply more powerful correlation method. This method is simply required when non-destructive elucidation reading should be done in the regime of weak signals.

Finally, to ensure a more reliable non-destructive elucidation read from the ferroelectric memory with passive matrix addressing in U.S. patent No. 5530667 offers storage device with ferroelectric memory material having hysteresis curve with nonlinear plots in two areas of steep rise. Non-destructive elucidation is read out using the probing signal not exceeding the coercive voltage, with the filing of this signal in the zones of the hysteresis curve, which detect detektiruya the difference in the capacitive characteristics between the two realized the logical States.

Thus, in General and especially in relation to the production of economically promising ferroelectric memory devices with passive matrix addressing, there is an urgent need for devices and methods that allow to perform non-destructive elucidation reading of the memory cells, which are made in the form of capacitors electrically polarizable material having hysteresis, which do not contain active elements such as transistors. Considering the fact that non-destructive elucidation read from the ferroelectric memory with passive matrix addressing should be done with the help of the read signal with a voltage lower coercive voltage, and, as a rule, in the regime of weak signals there is also a need for more reliable methods of non-destructive elucidation read than known methods, including those discussed above.

The invention

Thus, the main task to be solved by the present invention is directed, is to develop the conceptual basis of non-destructive elucidation of reading data from storage devices containing cells with electrically polarizable environment, especially with the ferroelectric.

Another problem solved by the invention is the ability to read data without increasing fatigue and wear that accompany traditional methods of reading by switching polarization and which limit the service life of the storage devices, based on ferroelectrics. Another task is to get rid of the inherent destructive readout of the need to restore the contents of the cells was done reading. Thereby is achieved simplification of the Protocol read and used equipment.

D. linesa task set before the invention is to improve the reliability of the reading process by using more than one criterion recognition to determine the logical state of a particular memory cell.

Finally, the problem to be solved by the invention is also to develop common procedures and devices for non-destructive elucidation of the read data.

The solution of these problems, and the implementation of additional features and advantages provided by the creating method according to the present invention. This method is characterized by the following operations:

application to the condenser of the first time varying voltage corresponding to the regime of weak signals, the amplitude and/or duration which is selected smaller than that required to create a significant permanent changes the polarization state of the capacitor

application to the condenser of the second time-varying voltage, which is formed with a first time-varying voltage, and the amplitude and/or duration of the sum of the first and second voltages changing over time, choose smaller, than this is required to create significant permanent changes the polarization state of the capacitor

check at least one characteristic of the current response of the capacitor, generiruemogo in the regime of weak signals, with linear or nonlinear dependence on the first and/or second applied voltage, time-varying,

conducting a correlation analysis based on the use of correlating the reference signals generated on the basis of both the first and second time-varying voltage applied to the capacitor

the definition of the logical status by obtaining a quantitative assessment of the result of this correlation analysis and

attributing a particular logical state of the logical value in accordance with a specified Protocol.

In the process according to the invention is preferable to conduct the correlation analysis in two stages. The first stage provides for the registration of temporal correlation between the specified voltage corresponding to the regime of weak signals, and at least one specified characteristic of the current response of the capacitor generated in the regime of weak signals. This check is conducted to determine the value (value), at least one parameter that characterizes the at least one specified characteristic of the current response of the capacitor generated in the regime of weak signals. The second stage correlation analysis provides for the registration of the correlation between the specified, by ENISA least one parameter and value, sign, and/or the second phase of the applied voltage, changing in time.

It is also preferred as an alternative to conduct correlation analysis in one step, by which establish a correlation between at least one specified characteristic of the current response of the capacitor generated in the regime of weak signals and a reference signal generated on the basis of both the first and second time-varying voltage.

It is also desirable for the second time-varying voltage applied to the capacitor, it was quasi-static voltage selectable polarity, which switch within the set of positive and/or negative values.

Alternative second time-varying voltage applied to the capacitor can have a low frequency or slowly changing value, for example, be a sinusoidal voltage.

In accordance with one of the preferred variants of the method as a first time varying voltage corresponding to the regime of weak signals, choose periodic voltage with a main component of the Fourier series with the frequency ω. When this register phase components of the current response at the frequency of the second harmonic. In dannemarie first stage correlation analysis is performed by using the phase reference signal, formed from the first applied to the capacitor time-varying, preferably sinusoidal voltage corresponding to the regime of weak signals.

In accordance with another preferred variant of the method as a time-varying voltage select two periodically varying signal with the main components of Fourier series with frequency ω1and ω2. Under this option register phase component of the current response to the sum and difference frequencies ω12and ω12and compare these phase with the reference phase. While the reference phase is obtained from these time-varying voltage applied to the capacitor, whereas these components periodically varying signals preferably are of the sine wave.

In addition, this option seems to be preferable to record the phases of two or more non-linear component of the current response at frequencies 2ω1and/or 2ω2and/or ω12and/or ω12. Then these phases is correlated with a reference phase derived from the same time-varying voltage applied to the capacitor. Alternatively, you can map these phase with the reference phase, p is obtained from a reference cell with a known logic state, to which are applied the same voltage.

According to another preferred variant of the method according to the invention, the registration of at least one characteristic of the current response of the capacitor generated in the regime of weak signals, provides for the registration, when two or more values of the second time varying voltage, the ratio of the current response generated in the regime of weak signals, for the first time-varying voltage to the value specified for the first time-varying voltage. Thus obtained ratio corresponds to the slope of the hysteresis curve.

It is considered preferable to choose a second time-varying voltage as low frequency or slowly varying bias voltage. This voltage varies within a given interval of positive and/or negative values. In particular, the second time-varying voltage, you can choose varying periodically between positive and negative values. Alternatively, this is the second time varying voltage can be selected in the form of smoothly changing voltage, overlapping voltage ranges between two positive or two negative values, or between the positive and negative values. In this case, the second time-varying voltage may be a sine wave and to periodically change the frequency of the lower frequency of the first time varying voltage.

In addition, when implementing the method according to the invention it is desirable that the specified Protocol was attributed to one of two possible logic States depending on the quantitative assessment.

The solution of the above objectives and the implementation of additional features and advantages provided by the use of the device for matching the phases in the implementation of the method according to the present invention. This device is characterized in that it contains:

a signal generator for supplying two or more read signals with predetermined phases by a memory cell connected to the generator and forming when applying readout signals signal response with two or more nonlinear current components;

out phase-sensitive detector connected to the memory and configured to implement out phase-sensitive detection of at least two phases in the signal response from the memory cell;

the source reference signal associated with the specified signal generator and configured to generate, based on the sum and difference of the phases of input read signals, the reference phase signal is Alov, supplied to the associated out phase-sensitive detector for detecting and correlating the specified component of the response, as well as for carrying out matching between the phase reference signals and at least one detektirovanii and correlated component of response, and,

at least one discriminatoire/logical circuit associated with the out phase-sensitive detector for receiving output signal, configured to determine the logical state of the memory cell.

It seems preferable to output the reference signal was associated phase control, providing out of phase signal with the phase of the ω+π and submitting the specified signal out phase-sensitive detector and, if necessary, in discriminatoire/logical path.

Finally, the solution of the above objectives and the implementation of additional properties and advantages can be achieved also by using a different device for matching phases in the implementation of the method according to the present invention. This alternative device is characterized in that it contains:

a signal generator for supplying a first periodic scanning signal superimposed on the second periodic readout signal of the lower frequency than the first read signal to the memory cell, under luceau to the generator and forming the signal response with frequency, equal to twice the frequency of the first read signal; and

out phase-sensitive detector/discriminator connected to the memory cell for receiving the signal and configured to obtain from the signal generator reference phase signals in the form of first and second readout signals, and correlating the phase of the signal response with the phase of one or both of the reference phase signals, and

out phase-sensitive detector/discriminator configured to determine the logical state of the memory cell by value and/or phase correlated in-phase signal response.

List of drawings

The above objectives and additional advantages and features of the invention will become clearer from the following detailed description of preferred variants of the invention, which should be read in conjunction with the accompanying drawings.

Figure 1 presents an example of known ferroelectric memory cell architecture 1T-1C, containing, as it was described above, one transistor and one ferroelectric capacitor.

Figure 2 illustrates a matrix structure with passive addressing, in which memory cells formed in areas of overlapping intersecting electrodes in the form of an orthogonal lattice, as has been described above.

On figa presents in General the form of the hysteresis curve for the storage ferroelectric substance type with a selection of some essential features.

On fig.3b high-frequency polarization response in the weak signal is represented as a function of history and the applied bias voltage.

On figa-4d are examples read by detecting the local slope of the curve, i.e. the polarization response as a function of voltage for a memory cell that is excited in accordance with the invention is represented by the signal voltage.

Figa illustrates the principle of counting by detecting the second harmonic in accordance with the present invention.

On fig.5b presents a block diagram of a known device for reading by detecting the second harmonic.

Figure 6 shows the block diagram of the device according to the invention is used for reading by parametric mixing.

Figa illustrates the principle of counting, strengthening the response of the second harmonic by using a periodically changing voltage offset.

On fig.7b presents a block diagram of a variant of the device according fig.5b used to read at strengthening the response of the second harmonic according to the invention.

Figa illustrates the principle of reading with periodic modulation of the response in the form of the second harmonic by means of a low-frequency bias voltage according to the invention.

On fig.8b presents a block schemavalidate device fig.5b, used to read at periodic modulation of the response in the form of the second harmonic according to the invention.

Information confirming the possibility of carrying out the invention

As described above, known methods for reading the logical state stored in the form of the polarization direction in the ferroelectric capacitor of the memory cell, typically use one of two approaches. The first one is used in each memory cell of microcenter; in this case, the polarization direction in the capacitor of the memory cell (i.e. its logical state) determines the bias on the gate of the transistor and, consequently, the current to the read amplifier associated with this cell. The second approach consists in the application to the ferroelectric capacitor voltage level which is sufficient to produce the inversion of polarization in the capacitor. Depending on whether this is the direction parallel or antiparallel to the applied voltage, the polarization will remain unchanged or its direction will be reversed. Although the first approach provides a non-destructive elucidation reading, as was shown in the analysis of the prior art, associated with serious problems in regard to both materials and processing data. The group of methods that belong to the who approach, corresponds to destructive reading and requires switching of polarization, which inevitably creates problems of fatigue, and leads to loss of data.

As will be described hereinafter with reference to the General characteristics of the response in part of the electric polarization of materials having the property of residual polarization, especially ferroelectrics, there are alternative ways of reading that are non-destructive elucidation, easy to implement and compatible with schemes both active and passive matrix addressing. However, the physical processes associated with such a reading, are numerous and complex. Therefore, the specific scheme of reading need to pick up materials, architectures and time scales of interest in each specific situation.

In accordance with the present invention the logic state, i.e. the polarization direction in a given cell of the memory device is determined by registration of the nonlinear response in the form of changes in electrical impedance of the specified memory cells when applying a time varying voltage. When this voltage level is chosen substantially smaller than that required to reverse the polarization in the cell. As will be shown, this nonlinear response can sootvetstvenno, depends on the voltage in the region of small signals, and the value of this impedance is correlated with the bias voltage, which allows to determine the logic state of the cell. Alternative nonlinearity leads to the response frequency spectrum than the spectrum of the exciting voltage. When this phase and/or level of a specified component of the nonlinear response will be different depending on the logical state of the cell.

In the context of the present invention, it is important to distinguish between the polarization response due to interactions with dipoles, which are responsible for the residual polarization, and the response generated by the quasi-bound mobile charges, which accumulate in response to polarization, asked these dipoles and field imposed by the electrodes. This circumstance affects the frequency and pulse protocols of reading that can be used in each case, the possible limitations that may occur in the selection of materials for the electrodes.

With respect to the first occasion on figa shows a typical hysteresis loop, which illustrates the response of the pre-polarized environment on the application of an external voltage to the electrodes of condens tropolone patterns. The voltage, which in this case varies periodically between two extreme values with positive and negative polarities, as can be seen in the drawing. These changes in the voltage range from +V to-V correspond to the change in polarization when switching between positive and negative saturation levels, i.e. in the interval R*. Through Vc+Vc - labeled positive and negative values of the coercive voltage corresponding to points of intersection of the hysteresis curve to the abscissa axis. Point "0" and "1" correspond to the positive and negative values of the residual polarization of PRcorresponding to the two stable States of the ferroelectric polymer.

Throughmarked change in the polarization after switching from "1" to state "0", i.e. when the voltage changes from +V to 0.

As can be seen from tiga, the relationship between strain and polarization is complicated because the local polarization P as a function of the applied voltage V at a given point of the curve depends on the background in relation to the polarization/voltage. In addition, the local polarization is non-linear both on the macroscopic and microscopic levels. On the local dependence of the polarization of the voltage differences, hung is the following from the logic state, i.e. from the fact whether the previous state logical "0" or logical "1". These differences can be used to create funds non-destructive elucidation of reading a logical state.

Marked differences occur in the form of polarization response to weak signals, which depend on the position on the curve. When this polarization response to a weak signal may contain both linear and nonlinear components of the response in relation to the applied vozbujdayuschego voltage corresponding to the region of weak signals. Accordingly, the complex impedance for the weak signal detected in the cell, is made in the form of a capacitor containing material with the characteristics shown in figa, can be analyzed in correlation with the voltage applied to the capacitor. The analysis has to determine the logical state of the memory cell.

It should be noted that the frequency of the applied voltage corresponding to the offset and a weak probe signal must be chosen low enough so that the polarization caused by the dipoles could follow their changes. Depending on material, temperature, and other factors, the maximum frequency can vary within wide limits (from hundreds of Hz to GHz). When this reorganise the Kie ceramic ionic ferroelectric have a rapid response, while polymer ferroelectric-based alignment of molecules react significantly slower.

Next will be considered the second case, when the polarization response due to the quasi-bound or mobile charges, which are accumulated under the influence of internal fields in the material. Analysis of scientific literature shows that the basic phenomena of asymmetry, depending on the polarization, namely the dependence on bias and nonlinear response is, apparently, the General properties of all ferroelectric materials placed in kondensatoprovodov patterns of interest in the context of the present invention. Although in many cases the level of polarization response is sharply reduced, the above statement applies even in the frequency domain, far superior frequency, which may be followed by polarization in the ferroelectric. Consequently, these phenomena are not appropriate to explain in terms of the hysteresis curve presented on figa.

In accordance with the present invention the logic state, i.e., the direction and/or the level of residual polarization, determined by using the nonlinearity inherent in the polarization response of the material to which the applied electric field. Hereinafter will be described in two different basic approach.

In accordance with the first mother of the l is exposed to the excitation voltage, the appropriate level of weak signals superimposed on the bias voltage, and at the same frequency as the frequency of the probe voltage, determine the polarization response as a function of bias voltage. The curve of the polarization response in the weak signal is shown in General form in fig.3b. When the response is logged on the same frequency that causes him stress, this response simply corresponds to the capacity that depends on the bias voltage and is associated with the polarization state of the material. It is important to understand that while the same qualitative behavior, there is a fundamental difference between the physical mechanisms leading to such curves due to the interaction with the accumulated quasi-bound or mobile charges, on the one hand, and with the curves obtained by the sensing curve hysteresis weak signals, on the other hand.

Given the similarity of some schemes for reading, which will be described hereinafter, the description of the preferred options based on the principles that are illustrated figa-4d, will be given in terms of local response to weak signals in various parts of the hysteresis curve. This will ensure an easy intuitive understanding of the principles implemented by the invention. However, it should be understood that the technical description of the reader Protocol and the s supply voltage applies to all cases when you are sensing quasi-bound and/or moving charges. The last case will not only cover the frequency ranges, which may be complete or partial inversion of the polarization (confirm hysteresis curves), but also-and high-frequency ranges, where the switching domains cannot follow the frequency.

In this connection it may be noted that the sense proposed by Brennan in the aforementioned U.S. patents are fully based on the interaction with the accumulated spatial charges in accordance with a specific model, according to which the sensed spatial charges are near each electrode in the presence of between neutral zone. While the relative size of the neutral zone and zones of finding spatial charges determine the perceived capacity. This puts scheme proposed by Brennan, outside the scope of that part of the analysis, which is based on the hysteresis curves. In addition, they ignore many other physical phenomena, leading to the characteristics of the response to a weak signal, such qualitative representation shown in fig.3b.

In accordance with the second approach, the material acts as a parametric mixer, depending on the polarization state, and in the output response, in addition to the frequencies present in a weak exciting voltage, contains new frequency components. Thus, the effect on the polarization at a given frequency causes the polarization response and, therefore, the detected current, which, in addition to the fundamental frequency, also contains its harmonics. If the excitation voltage contains multiple frequency components, the response may contain, in addition, the components corresponding to the sum and difference of these frequencies, with a specific phase relations, which can be explicitly tied to the state of the residual polarization of the environment.

In this case, a description of the following examples are given with reference to the hysteresis curves, providing a simple, intuitive approach to the understanding of the principles underlying the invention. However, as mentioned previously, the same General principles of reading and related devices will be applicable in high-frequency ranges, in which the switching polarization, reflected in the curves of the hysteresis cannot follow the frequency, being bound to quasi-bound or mobile spatial charges.

Some preferred variants of the invention are described hereinafter in the form of examples 3, 4 and 5. They represent General classes of possible implementations, with General the sign: the excitation of the memory cells of a weak signal for to call, as a consequence of the nonlinearity and asymmetry caused by background, polarization response, depending on a logical condition. In order to simplify the discussion will be taken that the polarization response to the application of a small voltage, changing in time, will follow in the forward and reverse direction along the side of the curve shown in figa. This assumption ignores the effects of partial switching and fatigue, which lead to a gradual decrease in the level of polarization, and to the fact that the polarization response to the small signal itself exhibits hysteresis.

Before mentioned will be described the preferred options will be discussed in detail two examples, giving an overview of the principles underlying the present invention, and illustrating these principles.

Example 1. Differences with respect to the polarization response in the weak signal

The slope of the hysteresis curve, i.e. the linear polarization response in the weak signal is the first derivative dP/dV of the specified curve, depends on the voltage and history. Presented at Figo standard curve has the same slope for the two logic States "0" and "1", and the measurement of the slope at these points will not reveal the logical status. Applying a certain voltage V and underwa characteristic slope in the vicinity of the points "1" and "0", you can define a Boolean condition. We introduce the following notation:

The slope in the vicinity of "0" when the voltage V offset: Slope"0"(V);

the slope in the vicinity of "1" when the voltage V offset: Slope"1"(V).

From figure 3 it follows:

Tilt"0"(+ΔV)<Tilt"1"(+ΔV);

Tilt"0"(-ΔV)>Nikon"1"(-ΔV).

Thus, the logic state of the corresponding cell can be read by application of a bias voltage of known magnitude and polarity and check the slope of the hysteresis, at least in two points of this curve. This operation may be performed in various ways.

(a) By registering the angle at two or more discrete values of the bias voltage, as shown in figa, and comparing the difference of the angles with the threshold value.

(b) By tracking the values of the polarization response in the regime of weak signals when applying the excitation voltage representing a voltage that changes in the regime of slow periodic scan overlaid with a small periodic variation in voltage with a higher frequency, as shown in fig.4b.

(C) By registering the differential polarization between the selected discrete points on the curve hysteresis. An example is given on figs.

For the logical state "0" are:

|P(+ΔV)-P(0)|<|P(0)-P(-ΔV)|,

while the logical state "1":

|P(+ΔV)-R(0)|>|R(0)-R(-ΔV)|.

(d) By registering the asymmetry of the magnitude of polarization (from maximum to minimum, RMS, and so on) when the application of voltage scan positive and negative polarity. An example illustrating two separate sweep, shown in fig.4d. However, the asymmetry can be detected and other methods obvious to a person skilled in the field of electronics.

Example 2. Detection of response to sinusoidal input voltage frequency harmonic distortion

The following simple consideration can be useful for an intuitive understanding of the main ideas.

Returning to figa, it is desirable to determine in which the logical state "0" or "1" is the storage material in the corresponding memory cell. These two logical States are characterized by different values of the curvature at the points where the hysteresis curve crosses the axis V=0. Using the decomposition of the second order, you can write:

(1) P("0")=P0+αV-βV2;

(2) P("1")=-P0+αV+βV2

Next, let us assume that the cell is excited by a sinusoidal voltage with amplitude much smaller than that required for switching the polarity of the cell (with the. figa). In this case:

(3) V(t)=V0cos(ωt).

Then the polarization response can be represented as:

(4) P("0")=R0+αV0cos(ωt)-βV

2
0
cos2(ωt)

=(R0-0,5βV

2
0
)+αV0cos(ωt)+0,5βV
2
0
cos(2ωt+πand

(5) P("1")=-R0+αV0cos(ωt)+βV

2
0
cos2(ωt)

=-(R0-0,5βV

2
0
)+αV0cos(ωt)+0,5βV
2
0
cos(2ωt).

Thus, the polarization response of the memory cell at the frequency of the second harmonic depends on what state ("0" or "1") is the cell. More specifically, the responses for these two States at a frequency of the second harmonic n which are in antiphase (i.e. mutually shifted in phase by 180°). Using the appropriate method of detection, such as coherent averaging (synchronous detection), the difference between these two responses can be quantified, for example in the form of positive or negative polarity detektirovanie signal.

The known device for detecting polarization response at the frequency of the second harmonic is represented on fig.5b in the form of a simplified block diagram. On fig.5b shown that the signal generator supplies a sinusoidal voltage with frequency ω to the memory cell from which the signal containing harmonic components goes on out phase-sensitive detector. In preferred embodiments, the implementation of out phase-sensitive detector can be considered as a combination of out phase-sensitive detector and discriminator. The signal generator simultaneously generates the input reference phase signal to the reference signal, which feeds the reference signal with a frequency corresponding to twice the frequency ω the read out signal on out phase-sensitive detector. The output voltage from out phase-sensitive detector will depend on the logical state of the memory cell. The result is a valid logic state will correspond to a simple quantitative parameter, i.e. opposite the tee detected signal.

As is easily seen, and as is well known to experts in the field of signal analysis, nonlinearities of higher order in the polarization response of the memory cell in the General case will result in detektiruya signal higher harmonics. Using the basic principles described above, and taking into account the specific characteristics of the response of the analyzed memory cell, similar components of the signal can also be extracted from the total signal in order to obtain information about the direction of polarization and, consequently, about the logical state of the cell. Thus, consider an example related to the detection of the second harmonic should not be considered as not allowing the detection of harmonics higher than the second when determining the logical state of the corresponding cell.

As already mentioned, hereinafter will be described some preferred embodiments, which are in any respect shall not be construed as limiting the actual scope of the invention.

Example 3. Detection of sum and difference frequencies in response to the filing of two mutually superposed input voltage

Similar to the discussion of the previous Example can be carried out a simple analysis for the case when the excitation of the memory cell can be represented by a sum of the Vuh sinusoidal voltages at two different frequencies ω 1and ω2. In this case we have:

(6) V(t)=V1cos(ω1t)+V2cos22t)

moreover, the polarization response takes the form:

(7) P("0")=[P0-0,5βV

2
1
+V
2
2
)]+α[V1cos(ω1t)+V2cos(ω2t)]

+0,5β[V

2
1
cos(2ω1t+π)+V
2
2
cos(2ω2t+π)+2V1V2cos((ω12)t+π)+cos((ω12)t+π)]

and

(8) P("1")=-[P0-0,5β(V

2
1
+V
2
2
)]+α[V1cos(ω1t)+V2cos(ω2t)]

+0,5β[V

2
1
cos(2ω1t)+V
2
2
cos(2ω2t)

+2V1V2cos((ω12)t)+cos((ω12)t)].

You can see that these expressions reduce to the expressions (4) and (5) at

V1=V2=V0/2 ω12=ω.

In addition to linear, time-dependent responses at frequencies ω1and ω2as well as the responses at frequencies of 2ω1and 2ω2the second harmonic, in this case, the response also appear components at sum and difference frequencies (ω12and (ω12), as shown in Fig.6. Similar to the situation discussed in the previous paragraph, these components correspond to the logical States "0" and "1"are out of phase relative to each other. This provides an alternative non-destructive elucidation of the read data. It is also possible to choose values ω1and ω2thus, to the frequency, which is the detection, i.e. (ω12or (ω12), was convenient for measurement range, for example, where the spectral density of the noise is the tsya low, and/or one in which the optimal frequency for the loop receiving and signal processing. It is also possible to discriminate those harmonics of the exciting voltage, which penetrate into the contour detection through mechanisms that are not associated with the interests of the polarization response (for example, due to the nonlinearity in the driver or detector circuits).

The device according to the present invention designed for detection at frequencies corresponding to the sum and difference frequencies ω1and ω2the input sinusoidal voltage, represented as block diagrams figure 6. In this device, the signal generator generates signals with frequencies ω1and ω2and supplies them to the memory cell. The response of the memory cell comes to out phase-sensitive detector, which produces a detection respectively of the total frequency ω12or the difference frequency ω12. The source reference signal associated with the signal generator to receive the reference phase signal and to apply the reference signals at the sum and difference frequencies out phase-sensitive detector. Out out phase-sensitive detector connected with discriminatoire/logic circuit designed to perform the necessary mapping phases of the La, to determine a valid logical state of the memory cell. As an option between the reference signal and the out phase-sensitive detector may include a phase control that provides the feed out phase-sensitive detector and possibly discriminatoire/logical circuit reference signal, out of phase with π relative to the original phase of the signal.

Because the logical state of the cell is manifested in the phase response at the same time on several different frequencies (namely 2ω1, 2ω2that ω12and ω12), correlation of the results of the phase detection can be performed on two or more frequencies in order to increase the reliability and/or speed of each read operation.

Example 4. Detection of nonlinear response in the case when the input voltages are low frequency offset.

Almost a universal feature of nonlinear responses in the substance is a strong dependence on the amplitude of the excitation. As mentioned earlier, in the framework of the present invention it is necessary to choose the stimulation that is strong enough to allow for rapid and reliable detection of nonlinear response, and at the same time be sufficiently weak so that the polarization remember what the material is not weakened and have not experienced invert.

An alternative strategy to increase the level of detected signals is to shift the operating point in this area on the hysteresis curve in which the curve shows a strong nonlinear dependence of the polarization between the response and the applied voltage. This strategy can be illustrated by Piga and 7a.

For example, assume that the cell is in logical state "1" and that the sensing response at the frequency of the second harmonic of the applied small field varying sinusoidally with frequency ω. But now there is also slowly changing, i.e. low-frequency bias voltage. This voltage can be selected so that the specified image to place the operating point on the curve hysteresis:

(9) V(t)=Voffset+V0cos(ωt).

For simplicity, let us assume that the second harmonic is directly proportional to the positive or negative curvature of the hysteresis curve at the operating point. When considering the curve 3A shows that for a cell in the logical state "1" signal of the second harmonic will increase as Voffsetincreases from 0, approaching Vc/3 (in practice, the maximum voltage in the memory with passive matrix addressing should be Vc/3 in order to avoid disturbance to other cells of the matrix). For a cell is the logical state "0" signal of the second harmonic is out of phase relative to the signal state "1". Thus with increasing Voffset0 this signal will remain small.

On the contrary, if Voffsetis negative, the result is changed to mirror the ones described. As the bias voltage has a greater absolute value of the negative value, the signal corresponding to the second harmonic remains weak, if the cell is in logical state "1", and increases for the cell in the logical state "0".

Thus, in addition to the possible increase of the signal of the second harmonic of the supply bias voltage causes an additional phenomenon that can be used to detect the logic state of the cell, as shown in figa. The amplitude of the signal corresponding to the second harmonic, of the cell in the logical state "1" is incremented by the application of a bias voltage of positive polarity and remains small negative values of the bias voltage. When the cell is in state "0", the signal increases when applying the bias voltage of negative polarity and remains low in the case of positive polarity. Among several protocols supply excitation voltage, which can be used to read data on the basis of this asymmetry, the preferred option includes consistently the TB measurements with supply various of the slowly varying (low frequency) voltage offset. As an example, you can specify a simple case of the two measurements of the amplitude and phase of the second harmonic. One of them is held at +Voffsetand one at Voffset. If the cell is in logical state "1", it will manifest itself in a significant signal of the second harmonic, which is correlated in phase with a reference signal in the case of +Voffset. Occasion-Voffsetcorresponds to a lower common-mode signal of the second harmonic. If the cell is in logical state "0", if +Voffsetthe signal corresponding to the second harmonic will be small and are out of phase with a reference signal, and in the case of Voffsetsignificant, but again out of phase.

To implement the non-linear detection response according to the invention when using the slowly varying (low frequency) signal offset can be used variant of the device presented on fig.5b. This embodiment of the device generally corresponds to the block diagram shown in fig.7b. The signal generator delivers periodic, for example sinusoidal, the read signal superimposed on the bias voltage in the form of a slowly varying periodic voltage offset or alternatively in the form of low-frequency bias voltage. The memory cell generates a signal response that contains the component h which depends 2ω that is input to the combined out phase-sensitive detector/discriminator to determine the logical state of the memory cell. Combined out phase-sensitive detector/discriminator is also connected with the signal generator, which receives the reference signal, for example, in the form of a sinusoidal voltage with frequency ωsuperimposed, as shown in the drawing, the voltage offset.

Example 5. Frequency detection response with the use of a bias voltage and a sinusoidal voltage with substantially different frequencies and amplitudes.

Another preferred variant of the invention, using the asymmetry dependence of the response on the frequency of the second harmonic from the offset provides for the filing of smoothly changing the bias voltage, i.e. a sinusoidal bias voltage to frequency Ω, which is substantially less than the frequency ω voltage, which excites the second harmonic (see figa, b). In this case,

(10) V(t)=VOFFSETcos(Ωt)+V0cos(ωt).

The example corresponds to the special case already considered excitation at two frequencies. However, now Ω<<ω, a Voffset>>V0. Since the coefficient of β nonlinear response in expressions (1) and (2) depends on the bias voltage, one can imagine there is existing an implicit time dependence, as

(11) β=β(VOFFSETcos(Ωt)),

i.e. a first-order approximation of the response corresponding to the second harmonic modulated with frequency Ω. Dependence β from the bias voltage determined by the material used, however, the behavior of the polarization response at a frequency of 2ω in time can be very difficult. However, the hysteresis curve having the General shape of the type shown in figa will correspond to the response at the frequency of the second harmonic, which is modulated in amplitude. For the logical state "1" the response has a maximum at time tpwhen the bias voltage reaches its peak value at positive polarity. For the logical state "0" maximum response frequency of the second harmonic coincides with the peak of the negative polarity bias voltage, i.e. the time tp+π/Ω. And in this case, the signals corresponding to the second harmonic, are in antiphase. Using data analysis, expert in the field of electronics will be able to design electronic equipment, which will be able to determine which logical state ("0" or"1") is interested in the cell.

In case of detection of the response using a bias voltage and a sinusoidal voltage, as described in the previous the current example, can be used variant of the device presented on fig.7b. The block diagram of this option presents on fig.8b. It includes a signal generator that supplies a memory cell of a sinusoidal voltage with frequency ωsuperimposed on the slowly varying sinusoidal bias voltage with a low frequency Ω. Component of the response with frequency 2ω served from a cell on out phase-sensitive detector/discriminator to determine the logical state of the memory cell. The signal generator produces a phase reference signal with a frequency of 2ω for reception of signals in antiphase relative to the signal of the second harmonic and an offset signal with frequency Ω to register the signal level of the response.

As described concept to read data does not cause the inversion of polarization in the medium, it has significant advantages, the main of which are the following:

Because reading is non-destructive elucidation, no cycle writeback, thanks achieved performance and easy storage.

In all known storage media having practical value, fatigue depends on the number of investirovanie polarization that occurred in the material. Eliminating the switching field is Itachi in the process of reading the data indicates a dramatic increase in the service life of the storage devices of almost all types, since read operations are typically executed much more frequently than write operations.

In the case of detecting the total frequency or harmonic frequency discrimination between logical States "0" and "1" can be implemented in terms of qualitative criteria, such as determining the polarity of the voltage, instead of spending the analog detection threshold voltage on a continuous ("gray") scale. This can lead to the simplification of contours, located at the output of the decoding, in which the decision concerning the logical status.

Finally, the use of two voltage bias with appropriately chosen frequencies, amplitudes and durations will allow you to apply the scheme of the detection based on correlation methods, which dramatically increases the ability to determine the logical state of the memory cell with non-destructive elucidation reading using only the responses in the regime of low signal.

1. The method for determining the logical state of the memory cell storage device that stores data in the form of a status of the electrical polarization of the capacitor, which contains the polarizable material is able to maintain stable electrical polarization in the absence of external voltage supplied to the capacitor and d is to generate current in response to the applied voltage, moreover, the current response contains linear and nonlinear components, characterized in that it includes the following operations: application to the condenser of the first time varying voltage corresponding to the regime of weak signals, the amplitude and/or duration which is selected smaller than that required to create a significant permanent changes the polarization state of the capacitor; application to the condenser of the second time-varying voltage, which is formed with a first time-varying voltage, and the amplitude and/or duration of the sum of the first and second voltages changing over time, choose smaller, than this is required to create significant permanent changes in the polarization state capacitor; registering at least one characteristic of the current response of the capacitor generated in the regime of weak signals with linear or nonlinear dependence on the first and/or second applied voltage, time-varying, conducting correlation analysis based on the use of correlating the reference signals generated on the basis of both the first and second time-varying voltage applied to the capacitor; determining a logical state by obtaining quantitative cancertutor specified correlation analysis and attribution to a particular logical state of the logical value in accordance with a specified Protocol.

2. The method according to claim 1, characterized in that the correlation analysis is carried out in two stages, the first of which provides for the registration of temporal correlation between the specified voltage corresponding to the regime of weak signals, and at least one specified characteristic of the current response of the capacitor generated in the regime of weak signals, to determine the value (value), at least one parameter that characterizes the at least one specified characteristic of the current response of the capacitor generated in the regime of weak signals, while the second stage correlation analysis provides for the registration of the correlation between the specified at least one parameter and value, sign, and/or the second phase of the applied voltage, changing in time.

3. The method according to claim 1, characterized in that the correlation analysis is performed in one step, by which establish a correlation between at least one specified characteristic of the current response of the capacitor generated in the regime of weak signals and a reference signal generated on the basis of both the first and second time-varying voltage.

4. The method according to claim 1, characterized in that the second time-varying voltage applied to the capacitor, is quasi-static tension is the group of arbitrary polarity.

5. The method according to claim 4, characterized in that the second time-varying voltage applied to the capacitor, switch between a set of positive and/or negative values.

6. The method according to claim 1, characterized in that the second time-varying voltage applied to the capacitor, has a low frequency or slowly changing value.

7. The method according to claim 6, characterized in that the second time-varying voltage applied to the capacitor, is a sinusoidal voltage.

8. The method according to claim 2, characterized in that as a first time varying voltage corresponding to the regime of weak signals, choose periodic voltage with a main component of the Fourier series with the frequency ωlog phase components of the current response at the frequency of the second harmonic and perform the first stage of the correlation analysis using the phase reference signal generated from the first applied to the capacitor time-varying voltage corresponding to the regime of weak signals.

9. The method of claim 8, wherein the first time-varying voltage corresponding to the regime of weak signals is a sinusoidal voltage.

10. The method according to claim 1, characterized in that the following time-varying n is prajini choose two periodically varying signal with the main components of Fourier series, with frequency ω1and ω2log phase component of the current response to the sum and difference frequencies ω12and ω12and compare these phase with a reference phase derived from these time-varying voltage applied to the capacitor.

11. The method according to claim 10, characterized in that the specified components periodically varying signals are sinusoidal voltage.

12. The method according to claim 10, characterized in that register phases of two or more non-linear component of the current response at frequencies 2ω1and/or 2ω2and/or ω12and/or ω12and compare these phase with a reference phase derived from the same time-varying voltage applied to the capacitor.

13. The method according to claim 10, characterized in that register phases of two or more non-linear component of the current response at frequencies 2ω1and/or 2ω2and/or ω12and/or ω12and compare these phase with the reference phase received from the reference cell with a known logic state, to which is applied the same voltage.

14. The method according to claim 1, wherein registering at least one characteristic of the current response is condensator, generated in the regime of weak signals, provides for the registration of two or more values of the second time varying voltage ratio current response generated in the regime of weak signals, for the first time-varying voltage to the value of the specified first time-varying voltage, and the ratio corresponds to the slope of the hysteresis curve.

15. The method according to 14, wherein the second time-varying voltage is chosen in the form of low frequency or slowly varying bias voltage that varies within a specified interval of positive and/or negative values.

16. The method according to item 15, wherein the second time-varying voltage is chosen in the form of a voltage varying periodically between positive and negative values.

17. The method according to 14, wherein the second time-varying voltage is chosen in the form of smoothly changing voltage, overlapping voltage ranges between two positive or two negative values, or between positive and negative values.

18. The method according to 17, wherein the second time-varying voltage is chosen in the form of a voltage periodically changing with a frequent is the the lower frequency of the first time varying voltage.

19. The method according to 17, wherein the second time-varying voltage is chosen in the form of a sine wave.

20. The method according to claim 1, characterized in that the specified Protocol assigns one of two possible logic States depending on the quantitative assessment.

21. A device for matching the phases in the process, as claimed in claim 1, characterized in that it contains a signal generator for supplying two or more read signals with predetermined phases by a memory cell connected to the generator and forming when applying readout signals signal response with two or more nonlinear current components out phase-sensitive detector connected to the memory and configured to implement out phase-sensitive detection of at least two phases in the signal response from the memory cell, the reference signal associated with the specified signal generator and configured to generate, based on the sum and difference phases of the input read signals of the reference phase signal applied to the associated out phase-sensitive detector for detecting and correlating the specified component of the response, as well as for carrying out matching between the phase supports the diversified signals, and at least one detektirovanii and correlated component of response, and at least one discriminatoire/logical circuit associated with the out phase-sensitive detector for receiving output signal, configured to determine the logical state of the memory cell.

22. The device according to item 21, wherein the output reference signal is associated phase control, providing out of phase signal with the phase of the ω+π and submitting the specified signal out phase-sensitive detector, and optionally in discriminatoire/logical path.

23. A device for matching the phases in the process, as claimed in claim 1, characterized in that it contains a signal generator for supplying a first periodic scanning signal superimposed on the second periodic readout signal of the lower frequency than the first read signal to the memory cell connected to the generator and forming the signal response with a frequency equal to twice the frequency of the first periodic scanning signal, and out phase-sensitive detector/discriminator connected to the memory cell for receiving the signal and configured to obtain from the signal generator reference phase signals in the form of first and second readout signals, and korrelirovana the phase signal response with the phase of one or both of the reference phase signals, and out phase-sensitive detector/discriminator configured to determine the logical state of the memory cell by value and/or phase correlated in-phase signal response.



 

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