Semiconductor memory device

FIELD: semiconductor memory devices.

SUBSTANCE: device has a lot of memory elements, each of which contains input and output areas, isolating film, channel area, shutter electrode, area for storing electric charges, device also contains large number of periphery circuits, containing reading amplifier, register for storing recorded data of memory elements, register, which preserves the flag, indicating end of record during its check, and circuit, which after recording operation compares value, read from memory cell, to value, fixed by flag at the end of record, and overwrites value indicated by the flag.

EFFECT: higher reliability of operation.

5 cl, 71 dwg

 

The present invention relates to a semiconductor memory device and semiconductor memory element.

Currently known non-volatile memory devices such as electrically erasable programmable permanent memory (EEPROM) flash type, which uses a MOS transistor device with floating and control gates. In such devices the storage and reading of information is due to the fact that the accumulation of charge carriers on the floating gate there is a change in the threshold voltage of the MOS transistor. Usually in the floating gate using polycrystalline silicon. The use of a MOS transistor with a floating gate allows using only one transistor to store one bit of information over long periods of time. As examples of the EEPROM or flash type can be called a normal memory cell and a contactless memory cell, which is described in Nikkei Electronics, No. 444, p.151-157 (1988).

Manufacturing technology of such devices are described in the work of K. Yano and others, 1993 IEEE International Electron Devices Meeting, Digest of technical papers, SCR-545 and work Kuapa and others, 1996 IEEE International Solid-State Circuits Conference, Digest of technical papers, str-267 458), in which we are talking about single-electron memory devices that use policriti the symbolic silicon. According to this technology in a thin layer of polycrystalline silicon are formed simultaneously channel, which is the current conductor, and the storage area, in which the capture of electrons. Information is stored by changing the threshold voltage electron capture in the capture area of the charge. A feature of this method is that the storage of one bit of information occurs when the capture of one electron. This technology allows you to make the device smaller in size than devices fabricated using crystallites of polycrystalline silicon, and is made in such a way that the devices can operate at room temperature.

To test the change of the threshold voltage in the flash EEPROM type with injection and drain of the charge carrier with the floating gate (the write operation and erase operation) is controlled his condition after the supply voltage is high level (or low level), and then checks, during which re-supply voltage and the regulation of the threshold voltages of those memory cells whose threshold voltage is not reached.

Technology such inspection of the storage device described in T. Tanaka and others, IEEE J. Solid-State Circuits, I. 29, No. 11, str-172 (1994), K. Kimura et al., IEICE Transactions of Electronics, so I, No. 7, str-837 (1995).

The technology that was previously used by the authors of the present invention, described in lined with the Japan patent No. Hei 7-111295, Hei 8-288469, Hei 9-213822 and Hei 9-213898.

Wide use in recent years, methods of lithography have enabled us to achieve great progress in creating a small area of memory cells such as dynamic memory with random access (ZUPU), a static storage device, random access (STOPV) and mass storage devices like flash memory. Having a small area of memory cells offer significant advantages, such as the ability to reduce the size and increase the yield of chips, and also reduce their costs by increasing the number of chips produced from the same size semiconductor wafer. Another advantage of a small area of memory cells is the possibility of reducing the length of the connections and the resulting increase their performance.

Manufacturing dimensions and the dimensions of the cell are determined mainly by the method of manufacture. If the underlying process size is equal to F, then ZUPU with a bent bit bus will have a size equal to 8F2, and flash memory schema type "And" will be the size, R is wny 6F2. Memory cells with smaller sizes can be manufactured by executing the flash memory on a single transistor, thus believe that the creation of memory cells with smaller dimensions in comparison with cells produced in the form of MOS transistors are made on the surface of the substrate, is almost impossible. To create cells with smaller dimensions is necessary, obviously, to use three-dimensional constructions of cubic form. When reducing the size of storage devices by giving them a cubic form and by reducing the step between the information tire or a dictionary (or numeric) tires size, the smaller the minimum size 2F, there are serious and intractable problems associated with the location information of the tire and dictionary of the tire, with the necessity of connection of cells with peripheral circuits and need to manage memory array composed of individual cells, such peripheral circuits.

On the other hand, when the injection and extraction of electrons in microscopic size particles of metal or semiconductor can be used effectively resulting in electrostatic repulsive force, and thus theoretically one electronic element, which controls the transfer of electrons in separate modules that can work in very small structures p is row 10 nm, while consuming very low electric power. Single-electron memory, representing one-electron memory device capable of storing information by accumulating a small number of electrons. Single-electron memory can store one or more bits of information in a single element, and because the management of stored electric charge can be performed in separate modules, such storage devices can operate at a thickness of about one nanometer. In addition, if the number stored or accumulated in the memory of the electrons such devices should have a significant advantage by reducing time rewriting and increase the number of possible transfer. But really in the manufacture of such elements of their technological dimensions depend on restrictions imposed on the current by the process of lithography. In addition, because of the rather large size of the removed areas of the drain and the source is not possible on the basis of existing elements to create the element, which due to its small size could be successfully used in various integrated circuits.

It was fabricated and tested operating at room temperature single-electron memory device. It is established that d is I the accumulation of electric charge by applying to the same device, the same voltage recording during the same time you want to spend different times. In other words, it was found that when applying the same voltage recording during the same time in such a device accumulates a different number of electrons. This phenomenon can be explained by random probabilistic nature of proceeding in the device processes, in particular process associated with the tunnel effect, or process of thermal excitation, due to the small number of electrons participating in the one-electron mass storage device.

The progress made in the establishment of an integrated semiconductor memory devices and allowed to increase the density in the individual memory cells and to increase the capacity of the device, associated with an increase in the cost of the equipment, which is used for manufacturing devices with a high degree of integration. The density of the memory device can be significantly enhanced when a multivalued logic, save in one cell of two or more bits, without resorting to greater integration forming device memory cells. When the multivalued data storage of special importance is the problem with the ability to clearly distinguish between the state of the memory cells, performing a write operation, reading and erasing the accumulated information.

The use of single-electron memory device is required, to the value of the charge was small and to the peripheral circuit did not create a big noise. In the semiconductor storage device as read amplifiers often use differential amplifiers. When this amplifier reads typically have relatively a data bus so that the matching data bus were performed either open and located on both sides of the read amplifier, or bent in the same direction. Open execution matching tire has a certain advantage, since this memory cell can be placed at all points of intersection of information tires and dictionary of the tire, thereby ensuring a high degree of integration of the device. However, this scheme does have some disadvantage associated with a high level of noise arising in the dictionary tires. The advantage of devices that have matching tires made bent, is the low level of noise arising in the dictionary the tires, but such devices have the disadvantages that are associated with the inability of the location of the memory cells in all the points of intersection of information tires and dictionary of the tire and with the inability to provide such devices with a high degree of integration.

To peripheral schemes, under which you want the greater the I area, in addition to the read amplifier includes a register which temporarily stores the recorded information during recording, the register that holds a flag which indicates the end of recording during the test, and the scheme that after the write operation compares the value read from the memory cell with the value recorded by the box in the end of the record, and rewrites a value that indicates the box.

Considering the above, to expand the limits that imposes certain restrictions on the current storage device, in the present invention are the following tasks: create a single-electron memory cell, the most suitable for the development of storage devices with a high degree of integration on a small area, creating a semiconductor memory device, protected from possible failures associated with the phenomena of random probabilistic nature, the creation of a semiconductor memory device, solving the problem of keeping multiple stored in its memory values, creating occupying a small area of the peripheral circuits that do not have a negative impact on the characteristics of occupying a small area of the memory device and single-electron memory device with high integration level, topic : creating and having a low noise level of the peripheral circuit, most suitable for single-electron memory devices, working with a small electric charges and sensitive to the influence of noise.

In particular, in the present invention in its basic version offers a semiconductor memory device containing a large number of memory elements, each of which contains a region of the source and drain region, located one above the other, an insulating film located between the areas of the drain and the source, channel region contained in the semiconductor connecting region of the source with the drain region, the gate electrode to create an electric field in the channel region, a region for storing electric charges, separated from the channel region by a potential barrier, which is memorized specified a large number of memory elements when changing the conductivity of the specified channel region in accordance with the number of charges, while the semiconductor storage device also contains a large number of peripheral circuits, designed for transmission of signals to the information and vocabulary tires and contains the amplifier is read, the register to store the recorded information of the memory elements, the register that holds a flag which indicates the end of recording during the test, and the scheme that after surgery the recording compares the value read from a memory cell, with the value recorded by the box in the end of the record, and rewrites a value that indicates the box, and at least part of these peripheral circuits is a CMOS elements, consisting of the n-channel MOS transistors and p-channel MOSFETs.

In the invention it is proposed another variant of the semiconductor memory device having multi-layered structure and containing the first local information bus, the first intermediate layer over the first local data bus, the bus source above the first intermediate layer, second intermediate layer over the bus source, the second local information bus over the second intermediate layer, and these first and second intermediate layers are insulating films, the first channel region connected to the bus of the source and the first local data bus and located on the side of the multilayer structure, and the second channel region connected with the second bus source and a second local data bus and located on the side surface of the layered structure above the first channel region, the grip area of the electric charge is surrounded by a potential barrier and located in close proximity to the first and second channel regions or inside the ka is a pressing region, located on the side of the multilayer structure, and vocabulary bus that is connected to the channel region through an insulating film shutter, and two semiconductor memory element located above the points of intersection and under the points of intersection of the first and second local information tire and dictionary tires, in which information is stored by changing the threshold voltage of the semiconductor due to controlled changes in the number of carriers in the capture area of the electric charge, while the semiconductor memory elements combined sequentially in a matrix of a large amount of local information tire and dictionary tires, and the first and second local data bus connected to the same common data bus through the transistors of the selection.

While the sampling transistors are controlled individually electrodes of the shutter.

Preferably, the device, in which a common information bus overlaps the first and second local data bus.

Moreover, the contact hole connecting the common information bus with a sampling transistor, preferably positioned between the contact holes connecting the first and second local data bus with the transistor of the selection.

In one of the preferred options to perform is placed a semiconductor storage device, the first and second local data bus, connected to the same common data bus through a separate MOSFET selection, have a separate structure of the diffusion layer to the sampling transistor and the contact hole for a common data bus and a separate plot of the diffusion layer passes at least one local information bus.

The semiconductor memory device in accordance with the invention can have auxiliary information bus, made of the same material as the main local information bus, located parallel to it and having essentially equal to it's width, and the auxiliary bus is not used for information storage.

The proposed semiconductor memory device may have an insulating film made on the inner wall of the contact hole bus source or a local data bus, while the semiconductor material is deposited on the side surface of the insulating film that separates the bus source from the local data bus is oxidized insulating film.

In one preferred embodiment of the semiconductor memory device has a semiconductor element is performed on the surface of the semiconductor substrate, and in this device, the contact hole is erecruit the gate electrode or the diffusion layer of the semiconductor element, performed on the semiconductor substrate, and at least the bus source or local information bus.

In addition, in this device, it is expedient to provide an auxiliary data structure, which is not used as a local data bus, but made of the same material as the local information bus, and a structure in which a contact hole dictionary tire is located on the auxiliary structure.

This device can also be an auxiliary structure that is not used as a local data bus, but made of the same material as the local information bus, and a semiconductor film that overlaps by 1 μm or more in the longitudinal direction of the side insulating film supporting structure.

It is expedient in the proposed semiconductor memory device bus from the power source, whereby the voltage supplied to the circuit reading data from the semiconductor memory element, are arranged in parallel dictionary the bus.

It is expedient in the proposed device as a shared data bus, a second layer or top layer is made of metal interconnects.

In yet another preferred embodiment of the proposed pressurizat Rodnikovoe storage device has a circuit reading data from the semiconductor memory element, which is connected to the common data bus through a layer made of metal interconnects below the common information bus.

Preferably, in the proposed device the local information bus connected with the common data bus MOS transistor.

In this device, the first and second local data bus can be connected to the same shared data bus separate MOS transistors samples that have different gate electrodes, with the input of the first and second local information of the tire through the respective gate electrodes are served vzaimodeisvie signals.

In another of the preferred embodiments of a semiconductor storage device has a control device that is designed to perform the first operation of erasing information stored in the semiconductor memory element, the second operation is repeated deletion, remaining in this semiconductor memory element by the incomplete erasing of information during the first erase operation, the third operation record information "0" or "1" in this semiconductor memory element, the fourth re-write information in this semiconductor memory element with incomplete information is recorded during the third operation and the fifth surgery is reading information, stored in the semiconductor memory element, and also has a register for storing information "0" or "1" in the outer part of the semiconductor device, and a device for storage of the list of semiconductor memory elements, in which the erasing of the information has been fully implemented, or list of semiconductor memory elements, in which the erasing data after the first erase operation was not fully met, and the device for storing data stored in the semiconductor memory element during a third write operation, and a device for storage of the list of semiconductor memory elements, in which the erasing of the information has been fully implemented, or list of semiconductor elements memory, in which after the third operation erasing of the information was not fully met, and the device that uses this register for storing data read from the semiconductor memory element during the fifth read operations.

While the above-mentioned semiconductor memory device performs a first write operation in the semiconductor element information "0" or "1", the second operation record information in the semiconductor element with an incomplete recording of information during the first write operation and has a register to store the list of semiconductor elements is s memory in which information was recorded completely, or list of semiconductor memory elements, in which information was recorded not fully after the first write operation, and a device has to re-write the register values in the semiconductor memory elements, in which the information was recorded.

In a preferred embodiment of the device to overwrite the values of the register is performed in the case where information indicating that a complete record of information, is a high-level voltage, consists of one p-channel MOS transistor and one n-channel MOS transistor in which the source of n-channel MOS transistor is connected to a source of high voltage level, the drain of the p-channel MOS transistor is connected to the drain of n-channel MOS transistor, evidence of the full recording information is input to the gate of n-channel MOS transistor, the drain of n-channel MOS transistor is connected to the input of the register storing information indicating that the write data has been fully implemented, and the control signal is input to the gate of the p-channel MOSFET.

In a preferred embodiment of the device to overwrite the values of the register is performed in the case where the information svidetelstvo what about the full recording information is a low level voltage, consists of one n-channel MOS transistor and one p-channel MOS transistor in which the source of the p-channel MOS transistor is connected to a source of low voltage level, the drain of n-channel MOS transistor is connected to the drain of the p-channel MOS transistor, evidence of the full recording information is input to the gate of the p-channel MOS transistor, the drain of the p-channel MOS transistor is connected to the input of the register storing information indicating that the recording of information was performed completely, and the control signal is input to the gate of n-channel MOS transistor.

In accordance with the invention proposes another preferred embodiment of a semiconductor memory device, which is performed on the substrate and consists of a large number of memory cells for storing data by accumulating or discharging electric charges and in which a group of two memory cells located vertically on the substrate, and these memory cells are properly connected to the information tires and dictionary tires, and in which selecting at least one of all memory cells of the address signal is fed to the input of predestinator address decoder local information tire is, moreover, the signal from predestinator address selects one word bus, the signal from the decoder to the local data bus is selected information bus, and when the sample is suitable for use of information the information bus for a group of two vertically arranged memory cells in cases erase selected simultaneously, and reading are selected separately.

In accordance with the invention proposes another preferred execution semiconductor memory device containing a large number of memory elements, each of which contains a region of the source and drain region, channel region, contained in the semiconductor connecting region of origin and region of the drain region for storing electric charges, separated from the channel region by a potential barrier, in which is stored a specified large number of memory elements when changing the conductivity of the specified channel region in accordance with the number of charges, while the semiconductor storage device also contains a large number of local information of tyres and General information bus, and a large number of memory elements includes in itself located one above the other memory elements, these local data bus include the impact located one above the other and separated by an insulating film of a local data bus, moreover, the area of the drain or source of the memory element located in the upper layer of the memory elements that are connected to local data bus, located in the specified upper layer, and the drain region or the source of the memory element located in the lower layer of the memory elements that are connected to local data bus specified lower layer, these local data bus these layers are connected to a common data bus via the MOS transistors of the sample having different length electrodes of the shutter.

In accordance with the invention it is also proposed another preferred execution semiconductor memory device containing blocks of memory cells, each of which consists of a large number of memory cells located at intersections of the intersecting dictionary and tire information tire, and peripheral circuits, the input signals to the vocabulary and information to the tires, and the memory cell consists of a substrate, the first multilayer region located on the substrate, the second multilayer region above the first region, an insulating film located between the first and second regions, a channel region connecting with each other, the first and second areas of the electrode shutter, which creates an electric field in the channel region, and the region C the grip of the electric charge, moreover, the peripheral circuit includes a read amplifier, a register for storing information of the memory elements, the register that holds a flag which indicates the end of recording during the test, and the scheme that after the write operation compares the value read from the memory cell with the value recorded by the box in the end of the record, and rewrites a value that indicates the box, and the storage charge is carried out by changing the threshold voltage of a semiconductor controlled change in the number of charge carriers in the capture area of the electric charge, and at least part of the peripheral circuits are complementary MOS structure consisting of n-channel MOS transistors and p-channel MOSFETs.

The grip area of the electric charge formed preferably fine particles of metal or semiconductor material with an average size of 10 nm.

Channel region in the preferred form of execution of a semiconductor memory element is a thin semiconductor layer, the average thickness of which does not exceed 10 nm.

In accordance with the invention, channel region in the semiconductor memory device performs the function of the capture area of the electric charge.

It is advisable for graynamore the first or the second region to form a substrate of the semiconductor storage device.

The first region or the drain region preferably made of polycrystalline silicon.

It is advisable that the minimum value of the effective width of the channel region in the semiconductor memory element does not exceed 20 nm.

Preferably in the semiconductor memory element block consisting of a large number of memory cells, to perform in a multilayer structure of two or more layers.

Preferably, in the proposed semiconductor memory device, two memory cells of the first region, located one above the other, connected to the same data bus via a corresponding transistor of the selection.

Semiconductor storage device, it is expedient to equip the control circuit that performs three operations, including the first operation consists in applying a voltage of a write to the memory cell, the second operation consists in reading the information stored in the memory cell after performing the first operation and the third operation consists in re-applying to the memory cell voltage recordings in that case, if the second operation is determined that the information in the memory cell was not recorded in full.

Proposed invention is a semiconductor memory device may have a storage schema info is prolonged, which stores are written in the memory cell information (or list of elements to record information "0" or data "1"in the external part of the memory cell, the write operation is performed again, if it is determined that the information stored in the storage schema, after voltage application record does not match the status information of the semiconductor memory element.

In accordance with the invention, the semiconductor storage device by supplying the memory cell of different sizes stresses record has the opportunity in this cell to store two or more bits of information.

Other elements, advantages and features of the present invention is described in more detail below in the description of the different variants of its implementation.

Below the invention is explained with reference to the drawings on which is shown:

figure 1 (a) and 1 (b) is a semiconductor element according to the first variant implementation, while in figure 1(a) shows a view in isometric and figure 1 (b) shows the cross-section,

figure 2 (a) and 2 (b) is a semiconductor element according to the third variant of execution, while in figure 2 (a) shows a view in isometric and figure 2 (b) shows the cross-section,

figure 3(a) and 3 (b) is a semiconductor element according to the fourth variant of execution, while figure 3 (a) is rendered view in isometric, and figure 3 (b) shows the cross-section,

figure 4 (a), 4 (b) and 4 (b) is a semiconductor element according to the fifth variant execution, while in figure 4 (a) shows a view in isometric, figure 4 (b) shows the cross-section including a cross section of the channels, and figure 4 (b) shows the cross-section including a cross section of the source,

figure 5 (a) and 5 (b) is a semiconductor element according to the sixth variant execution, while figure 5 (a) shows a view in isometric in the process of forming the channel, and figure 5 (b) shows a view in isometric after forming the gate,

figure 6 is a semiconductor element according to a seventh variant execution

figure 7 (a) and 7(b) is a semiconductor element according to the eighth variant execution, while figure 7 (a) shows a view in isometric in the process of forming the channel, and figure 7(b) shows a view in isometric after forming the gate,

on Fig (a) is a view in isometric of a semiconductor device according to a ninth variant of execution, and Fig (b) shows a top view,

figure 9 (a) and 9 (b) is a semiconductor element according to the tenth version of the run, while figure 9 (a) shows a view in isometric and figure 9 (b) shows a top view,

figure 10 (a) and 10 (b) are the views from the top, showing the process of manufacturing the semiconductor device according to the eleventh version of the imp is in,

figure 11 (a) and 11 (b) are the views from the top, showing the process of manufacturing the semiconductor device according to the eleventh variant execution

on Fig(a) and 12 (b) are the views from above showing a semiconductor device according to the eleventh variant execution and the process of its manufacturing,

on Fig (a) and 13 (b) is a semiconductor element according to the twelfth variant execution

on Fig - semiconductor element according to the thirteenth variant execution

on Fig (a) and 15 (b) is a semiconductor element according to the second variant implementation, Fig (a) shows a view in isometric, and Fig (b) shows the cross-section,

on Fig (a) and 16 (b) image in ISO semiconductor device according to the first variant of execution in the process of its manufacturing,

on Fig is a cross section showing a contact portion of a semiconductor device according to the eleventh variant execution

on Fig (a) and 18 (b) is a semiconductor storage element, which is a structural element of the semiconductor memory device according to the fourteenth variant execution, Fig (a) shows the view after the formation of the channel, and Fig (b) shows a view in isometric after forming the dictionary tires

on Fig - type over the semiconductor storage element, which is a structural element of the semiconductor memory device according to the fourteenth variant execution

on Fig is a drawing illustrating the principle of operation of the semiconductor storage element, which is a structural element of the semiconductor device according to the fourteenth variant execution

on Fig is a top view of a flat semiconductor storage element, which is a structural element of the semiconductor memory device according to the fourteenth variant execution state before the formation of the storage element,

on Fig is a top view of a flat semiconductor storage element, which is a structural element of the semiconductor memory device according to the fourteenth variant execution, after formation of the information tires

on Fig is a top view of a flat semiconductor storage element, which is a structural element of the semiconductor memory device according to the fourteenth variant execution, after applying mesh resist for forming channels,

on Fig is a top view of a flat semiconductor storage element, which is a structural element of the semiconductor memory condition the device according to the fourteenth variant execution after forming the dictionary tires

on Fig is a top view of a flat semiconductor storage element, which is a structural element of the semiconductor memory device according to the fourteenth variant execution, after forming contact holes,

on Fig is a top view of a flat semiconductor storage element, which is a structural element of the semiconductor memory device according to the fourteenth variant execution, after forming the first layer of conducting wires,

on Fig is a top view of a flat semiconductor storage element, which is a structural element of the semiconductor memory device according to the fourteenth variant execution, after forming the second layer of conducting wires,

on Fig is a top view of a flat semiconductor storage element, which is a structural element of the semiconductor memory device according to the fourteenth variant execution, after forming contact holes, in particular, shows the network of contacts dictionary tire, located at the end of the matrix of storage elements,

on Fig - cross-section of the contact structure of the MOSFET of the sample flat on provodnikov storage element, which is a structural element of the semiconductor memory device according to the fourteenth variant execution

on Fig (a) and 30 (b) image of a semiconductor storage element, which is a structural element of the semiconductor memory device according to the fifteenth variant execution, Fig (a) shows a top view after the formation of the channels, and Fig (b) shows a top view after the formation of the dictionary tires

on Fig (a) and 31 (b) image of the other in the form of a variant of the flat semiconductor storage element, which is a structural element of the semiconductor memory device according to the fifteenth variant execution, Fig (a) shows a top view of the semiconductor storage element after the formation of the channels, and Fig (b) shows a view in isometric after forming the dictionary tires

on Fig is a top view of a flat semiconductor storage element, which is a structural element of the semiconductor memory device according to the fifteenth variant execution, after forming contact holes,

on Fig image in ISO matrix of cells used in the device, made according to the options from the sixteenth through the twenty who ü second,

on Fig - drawing, which illustrates the sequence of operations of read, erase and write semiconductor memory device according to the sixteenth option

on Fig - drawing, which illustrates the sequence of operations of read, erase and write semiconductor memory device according to the seventeenth variant execution

on Fig is a block diagram of a semiconductor memory device according to the seventeenth variant execution

on Fig - drawing, which illustrates the sequence of operations of read, erase and write semiconductor memory device according to the eighteenth variant execution

on Fig is a block diagram of a semiconductor memory device according to the nineteenth variant execution

on Fig - drawing, which shows the sequence of operation of the semiconductor memory device according to the nineteenth variant execution

on Fig is a block diagram of a semiconductor memory device according to the twentieth variant execution

on Fig - drawing, which shows the sequence of operation of the semiconductor memory device according to the twentieth variant execution

on Fig is a block diagram of a semiconductor remember what its device according to the twenty-first option run

on Fig is a graph which shows the time variation of the current in the data bus of the memory element according to the twenty-first option run

on Fig - drawing, which shows the sequence of update operations when operating the semiconductor memory device according to the twenty-second version execution

on Fig - figure, which is conventionally depicted memory element with a floating gate,

on Fig - drawing, which shows a diagram of a semiconductor memory device according to the twenty third variant of execution, in which reading and writing are performed in a matrix of memory cells multiplex method,

on Fig - drawing, which shows the voltage applied to items made on the twenty-third variant of the memory cell during a read operation, the erase / write

on Fig - timing diagram for a read operation in the semiconductor storage device according to the twenty third variant execution

on Fig - time chart of the operations of erasing and writing in the semiconductor memory device according to the twenty third variant execution

on Fig - arrangement of memory elements at all points of intersection of the dictionary and tire information tire in the device from the collapsed structure information shall include tires, performed according to the twenty-fourth variant,

on Fig - drawing, which shows a schematic of the I/o and control circuitry in the device, made according to the twenty-fifth variant,

on Fig is a block diagram of a semiconductor memory device according to the twenty-sixth variant execution and

on Fig is a block diagram of a semiconductor memory device according to the twenty-seventh variant of execution.

The first option

Below is a detailed description of specific embodiments of a semiconductor storage element, semiconductor memory device and method of management with reference to the accompanying drawings. For simplicity, the description is considered only a part of the semiconductor memory device, although in practice it contains and other appropriate connections and peripheral circuits.

Figure 1 (a) and 1 (b) shows the structure of a semiconductor memory element made according to the first embodiment. Figure 1 (a) this item depicted in isometric and figure 1 (b) shows its cross-section. The source 76 and the drain 77 are respectively region made of polycrystalline silicon of n-type high impurity concentration. Between the regions of the source 76 and the drain 77 is made of insulating film 82 of SiO2. To Bo the OIC surface of this insulating film 82 made of polycrystalline silicon p-type made the channel 78 with a thickness of 20 nm and a width of 150 nm. Region 79 capture the electric charge is made of polycrystalline silicon and isolated thin insulating film 87. The channel 78 and the region 79 of the capture of the electric charge associated with the electrode 80 of the gate through an insulating film 81 of SiO2. The distance between the electrode 80 of the shutter and the region 79 capture of electric charge equal to 30 nm.

Compared with discussed below device made according to the third variant, in which the channel and the grip area of the electric charge is made at the same time, in the first embodiment of the invention, the channel 78 and the region 79 capture of electric charge are formed separately, which allows you to create more options and creates great opportunities in their manufacture. A special advantage of this scheme is that it allows you to arbitrarily set the height and width of the potential barrier, choosing the appropriate material and thickness of the layer insulating film 87 between region 79 of the capture of the electric charge and the channel 78. In this embodiment of the invention field of the potential barrier is lower than the source and drain, but it can also be performed from the opposite side. In addition, in this embodiment of the invention, as in the next, as the charge carriers are electrons, however, as the charge carriers can also use isolates positively charged holes.

In the semiconductor memory element according to this variant of the invention, the source 76 and the drain 77 vertically overlap each other, which reduces the required surface area. The size of the surface area of this element is reduced and due to the vertical arrangement of the channel region (channel) 78. In this implementation element, the memory capacity can be increased by serial arrangement of memory elements. In all subsequent embodiments, it is assumed that the storage elements are placed in this way.

Working memory elements made according to this variant, as follows. The voltage potential on the electrode 80 of the shutter changes in the operations of erasing and writing. Between the inlet 76 and the outlet 77 is created some tension, and when the voltage applied to the gate, electrons pass through a thin layer of polycrystalline silicon of the channel 78 and starts the flow of electric current. When a large voltage on the gate potential difference between the region 79 of the capture of the electric charge and the channel region 78 is large, and due to a tunneling effect or thermal excitation of the electrons cross the potential barrier insulating film 87 and fall in the region of 79 capture of electric charge. In the result, the threshold voltage increases, and the amount is and the electric current at the same voltage on the gate is reduced. Reading of information is carried out by measuring the quantity of electric current. Erasing of information is conducted by application to the gate of the other in the direction of tension.

Below with reference to Fig (a) and 16 (b) describes the process of manufacture of the device made according to this variant. After oxidation of the surface of the substrate 86 p-type and forming a layer 84 of SiO2it is applied sequentially a layer of SiO2the layer of polycrystalline silicon of n-type and a layer of SiO2. Then a layer of protective photoresist and is the simultaneous etching of all four layers with formation region 76 of the source region 77 runoff and shown in Fig (a) layers 82, 83 of SiO2. When simultaneous (in the package) the formation of all layers in the multilayer structure item no increase its size during lithographic processing does not occur. Then, after forming a layer of amorphous Si with a thickness of 20 nm in the heat treatment process is carried out crystallization. After defending the photoresist from crystalline silicon to perform the etching, forming the channel 78 (Fig (b))representing the linear region, which connects the drain 77 and the source 76. During etching in the presence of the coating layer 83 of SiO2region 77 of runoff to prevent excessive removal of material in the field 77 runoff. After deposition of oncolo layer 87 SiO 2put polycrystalline silicon region 79 of electron capture and carry out etching. Then, after forming a layer 81 of SiO2put a layer of polycrystalline silicon of n-type and after protection of the photoresist and etching to form the electrode 80 of the shutter.

The second option

On Fig (a) and 15 (b) shows the structure of a memory element made according to the second variant. The source 1 and drain 2 represent a region of polycrystalline silicon of n-type high impurity concentration. Between the source 1 and drain 2 is made of insulating film 7 of SiO2. On the side of the insulating film 7 of SiO2made a 3 channel width of 20 nm and a thickness of 10 nm of undoped polycrystalline silicon. Area 4 capture electric charge consists of a large number of polycrystalline silicon particles with an average size of 6 nm and isolated by an insulating film. Channel 3 and area 4 capture the electric charge is connected to the gate electrode 4 through an insulating film 6 of SiO2. The distance between the gate electrode and the region 4 capture of electric charge equal to 30 nm. The entire element is located on an insulating film 8 of SiO2. The location of the element on an insulating film made in a similar way and discussed below in other embodiments of the invention (unless specified otherwise). the anal 3 and region 4 of the capture of the electric charge in this embodiment is made separately, however, the known and can be used and the method of simultaneous formation of the channel 3 and the capture area of the electric charge. The separate formation of the channel and the capture area are provided in all subsequent versions of the invention. The layer 18 of SiO2whose width equals the width of the drain 2 and the source 1, is located above the drain 2 and prevents excessive removal of material from the area of the flow 2 is similar layer of SiO2in the first embodiment of the invention.

Below we discuss some aspects related to the operation of the device made according to this variant of the invention, and different from the characteristics of memory elements, executed in the first embodiment. In this embodiment of the invention after the capture of charge carriers due to the narrowness of the channel 3 distributed capacitance between gate electrode 5 and channel 3 becomes small, and therefore from region 4 capture, you can read a small accumulated therein electric charges. In this embodiment of the invention when changing the threshold voltage of approximately one volt can be considered as three saved (or accumulated) electric charge. Increasing the channel width and with a larger number of silicon crystal particles in the capture area of the electric charge, the number of stored electric charges can be increased and to get a result, it is possible to change the threshold voltage. Increased bandwidth allows to increase the flow through it of an electric current and to simplify the process of lithography. The size of the capture area of the electric charge is limited to 10 nm, and the total peripheral capacity does not exceed 3F. At room temperature, even taking into account thermal effects, it is always possible to determine the sustainable number of media held in the capture area of the electric charge. Therefore, in such devices should not be any injection in the capture area of excessive number of charge carriers or extraction from it is stored (accumulated) of charge carriers. Erasing of information is conducted by changing the gate voltage.

A third option

Figure 2 (a) and 2 (b) shows the third option proposed in the invention device. This device differs from the device according to the second variant only by the fact that the channel and the grip area 11 of the electric charge integrated in one element, and that the channel 11 on both sides of the source 9 and drain 10. As a material for the channel region 11 of the capture of electric charge using undoped polycrystalline silicon in the form of a thin layer with an average thickness of approximately 3 nm. This device, in which large fluctuations in potential occur in a thin layer of polycrystalline cu is mnia with an average thickness of less than 5 nm and in which the channel and the grip area of the electric charge are formed in a thin film (11), has very small dimensions and, being manufactured in a simple way, the most suitable for operation at room temperature. The size of the crystalline particles in the device is equal to approximately 3 nm, which allows to maintain the size in the transverse direction in the range of about 10 nm with the same size of the respective areas of the capture of the electric charge.

A distinctive feature of this structure is that, by forming the channel region 11 of the capture of the electric charge on both sides of the source 9 and drain 10, at a certain width of the electrode 12 of the gate width of the channel can almost be doubled, thus increasing the current proceeding through it. Usually the increase of the width of the channel region and the magnitude of electric current requires an increase in the surface area, however, with such the structure of the proposed device no increase in size is not required. In structures with joint channel and the capture area of the electric charge having problems, because a simple increase in channel width due to the capture of carriers possible range of variation of the threshold voltage decreases. In the proposed device this problem, however, does not occur as existing in a large number of channels are isolated from each other.

The fourth option

The fourth option pre is proposed in the invention device shown in figure 3(a) and 3 (b).

This device differs from the device according to the third variant, there are two sinks and a three-layer structure consisting of the flow (1) 13, source 14 and drain (2) 15. In this embodiment, device memory capacity can be doubled compared with the first option, without increasing the surface area. In addition to sharing the source 14, this device differs in that the data storage is the source 14 and drain (1) 13 and the channel region 16 of the capture of the electric charge, which is connected with the specified drain and source. In addition, storage of data, it is also the source 14, drain (2) 15 and the channel region 88 of the capture of the electric charge, which is connected with the specified drain and source. Two channels and two areas 16, 88 capture the electric charge generated at the same time (deposition). Due to the different relative position to the source and drain, they perform different functions. Although they share the same electrode 17 of the shutter, only one side of the element capable of changing the voltage on the drain (1) 13 or drain (2) 15 to perform a write operation and erase. In addition, since the source 14 and drain (1) 13 and the drain (2) 15 can be performed all at the same time and also at the same time can be performed and the channel region 16, 88 capture electric charge, such a device has a certain mainly what westom, consisting of a small number of operations required for its manufacture. In this embodiment of the invention, the channel and the grip area of the electric charge combined with each other, although they can be performed separately from each other.

The fifth option

The fifth option proposed in the invention device shown in figure 4(a), 4 (b) and 4(b).

This device differs from the device options first to fourth by the fact that the source and the drain in it is made in a multilayer structure, and the fact that the gate electrode is also made in a multilayer structure. On the outer side of the multilayer electrode (1) 19 gate electrode (2) 20 shutter made the source 21 and drain 22, which are isolated by an insulating film 26 of SiO2. Non-alloy thin-film polycrystalline silicon 23 with the thickness of about 3 nm connects the source 21 and drain 22 on the side surface insulating film of SiO2. The function of the channel and the capture area of the electric charge runs thin film layer 23. Polycrystalline silicon thin film 23 contains a very thin round crystal particles that define a high threshold voltage of the element.

When voltage is applied to the gate only a section of a thin film in the region of the gate electrode can conduct an electric current and, although a thin film 24 on the Auron electrode 1 (19) shutter and a thin film 25 on the side of the electrode 2 (20) shutter isolated during etching, these film forming device corresponding channels and the capture area of the electric charge. This ensures the storage element of at least two bits of information in the item. The gate electrodes in this device is made in two layers, although the actual number of layers can be large. In this embodiment, the structure of the sources and drains made in the form of layers as in the third embodiment, it should, however, be noted that the use of the structure, in which the number of layers is more than four, difficult, because when you are sharing drains the device usually works poorly. The structure in this embodiment of the invention has a particular advantage in the possibility of increasing the memory capacity is proportional to the number of added layers of electrodes of the gates.

The sixth option

The sixth embodiment of the proposed invention in the device shown in figure 5 (a) and 5 (b).

Made by this variant of the invention, the memory element is for storing at least two bits of information. The element structure in this embodiment is essentially the same as the structure of the element according to the third variant of the invention, except that it consists of two parts, however, made it in a slightly different way.

The process izgotovlenie of the memory element are discussed below. After oxidation of the surface of the substrate p-type on it consistently put a layer of polycrystalline silicon of n-type, the layer of SiO2the layer of polycrystalline silicon of n-type, and then perform the protection of the photoresist and forming source 27 and drain 28 and insulating their layer 32 of SiO2. Then put a deposition of a thin layer of Si3N4thickness of 15 nm and a layer 32 of SiO2. After applying the photoresist to form openings of a mask that includes a stepped section, the lateral edge of the drain 27 (figure 5 (a)), perform the etching of the layer of SiO2and a layer of Si3N4. This exposes the side surface of the layer (30) of Si3N4. Then, on this layer Si3N4(30) put a layer of amorphous Si to a thickness of 3 nm. Compared with the application of the lower layer of SiO2the process of applying the lower layer of Si3N4since the gas supply to the beginning of the process, the actual clutch silicon with the surface of the substrate has more time, and therefore, in this case, the surface layer of SiO2amorphous Si (a-Si) are not deposited. Therefore, a thin layer of a-Si with a width of about 15 nm can be applied to the surface of the layer 30 of Si3N4layer connecting the source 27 and the drain 28. Then when heat-treated a-Si crystallization occurs, and the channel and the grip area electric ZAR is Yes integrated into one element. After deposition (formation) layer 33 of SiO2put polycrystalline silicon layer is n-type and by performing etching using a mask of photoresist, to form the electrode (1) 29 gate electrode (2) 34 shutter (figure 5 (b)).

In this embodiment of the invention the storage of information can be performed using each of the two electrodes 29, 34 gates, allowing you to store at least two bits. Using multivalued storage, this item can store more bits of information. A distinctive feature of this device is its good handling and the possibility of the formation of very small tires. Apart from the fact that this element is less in comparison with the conventional semiconductor elements heterogeneity, it is possible to provide a large change in the threshold voltage with a small number of trapped electrons. In the shown device, a hole is made on the stepped section of one of the parties to the lateral edge of the drain 29, however, such openings can be performed on both sides, while managing two channels and areas of capture of an electric charge the same electrodes. This structure allows you to create a memory element with a large electric current. In addition, in this embodiment, the source 27 and drain 28 is made in the form of two placed one on the other the layers, however, it is possible, as in the fourth variant embodiment of the device with a three-layer structure of layers of flow 1, the source and drain 2 and higher density of information storage.

The seventh option

Below is the seventh embodiment of the proposed invention in the device, which is shown in Fig.6.

This device differs from the device according to the 6th option in two ways: one of which is that the channel and the grip area of the electric charge is made separately, and the other is that both channels are controlled by one and the same electrode 35 of the shutter. The advantage of separate formation of the channel and the capture area of the electric charge are discussed in detail in the description of the first variant of the invention. A distinctive feature of this variant of the invention is a simpler method of manufacturing electrode 35 of the shutter using a structure in which the electrode 35 of the shutter controls both channels and is made in the same hole. The difference of this method of manufacture as compared with the sixth option is that a thin layer of SiO2applied immediately after formation of the channel, and the formation of a capture area of electric charge is performed using the silicon crystal particles.

The eighth option

Below is the eighth option you is filling up proposed in the invention device, which is shown in Fig.7 (a) and 7(b).

In this embodiment of the invention the process of manufacturing and mutual arrangement of the channel and the capture area of the electric charge is different from the seventh option. The following are the main differences of the manufacturing process of this device from the process of manufacturing the device according to the sixth variant of the invention. After formation of the source 36 and drain 37 they applied a thin layer 34 of Si3N4thickness of 15 nm. Then a layer 40 of SiO2thickness of 5 nm and, in contrast to the sixth variant, a layer 39 of Si3N4thickness of 10 nm. Then on the layer 41 SiO2put the protection of the photoresist for forming the mask holes located on the stepped section at the end of the field drain 37, and after etching perform operations similar to the sixth variant of the invention. The thickness of the applied layer of a-Si in this embodiment, equal to 5 nm. In the process of deposition of a-Si on the side of the channel region, which connects the drain 37 and the source 36 on the side surface of the layer 38 of Si3N4form another layer 39 of Si3N4the grip area of the electric charge. This structure is distinguished by good control of the distance between the channel and the capture area of the electric charge.

The ninth option

Below is the ninth version of the proposed in the present invention and the device, which is shown in Fig (a) and 8 (b).

In this embodiment of the invention uses four of the memory element in the first embodiment of the invention, which form a matrix of memory elements, two of these elements are connected to each other sources and sinks, and the other two electrodes of the gates. When managing columns and rows are two drain 42, 43 for information tires and two gates 46, 47 for dictionary tires. In such a device a number of elements that share the sources and sinks, can be increased or left unchanged, and the number of items managed by the information tire can be increased. In addition, in this device the number of elements that share the gate electrodes may be either increased or left unchanged, and the number of items managed dictionary tires increased. The increase in the number of elements gives the same results when applied to other variants of the invention. To reduce the resistance of the data bus can be used a method of applying a stamping on the reverse side of the substrate corresponding metal (for example, Al, W, TiN, WSi2, MoSi, TiSi, and so on). This method is the reverse stamping may be used in the manufacture proposed in the invention device. The same method can be used to reduce the resistance with overnig tires as this, and in other embodiments of the invention.

The tenth version

Below is the tenth version of the proposed in the invention device, which is shown in Fig.9 (a) and 9 (b).

In this embodiment of the invention four of the memory element according to the fourth variant of the invention comprise a matrix of storage elements, in which two elements together form the source, drain 1 and drain 2, and the other two electrodes of the gates. For the formation of sinks and shutter, as well as to make information tires and dictionary of tires you can use polycrystalline silicon. In this embodiment of the invention, control is performed four informational tires (1-4) 48-51, as well as dictionary bus (1) 54 and dictionary bus (2) 55 that provides storage for eight or more bits of information. A data bus with a 1-St to 4-th marked on the drawings positions 48 to 51, and the same symbols are used in subsequent versions of the invention. In this embodiment of the invention the bottom layer of three-layer structure of polycrystalline silicon of n-type contains information bus (1) 48 and 3 (50). The next layer forms tires origins (1) 52 (2) 53, and the top layer forms an information bus (2) 49 (4) 51.

The drawing shows also the contact elements of the device according to the considered variant of execution. The following describes the process f is Mirovaya these contacts. First, for the formation information of the tire (1) 48 and information of the tire (3) 50 on a substrate applied a layer of polycrystalline silicon of n-type and a layer of SiO2and then for the formation of the tire (1) 52 source and tires (2) 53 source put a layer of polycrystalline silicon of n-type. Then, the polycrystalline silicon layer is n-type, forming tires origins (1) 52 (2) 53, cut the first hole 56. Then, after forming a polycrystalline silicon layer of n-type for the information of the tire (2) 49 (4) 51 it cut the second hole 57. Then after applying a layer of SiO2and digital tire and tire source process areas (for example, 58, 59, 60)connecting the contacts in each contact section. Such element information bus 2 in region 60 is formed by the top layer of polycrystalline silicon, and in the area of 59, on which the polycrystalline silicon is cut, the top layer is a polycrystalline silicon layer bus source. In addition, due to the lack in the area 58 polycrystalline silicon data bus 2 and the polycrystalline silicon tyres source of the upper layer is a polycrystalline silicon data bus 1. In this embodiment, for forming the contact holes in each layer do not need to perform a separate operation. This process formed the Oia contacts can also be used for other multilayer structures (several layers) and in particular, for performing the gate electrodes in the fifth embodiment of the invention. In this and in other embodiments it is possible, obviously, to use other methods of forming the contacts.

The eleventh version

Below is the eleventh variant of the invention, which is illustrated in figure 10 (a)-12 (b) and 17.

In this embodiment, eight memory elements made according to the fourth variant of the invention, connected in a matrix 4×2. The source, drain 1 and drain 2 is made common to all four elements, and the gate electrodes are made common to two elements. The gates and drains are made of polycrystalline silicon and, as in the tenth embodiment, are used as information of the tire and dictionary tires. The bottom layer in the three-layer structure consisting of a data bus 1, bus source bus 2 flow, which are co-etching, is formed of polycrystalline silicon. In this embodiment also has a transistor element for sampling a data bus. The cell represents the portion 61 of the scheme, which is highlighted by the dotted line. The control in this embodiment is provided by four information tire 62, four transistor keys 63 and dictionary bus 64 and allows you to store this matrix information volume 16 bits or more. The size of the area of contact and the peripheral elements of the integration of the existing schemes in this embodiment must be less due to the smaller cell size. In particular, when forming the source, drain and gate in this embodiment, in a multilayer structure is necessary to consider that the large size of the contacts and the peripheral circuits will not allow you to create a multilayer structure.

Below is the structure of the proposed device in the process of its manufacture. First, on a silicon substrate transistors of the sample (figure 10 (a)). Positions 66, 67 and 68 are marked diffusion layers. At the same time formed the other peripheral circuit elements, of which the drawing shows only the transistors that select data bus. After forming the electrode 63 of the shutter for sampling transistors and memory cells cause the protective oxide layer 69, which form the memory cell. For the cell formation is used the same way as in the fourth embodiment of the invention, and further, we consider only the differences. Before applying the lower layer of polycrystalline silicon of n-type, which forms a data bus 1, is protected by the photoresist, the oxide layer and etching in the region of 70 diffusion layer 66, which are formed of the transistors of the sample (figure 10 (b)).

Further, the manufacturing process of this device is shown in 11 (a) and 11 (b). After the formation on the substrate of the lower layer of polycrystalline silicon of n-type, the image of the corresponding data bus 1, put a protective layer of photoresist, is etched, and put a layer of polycrystalline silicon of n-type for forming tire 71 source, as shown in figure 11 (a). After deposition of the polycrystalline silicon layer is n-type for forming tire source put a layer of SiO2and a layer of polycrystalline silicon of n-type for forming a data bus (2) 49, then carry out the etching of the polycrystalline silicon layer, forming a data bus (2) 49 in the areas of the holes 72, which are shown in the drawing, bringing together the etching of information tires and tire source. In a joint etching tire source and information of the tire on the outer side of the area indicated by the position 71, polycrystalline silicon on the data bus (1) 52. Polycrystalline silicon is also removed on the data bus (2) 49 in the area marked on the drawing position 72.

After the simultaneous formation of the source and the information of the tire described above, the information bus (1) is directly connected with the diffusion layer 66 of the transistor of sample without metal interconnects, which eliminates the need for special formation of interconnects and contacts and makes it easy to make small structure. Separate the s bus source are interconnected polycrystalline silicon, which is removed from the field (65) data bus 2. So on this site it is possible not to provide interconnects, thereby creating a structure with a small surface area.

A further stage of the manufacturing process shown in Fig (a) and 12 (b). After the formation of the oxidized layer of polycrystalline silicon and complete dictionary of the tyres perform the alignment surface and the formation therein of the oxidized layer. On this layer after forming the holes for the pins are made of metal interconnect 75, as shown in Fig (a). Thus, information bus (2) 73 and the diffusion layer 68 for sampling transistor are connected to each other.

On Fig shows the cross-section plane a-b in Fig (a). For simplicity, Fig (a) and 12 (b) metal interconnect transistor 63 sampling speed and vocabulary bus 64 is not shown. In the diffusion layer for the transistor 67 sample made contact hole and at the same time made the second metal interconnect 75, which is shown on the drawing. As a result, when the application voltage to the two electrodes of the gate transistors of the sample metal data line 62 is electrically connected with either data bus (1)or data bus (2).

For simplicity, the structure of this variant of the invention shown in the drawing is reduced in the ohms scale, because in the real storage device has a lot more information and vocabulary tires. Usually the device has about 1000 information tires and tire origins and vocabulary tyres is about 16 and all of the information bus with the sampling transistors are the same as in this embodiment of the invention. For convenience, such a device is called a block. A large number of blocks with dictionary tires, which are arranged vertically in an alternating form the memory device. Located in several layers of the information bus (1, 2) can be controlled from a single data bus, located on the external side of the block, using transistors of the sample. Available in a block in a large number of metal data bus can be connected to each other. In this case, the number of metal the information of the tire is equal to the number information of tires of the same block. The characteristic structure of the device in this embodiment of the invention, which is divided into separate blocks, is that the information bus of the polycrystalline silicon can be made short and will have a small resistance.

Twelfth variant

The structure of the device, made the twelfth version, shown in Fig (a) and 13 (b).

This variant of the invention is distinguished by the I from the fifth option only as tire 74 source instead of polycrystalline silicon using diffusion layer substrate. Bus source that uses the surface of the substrate, easily forks for each cell. This variant of the invention has a low resistance bus 74 source due to the lack of a single layer of polycrystalline silicon, which simplifies the whole process of manufacture. It should be noted that this structure, with bus source, made in the form of a diffused layer of the substrate, can be used even in the element according to the first variant implementation of the invention.

Thirteenth option

The structure of the device according to the thirteenth variant shown in Fig.

In this embodiment, a structure consists of two overlapping layers and matrix of memory elements, executed in the first embodiment. On Fig shows a cross-section of the data bus. Memory element and proposed in the invention, the storage device is performed on the insulating film in such a way that allow you to implement a multi-layered structure or a structure with insulated from each other by layers other than the memory elements formed on the substrate surface. Another difference of this structure is that it allows to achieve a high degree of integration. In addition, when using a multi-stakeholder who oinoi structure of the channels of the memory element and proposed in the invention of the storage device are vertical, and unlike the flat structure of the upper and lower layers of such a multilayer structure is less susceptible to the adverse effects generated by the electrodes of the closures of the cells.

Fourteenth option

The structure of the device according to the fourteenth variant shown in Fig(a)to 24.

On Fig (a) and 18 (b) shows a General view of the matrix of memory cells comprising a storage device, executed by this variant. On Fig (a) shows the structure after forming the channel, and Fig (b) shows the structure after forming the dictionary tires. Information bus (1) A1, bus (A3) of the source and information bus A2 (2) made of polycrystalline silicon of n-type high concentration impurities and separated by an insulating film A4, A5 of SiO2. Conductive channels A6, A7 thickness of 2.5 nm and a width of 50 nm made in the undoped polycrystalline silicon adjacent to these insulating films A4, A5 of SiO2. Dictionary bus A9 performed on the upper and on the lower surface of the layer of polycrystalline silicon and isolated from the gate by A8 film thickness of 25 nm. The drawing shows a layer structure with two data buses and the basic structure of a matrix with two dictionary tires, even though the memory cell may have a much larger number of information tires and vocabulary tires. I is a side memory consists of two layers, the top and bottom, each of which has four points of intersection of the tire, and is capable of storing at least eight bits of information even without the use of multivalued data store.

In the top view of this structure is shown in Fig. Information bus (1) A1, bus A3 source and information bus (2) A3 made in the form of multi-layered vertical structure (a10)that allows you to limit the surface area of the device. The entire structure A11 occupies an area equal to 4F2. In this structure contains two cells, and therefore the surface area of one cell is equal 2F2.

The work of this memory element is illustrated in Fig. Fluctuations (rise and fall) of the potential within an extremely thin layer of polysilicon such that within this thin layer are contiguous region A12 low capacity for conducting an electric current, and an isolated area of low potential, which forms a region A13 capture of electric charge. The size of the crystalline particles of this layer is limited by the layer thickness of approximately 2.5 nm, and the horizontal length does not exceed 10 nm. The size of the charge carriers in the area A13 capture of electric charge is measured in the same units. This structure is most suitable for a small element times the EPA, able to work at room temperature and easy to manufacture. It should be emphasized that the grip area of the electric charge and the channel for the passage of electric current can be, obviously, are formed separately from each other.

In the present embodiment, if the size of the particles in the capture area of the electric charge does not exceed the maximum of 10 nm, the effect of the electrostatic repulsion of charges can be obtained even at room temperature. Operations of writing and erasing are carried out by changing the electrical potential on the vocabulary of the bus A9. Between the data bus (1) A1 and bus A3 source creates a certain tension, and when the application voltage to the dictionary the bus, a thin polycrystalline silicon film channel A6 produce electrons and starts the flow of electric current. At a higher voltage on the gate potential difference between the channel A12 flow of electric current and the area A13 capture the electric charge becomes large, and the electrons traverse an area of high potential barrier by the tunnel effect or thermal excitation and fall within the scope A13 capture of electric charge. The result is a shift of the threshold voltage towards larger values, and the magnitude of the electric current becomes small is even when the same voltage on the gate. Reading of information is performed by measuring the quantity of electric current. Erasing is carried out by changing the sign of the gate voltage.

Below is the structure of the flat semiconductor storage element, which is the main block of the semiconductor memory device of large capacity, containing the matrix of the semiconductor memory of large capacity, consisting of individual memory cells.

Scheme flat semiconductor memory element shown in Fig, 22, 23, 24, 25, 26 and 27. On these drawings shows the various stages of the manufacturing process of this element in the same section.

The above-described memory cell according to its configuration suitable for use as the matrix element is large in size. Since, however, the memory cell has a long data bus of polycrystalline silicon, its resistance becomes too large. Therefore, for large size devices contacts their interconnections must be made of a metal material with low electric resistance. Compact module for this structure will be referred to as a flat memory element. In this embodiment of the invention to create a flat memory element 128 cells must have 8 rows of information tires and with overnig tires with two cells in each of the 64 points of their intersection.

In addition, in order to identify polycrystalline silicon data bus 1 and 2, designed to perform internal interconnects flat memory element, called local information tire information the tires with low resistance, designed to meet the interconnections between the planar memory elements, called General information tires. Because two tires, including information bus 1 and the bus 2, overlap each other, the MOS transistor samples the upper and lower flat memory elements performed on the surface of the substrate. This arrangement of transistors solves the problems associated with the placement of elements with a certain step, and allows you to perform common information bus outside flat of the memory element in the form of one of the conductor. Because the step between the transistors of the sample must be greater than the step information of the tire, a sampling transistor, whereas the presence of the insulating region, can work for related information tire split on the top and bottom of the flat memory element.

Below with reference to Fig-27 in detail the manufacturing process of the device made according to this variant. Area A22, which is highlighted by the dotted line forms a planar semiconductor module of the storage device. Initially, n is the surface of the substrate p-type to form an n-type transistor. Then form the area A15 - gate electrodes that intersect the active region A16, forming the matrix adjacent to each other of the memory elements. At the same time on the outside of the matrix of memory cells form a complementary MOS structure. The MOS transistors are in the form of sandwich pocket structure, providing the opportunity to work in the desired voltage range. Such MOS transistors are at least two different length valves, since the transistors of the amplifiers of the read transistors of the decoders and the transistor control circuit dictionary of tyres with high permissible voltages have different voltage electrical breakdown. In this embodiment, do not use CLP-substrate (structure type "silicon on insulator"); it should be noted that the use of thin-film KND-substrate eliminates the need for a memory cell in this embodiment of the invention in the form of sandwich pocket structure. Then, after forming a layer of SiO2perform etching using a mask of resist, exposing the area A14 diffusion layer of the MOS transistor of the sample. Then put a layer of polycrystalline silicon of n-type thickness of 50 nm and perform the etching of the layer of SiO2using as a mask the resist shows the CSOs on Fig template A33. This method allows a direct connection between the local information buses A1 and the diffusion layer of the MOS-transistors of the sample without forming special contacts for local data bus A1 (1). Then put a layer of SiO2(thickness 100 nm), a layer of polycrystalline silicon of n-type (thickness 50 nm), a layer of SiO2(thickness 100 nm), a layer of polycrystalline silicon of n-type (thickness 50 nm) and a layer of SiO2(thickness 30 nm), and then perform the etching of the layer of SiO2using it as a mask of the resist for six formed before the layers shown in Fig multilayer structure A17, consisting of bus A3 source, the local data bus (1) A1 and a local data bus (2) A2.

The simultaneous formation of all these layers simplifies the process of lithography in comparison with the manufacture of the memory element in the form of a two-layer structure. In addition, in the proposed version of the network information tire A18 is performed between the planar memory elements. When the lithographic method of forming information of tyres such a scheme makes it easy to determine the optimal conditions for the implementation of structures with the same light exposure (creating a schema using e-beam). Positioning adjacent structures on both sides adjacent the information of the tire, the local bus can be performed with the same static capacitance that adjacent tires, greatly increasing the stability of the memory device. Then after forming the layer of a-Si (amorphous silicon) to a thickness of 2.5 nm in thermal treatment process is performed crystallization. After crystallization put a layer of SiO2thickness of 15 nm and then forming the strip A19 of the resist width of 0.1 μm, placing them at right angles to the data bus, as shown in Fig.

After forming resistol mask A19 perform its etching. This forms a thin splint of SiO2, which runs perpendicular to the substrate layer side A6 of SiO2between the local data bus (1) A1 and bus A3 source, and the SiO2- layer A7 between the local data bus (2) A2 and bus A3 source. At the same time form the auxiliary circuit A20, prevent collapse of the tire of the small width of the resist. Then a layer of SiO2cut parallel to the substrate dry anisotropic etching. This method of etching prevents the connection of adjacent local information tire each other through polycrystalline silicon. Then a thin layer of polycrystalline silicon are oxidized in a plasma environment O2. With the purpose of the oxidation layer is not more than 10 nm, a thin layer of policy Starichenko silicon, which is located below the pre-formed small bus width of SiO2not oxidize, forming thereby a very clear scheme of an extremely thin layer of polycrystalline silicon. This method of dry etching is most suitable for a low tire width for the following reasons. First, by using dry etching and oxidation by wet etching of the resist can be carried out very clear and fine structure. During the preliminary studies it was found that the change in threshold voltage can be obtained both before and after the write operation when using an extremely thin layer of polycrystalline silicon with a very narrow bus channel width to length ratio equal to at least 2. In this embodiment of the invention, when the thickness of the layer of SiO2between bus A3 source and the local data bus A1 equal to 100 nm, it is necessary that the width of the channel was approximately 0.5 micron. In the experimental sample was used, the resist layer with a width of 0.1 μm, and after completion of the wet etching was formed narrow bus channel of SiO2width of 0.07 μm. With additional oxidation of the side surfaces after oxidation was formed extremely thin layer of polycrystalline silicon with a narrow bus width of 0.05 μm. The WTO is s, when the depth of the plasma oxidation of O2of approximately 10 nm, there is no possibility of an excessive increase in the size of the bus channel after its formation. After execution of the channel, and after the formation of a thin layer A8 of SiO2used as an insulating film of the gate, put a layer of polycrystalline silicon of n-type and perform etching using a mask of photoresist, forming, as shown in Fig, dictionary bus A21.

If the thickness of the layer of polycrystalline silicon of n-type will be more than half of the gap between the information tire while generating the data bus can be performed recess (or groove), easily forming a circuit from the resist. The presence of the auxiliary region between information tire allows to obtain an effect similar to the implementation of the desired groove width, even for the boundary areas of flat memory element. After forming the layer of polycrystalline silicon of n-type produce etching and after reducing the thickness of the layer deposition of silicon form dictionary tire with a lower resistance. After forming the dictionary tires on them put insulating film and perform the alignment of the contacts, as shown in Fig. After etching the insulating film in the upper part of the schematic form the contact A26 for locking Inoi data bus (2) A2, contact A27 to the diffusion layer A16 MOSFET sampling, contact A25 for electrode A15 gate MOSFET selection and contact A34 dictionary for bus A21. Because the bus A3 source is located below the local information tire A2, the contact window A23 for it should be made in local information bus (2) A2. In addition, with the purpose to not take up a large area for placement of the sampling transistor, the active width is determined step matrix for connecting the common data bus and a transistor of sample required to perform the contact hole A24, which must pass through the local information bus (2) A2 and bus A3 source. This scheme allows you to create a structure in which a contact hole and an information bus overlap. In this place the contact area local information bus (1) A1 is absent, due to the need for adjustment after its formation. In order to avoid short circuits with a layer placed around a hole in the contact hole is formed in the side wall of the insulating film by selective dry etching holes and deposition of the insulating layer.

The cross-section of the contact region of the MOS transistor of the sample after the formation of the side wall shown in Fig.

Contact A34 dictionary tires, is the th at the end of the memory cells, shown in Fig.

the size of the auxiliary structure A35 made from the same material as the layers of a data bus which is different from the material of the auxiliary information of the tire. This support structure made contact A34. This pin allows for the formation of the polycrystalline silicon layer to get the effect of information tires deepening in the same way as when forming the dictionary tires. After forming the support structures put metal and after defending the photoresist perform etching, forming, as shown in Fig, the first layer metal interconnections M1.

The resistance of a conductor A29 interconnects M1 reduced back embossed electrode A15 gate made of polycrystalline silicon. Connection A28 bus source A3 is also the interconnect M1. Similarly executed and the connection (A30) from the local data bus (2) A2 and with the diffusion layer of the MOS transistor of the sample. In addition, after forming the insulating film between layers are contact holes, after which a layer of metal, and after defending the photoresist is etched in the process of forming the second interconnect M2 of metal, as shown in Fig. is the interconnect M2 is made of a common information bus A31. The formation of a common information bus interconnect M1 prevents other interconnects, since all planar matrix of memory elements is made with a very small step. Therefore, for General information tire A31 need to use the interconnect M2 or more located above the interconnect. The same applies to the schema of the reader, which is connected with the outside of the matrix of memory elements, ie, in other words, you need to connect the schema is read to the layer located below a common data bus, for example to interconnect M1. The arrangement of the auxiliary patterns common data bus within a flat semiconductor storage element allows to obtain the same effect as for the local data bus.

Fifteenth option

The following describes the fifteenth variant of the invention, which is illustrated in Fig (a), 30 (b) 32.

On Fig (a) and 30 (b) shows a cross section of a matrix of memory elements made by this variant. On Fig (a) shows the structure of the matrix after the formation of the channels, and Fig (b) after the formation of the dictionary tires. The device, made on the fourteenth variant, two memory cells are arranged vertically. In this embodiment, unlike the other uses only one memory cell, which works on the same is the very principle as in other versions.

Channel A38 made vertical and connects the local data bus A37 and bus A36 source. The electric potential of the channel is defined dictionary bus A. The structure according to this variant of the invention has a lower in comparison with the fourteenth variant degree of integration, but the presence of several different tabs (grooves) and a more flexible manufacturing process.

On Fig shows a top view of a planar semiconductor storage element. The contact technology in this variant corresponds shown in Fig fourteenth variant of the invention. In the flat element local information bus connected to a common data bus via the MOS transistor. In the fourteenth embodiment of the invention, this transistor is designed to sample the top or bottom of the cell, and in this case it reduces the capacity of the local data bus, which during operation is electrically connected to a common data bus. If the capacity information on the local bus to reduce, when the same electric current can more quickly and to a greater extent modify the electric potential, providing higher performance devices. This advantage is not limited to this variant implementation of the invention and the structures with vertically is mi channels, as in the fourteenth embodiment, and can be implemented also in the structures in which the channels are parallel to the surface of the device, as shown in Fig (a) and 31 (b).

The main embodiment of the matrix of memory cells shown in Fig (a) and 31 (b). The upper drawing (Fig (a)shows the structure of a matrix of six elements after formation of the channel. Matrix view after the formation of the dictionary of the tire shown in Fig (b). The structure has a local information bus (1) A39 motorway, local information bus (2) A41 and one common bus A40 source. The electric potential of the channel is defined dictionary bus A43. If the base size of the structure element is equal to F, the size of this structure is equal to 6F2, and it is compared with the spatial structures is easy to make. Further explanations refer to Fig. The contact hole includes a contact hole A46 to connect with bus A36 source contact hole A for connection with the gate electrode of the MOS transistor and a contact window A48 motorway to connect the diffusion layer of the MOS transistor with a common data bus. This variant of the invention differs in that the contact hole can be performed during the same operation, and the fact that the number of operations of manufacturing this device is smaller than in the manufacture of devices by cataracts is the fact a variant of the invention.

Below are related to different variants of execution of the invention (from the sixteenth to the twenty-second) examples of write operations, erase, a write-verify, erase verify, cleanup and multivalued data storage in the proposed invention the matrix of memory cells, performed on various options.

The base matrix, which is used in these examples, shown in Fig. Obviously, in addition to this matrix in these devices can be used and the previously described structure of the memory elements.

Sixteenth option

The sequence of operations of reading, writing, and erasing of information shown on Fig. Read the information comes from item 1 and item 2. When erasing data is erased from item 1 and item 2. When recording element 1 record information "1", and in item 2 is "0". When reading first create a preliminary charge (step 1), and then to the source, the information tires and dictionary tires make rated voltage reading (step 2). The reading is carried out by measuring the amount of current which characterizes the information stored in the cell 1, and flows in the data bus 1 and DC, which characterizes the information stored in the cell 2, and runs through the data bus 2. The electric current in the dictionary the tire 1 when the value INF is rmacie "0" for more current corresponding to the value of the information "1", making it easy to distinguish from each other the two possible States of the memory cell.

When the voltage less a threshold, and storing information "0" on the vocabulary of the tire 2, the current in the cell 3 and cell 4 is missing regardless of the information stored in them. Even with a large number of cells in the matrix they all work the same way, since the voltage reading is applied only to the dictionary tire management cell, from which is read the information, and on the other dictionary tire associated with the same data bus, install a low voltage. The following describes the erase operation. The erase operation is performed simultaneously for element 1 and element 2. When performing a verification operation for each erased bits, you must have a list of cells in which the information should be erased. Before filing the cell voltage erase it served voltage recording (step 1).

The implementation of this step prevents the application of the erase voltage to the cells in which the write operation after the erase has not been executed, and contributes to the suppression of unwanted fluctuations of the characteristics of the device. After that, in accordance with the list of cells set the voltage on the corresponding data bus (step 2).

Voltage (for example, 5 V), own the right to the data bus, which is associated with the cell in which erasing is not fulfilled, must be higher than the voltage (for example, 0 V), which is appended to the data bus associated with the cell in which erasing is executed completely. To check the status of the cell element after the filing of a low erase voltage (for example, 10 V) (step 3) on the vocabulary of the bus serves the normalized voltage (for example, 0.5 V) and the control voltage changes on the vocabulary of the bus (step 4, step 5).

As a result, if the value of the threshold voltage of the cell will be lower than the standard voltage, the cell is excluded from the above list (list of cells to be erased). The erase operation ends when the list of Erasure becomes empty, but if the cells are still in the list, then the erase operation is performed again by returning to step 2. In step 2, the voltage that is applied to cells removed from the list erase(0 V)and the potential difference (in this case 10) relative to the dictionary tyres are also small, which eliminates the possibility of unwanted Erasure. In this sequence of operations is repeated for cells in which you want to erase, right up until the required threshold voltage becomes less than the normalized value.

The write operation requires that the tsya in recording information, represented by "0" or "1"in item 1 and item 2. When recording information on the bus corresponding to the cell from the list of cells that should be written to "1", voltage is applied (step 1).

Voltage (for example, 0 V), which is appended to the information tire cells in which "1" is not written completely, lower the voltage applied to the information tire cells in which "1" or "0" is made entirely; when it is set to a large potential difference relative to the dictionary of the tire. Then to check the status of the cell after submission (step 2) at high voltage (for example, 15 V) entry to the dictionary tire normalized applied voltage (for example, 2.5 V) and the measured voltage change (step 3, step 4).

If the measured voltage is higher than the preset threshold voltage, the cell is removed from the list of cells that are intended for recording. In other words, the write operation ends with an empty list, but if cells still remain in the list, then the whole procedure is repeated, starting with step 2. In step 2, the voltage (in this case 5 V)applied to the data bus, more for cells that have been removed from the list, and a small potential difference relative to the dictionary of the bus (in this case 10) avoids excessive change the value of the threshold voltage. In this is the example we were talking about the list of cells for recording "1", however, similarly you can use and a list of cells in which "1" is executed, or a list of cells to "0"is written, and these lists can optionally be used during the operation of the control record, which can be completed at the moment when all the cells will be included in the list. This principle can also be used in relation to the list of cells that are erased. To simplify the description of all of the above definitions will be used in the future.

In this embodiment, polycrystalline silicon was used in the data bus, buses effluent dictionary tire and channels, however, the use of such material does not necessarily and for these purposes can be used instead and various other semiconductor materials or metal. For the formation of information tire, tires drains and channels can also be used KND-substrate and the bulk silicon substrate. Their resistance when using a bulk silicon substrate is reduced, which allows you to increase the memory speed. For forming channels is used undoped polycrystalline silicon, but with the same purpose it is possible to use polycrystalline silicon with impurities. In addition, in this embodiment, as a conductor of electric current and as a storage medium for ELEH the electric charge storing information used for the thin layer (1) of polycrystalline silicon; however, the formation of low resistance in a thin layer in the role of conductor and nakaplivaya charges to store information, can be performed in other places scheme. In addition to the semiconductor material for the accumulation of electrical charges can be used and the metal. However, as mentioned above when considering the principle of operation of the element, the storage area of electric charges has the appearance of a small structure, which is surrounded by a high potential barrier. This structure is distinguished by use of different size and material properties, since the path of flow of the electric current and the grip area of the electric charge is made separately from each other.

Seventeenth option

The device, made according to the seventeenth to the variant shown in Fig and 36.

The principle use of the register for storage of the list of cells for the variant shown in Fig and 36, the same as in the sixteenth embodiment, which is illustrated in Fig. The sequence of operations in this embodiment are shown in Fig. Structural diagram of a semiconductor memory device for this option, shown in Fig. The number of tires I/o can be reduced by sequentially performing the exchange of information with the external device is you in a certain sequence using a shift register. The principle of operation of this memory cell is the same as for the sixteenth option. Each bit of the register corresponds to the data bus. In this embodiment, the cell 1 and cell 3) correspond to the first bit of the register, and the cell 2 and cell 4) correspond to the next bit of the register. When erasing data incomplete Erasure corresponds to the state "1", and the complete Erasure corresponds to the state "0". In other words, when erasing information in item 1 or item 2 condition {1, 0} register indicates that the erasing element 2 is executed or that the erasing element 2 is not completed. When you return to step 2, when register bit corresponding data bus is equal to "1", the data bus is required for the erase voltage (for example, 5 V). The verification process of the erase ends when the potential of the corresponding bit of the register will be equal to 0 (for example, 0 V), and when all bits of the register will be equal to zero (0).

During recording in the cell information in step 1 recorded information bits will be inverted relative to the corresponding bit value of the register. In other words, the presence of a register during the execution of step 1 bits {0, 1} means that the cell 1 is written to "1"and the cell 2 is written "0". Further, after step 2, with the full entry in the cell information "1" information on the input of the corresponding b is the register will be equal to "0". If in step 1 the corresponding bit of the register is equal to "1"on the data bus, as if erasing a corresponding potential (for example, 0 V), and if the bit of the register is equal to "0"to the bus put a high voltage (for example, 5 V). The operation of the control recording ends when all bits of the register will be equal to "0".

Eighteenth option

The principle of operation of the device made according to the eighteenth to the variant shown in Fig.

In this embodiment, the verify erase is not performed for each bit, and the erase cycle is completed when the threshold value for all cells, which need to be done erasing, will be less than the specified threshold voltage. With this method of erasing in step 2, the erase voltage is supplied to all selected cells. The control of each bit is not necessary, and therefore this method is relatively simple. Avoid excessive erasing the cells you want to apply a stable voltage. With respect to the cell erasing means the injection of electrons, and therefore the end of the cycle for all cells, which is erasing, they need to build capacity is greater than the specified threshold voltage. In this way, almost all cells, where the potential exceeds the threshold voltage is agenie, when you wipe there is a decrease of the electric current, which can significantly reduce current consumption during the erase operation.

Nineteenth option

The nineteenth embodiment of the proposed invention device shown in Fig and 39.

The structure of the memory cell in this embodiment is the same as in the seventeenth embodiment. In addition to performing verification operations of writing and erasing, this option is also run during data storage operations regeneration. As indicated in the description of the first variant, in the memory cell during the recording of information in a small number of stored electrons with high probability there are things like thermal excitation and tunneling effect. The same applies to the storage of information that is the cause unstable operation of the cell when storing information. However, the known method of stabilizing the storage of information by increasing the thickness (or increase the width of the potential barrier insulating film between region of origin and region where the stored electric charges, is not optimal, since the recording time this significantly increases. The proposed semiconductor memory device has a high speed recording and erasing, the same as in the blocks of the flash memory, however, performing the OPE is the situation of recovery during storage of information, you can provide both high speed recording and erasing and sustainable storage of information. Furthermore, with respect to ZUPU, which are widely used as a volatile memory with a high level of integration offered by the storage element can be made of one cell based on a single transistor that allows you to create a memory element with a simple structure and high degree of integration.

Diagram of the device according to this variant shown in Fig. In this embodiment, unlike the seventeenth options provided by the use of two types of registers. The sequence of stages of regeneration information shown on Fig. Just as in the sixteenth embodiment, in this embodiment, is provided by the use of four adjacent memory elements. The sequence of operations of read, erase and write corresponds to the seventeenth option of carrying out the invention, and all operations are sequentially repeated when selecting vocabulary tires. Data dictionary tires read and store in register 1. In this embodiment, each bit of information is stored in the register 1 in inverted form with respect to information of a memory cell. After that, the erase operation described above for the seventeenth variant implementation of the invention. During the operation of erasing the data read from the region is tra 2, lost that determines the need for the preparation of the case 2. Data from register 1 again rewritten in the memory cell. All these operations are sequentially repeated when switching dictionary tires. Stable storage of information provided by the fact that the period of the regeneration operation is significantly less than the average time during which the loss occurs is stored in the memory information. Case 1 or case 2 is used to check the operations of erasing and writing. When the temporary storage register 1 register 2 erase the information in the register 1. After the wipe and after overwriting the information from register 2 to register 1 executes the write operation. The operation of recording, erasing and reading are performed similarly to the seventeenth embodiment. However, in the read operation to make adjustments, as in this case to improve performance when performing erase and write width of the region of the potential barrier or the height of the potential barrier between the grip area of the electric charge and the outer regions should be reduced. Thus during the operation of reading the information stored in memory will be lost, and therefore, to prevent this loss of information you want to overwrite. The sequence of such about what erali same as for the operation of regeneration, and the only difference is that the read information is transmitted to the external device. The same method is used and in other embodiments, performing the operation of regeneration.

Twentieth option

The twentieth embodiment of the proposed invention device shown in Fig and 41. The block diagram of this device is shown in Fig. The sequence of operation of regeneration shown in Fig.

This option differs from the nineteenth to the fact that when performing the verification operation erase is not performed for each bit, and the erase operation is completed when all the cells where data should be erased, the voltage drops below the specified threshold voltage. In all other respects, this option is similar to the nineteenth variant and is characterized by the fact that it is not required to have a register of information on each bus during the erasing process, because the verification of Erasure is not performed for each bit, and the fact that it does not require the second register.

Twenty-first option

The block diagram of the twenty-first variant implementation of the invention shown in Fig.

The distinctive feature of this variant is that in one cell is stored more than one bit of information (multivalued data storage). With ructure of the memory element in this embodiment is the same as in the sixteenth embodiment.

On Fig shows the experimental characteristics of the unit cells according to this variant implementation of the invention. The graph shows the change of the electric current in the data bus in time when the bus voltage source of 0, the data bus 2 and on the vocabulary of the bus 9 Century With a slight increase in electric potential on the vocabulary of the bus injection of electrons is slowed down, which simplifies the process of measuring changes in current over time. From the graph it is seen that when a single accumulation of electrons in the storage area in the threshold voltage changes associated with the dispersion or dispersion, and the electric current is changed stepwise. Each threshold value corresponds to a different information that makes it possible multivalued data storage. For example, the condition in which has gained one electron corresponds to the information "0, 0", the two accumulated electrons corresponds to the information "0, 1", three accumulated electrons corresponds to information "1, 0", and the four accumulated electrons corresponds to information "1, 1", which means the possibility of storing two bits. This variant of the invention is characterized by simple identification of the state compared to devices with multiple storage where data is determined by the sequential comparison of the ha is of acteristic. The structure of the storage device in this embodiment of the invention is similar to the structure of the nineteenth variant and is characterized by the fact that the registers corresponding to each of the dictionary tires have a large number of bits, as well as the voltage and timing characteristics when performing write operations and read. In this embodiment of the invention the capture of one electron corresponds to the accumulation of one piece of information, but, as mentioned, the capture and removal of electrons occur probabilistic processes, which cause the instability and failures in working memory and degrade its characteristics in terms of recording and erasing information. To increase the stability of the storage of information in memory effectively influences the operation of the regeneration information and performing the scanning operation when recording and erasing. The multivalued recording of information is performed by changing the recording time (the duration of each pulse of record or their sum). The recording time is characterized by a value proportional to the duration of the record. As in the sixteenth embodiment, the storage area in this device has a small size, and injection of one electron affects the probability of injection of the next electron, but the function describing the effect on the number of captured electrons has the form ek the components. For selective recording of information is preferable to increase the number of voltages recording and not recording. Voltage recording varies, because the injection of electrons under the action of a voltage from an external source for data erasing only the change of potential in the field of capture of charges there is a strong likelihood that the next electron will injectionin the previous one. It should be noted that for this you can use a different method of changing the voltage recording and method of changing the recording time. To perform read operations in this case because of the large number of read States you want to use the generator of the reference voltage. In a multivalued memory device to perform a control operation or the regeneration operation multivalued information is also required to have appropriate devices to store multiple values of information.

Stable operation of the storage device is supported by a large number of accumulated electrons (if, for example, five electrons correspond to the coincidence information)that more effectively characterize the recorded information than one electron. When this memory structure and sequence of operation remain the same. The memory device, to the m storage of information is performed a large number of electrons, is less than unit, configured to store one electron, the probability of occurrence of the above phenomena and more stable operation. When this change for the better and other characteristics of the device, in particular elongates the cycle of operation of regeneration and reduced current consumption.

The twenty-second option

The regeneration operation for the twenty-second variant implementation of the invention shown in Fig.

This option differs in that the regeneration operation performed at the time of storing information, and check erase/write do not produce. The structure of this memory element is the same as in the twenty-second embodiment, however, the crystalline silicon particles in the storage area have a size of about 4 nm. During a write operation and the injection of one electron in one crystal particle the probability of injection of the second crystalline particle is significantly reduced. The time required for injection of the second electron, the much longer time required for injection of the first electron. Therefore, the voltage of the records required to be maintained long enough for the time that is greater than the average time of injection of one electron, and given some probabilistic deviations this time, in addition, must be less than the average time required DL the injection of two electrons. Therefore, this option provides stable storage of information, and the storage of one bit in the storage element or in the multi-level data storage in the form of a large number of bits in a single cell is not required to perform the verification operation.

Below are described some examples of peripheral circuits with a small surface area that work with small electric charges, have low noise and are most suitable for use with single-electron memory blocks that are sensitive to noise impacts, as well as methods of making such peripheral circuits having the required characteristics and a small surface area, which allow you to create an integrated storage elements with a high degree of integration, corresponding to variants of execution of the invention with the twenty-third to twenty-fifth.

The symbol of the elements of these devices is shown in Fig. In all of these devices in order to distinguish them from ordinary field-effect transistor, the grip area of the electric charge represented by the black dot shown in the diagram of a semiconductor memory element, depicted in Fig.

Twenty third option

Diagram of the semiconductor memory device according to the twenty third variant of execution of the invention and graphics, and lusterous read operations erase and write, shown in Fig-49.

Schematic diagram of this situation is shown on Fig. On Fig for simplicity, shows only one pair of information of the tire, although in practice, in the semiconductor storage device has a lot of such tires, located as shown on the drawing next to each other. Shown in Fig elements MM1, MM2, MM3, MM4 forming a multilayered matrix memory and are located on the top and bottom layers. The MOS transistor M3 and the MOS transistor M4 are MOS transistors sampling the local information of the tire. MM1, MM3 represent storage elements of the lower layer and connected to the lower layer from the local data bus LDL. MM2, MM4 are storage elements of the top layer and connected to the upper layer with local information tire LDU. The bus source is made common to the upper and lower elements. Bus LDL connected to the local data bus D1 through transistor M3. Bus LDU connected to the local data bus D1 through transistor M4. Group of a matrix of storage elements and MOSFET selection of local information tire hereinafter referred to as a memory block. In the device there is also a shared data bus D2 and D1. On the data bus D2 is an auxiliary memory unit, consisting of auxiliary storage E. the elements of DMM1, DMM2, DMM3, DMM4 and the MOS transistors M1 and M2 sampling the local data bus that is connected to other circuit elements as well as the main unit memory.

Timing diagrams illustrating the operation of the circuit shown in Fig and 49. To discharge these schemes on a common data bus D1 and D2 are MOS transistors M5 and M6 of the preliminary discharge. In addition, these common data bus D1 and D2 are connected through the MOS transistors M7 and M8 with the read amplifiers (differential amplifiers), consisting of transistors M13, M14, M15, M16.

For amps they read through the transistors M11, M12 are connected to the power supply. For discharge of the read amplifiers connected to two sides of the tires D3 and D4 input/output through the MOS transistors M9 and M10.

The following describes the operations of read, erase / write, executable proposed in this embodiment the device. This device is characterized by the fact that reading and writing are performed by switching the upper and lower storage elements. In addition, in the description below, the high level threshold voltage storage element upper area designated as "1"and the low level threshold voltage is indicated as "0". In addition, the high level corresponds to a logical "1"and the low level corresponds to a logical "0". When necessary the particular logic levels and the threshold voltage can be obviously, inverted.

Before consideration of the operation of the circuit shown in Fig, explains how changing the voltage applied to the storage elements when performing write operations and erase.

For read operations on the memory cell, which is designed to read (in this case the cell MM1), and on the local information

the tire of the respective supporting element (in this case DMM1) voltage preliminary charge (for example, 2.5 V), and a dictionary bus (W1) and bus (DW1) auxiliary memory element voltage reading (for example, 2.5 V), resulting in the inclusion of MM1 and MM2 and discharging the local data line (LDL) and the local auxiliary data bus (DLDL). On a secondary storage element DMM1 pre-installed state with a threshold voltage in the range from "1" and "0". Therefore, when in MM1 data "0", the voltage on LDL decreases rapidly, and when the data is "1", the voltage decreases rapidly to DLDL, resulting in LDL supported high voltage.

When the erase operation, the voltage at the top of LDL and lower LDU information tires and tire S source corresponds to a high level (for example, 5 V), while the dictionary to the bus W1 is applied to the erase voltage (e.g. 10 V), the resulting drop of the threshold voltages of all the memory elements.

When performing a write operation on the bus (S) source level is set to high voltage (for example, 5 V), information on the local bus LDL storage element (in this case, MM1), which should be written "1", a voltage of 0 V, and information on the local bus LDU storage element (in this case MM2), which should be written "0", is supplied with a high voltage (for example, 5 V) and a dictionary W1 bus voltage recording (for example, 15 V). In the Appendix to the dictionary tire and tire data MM1 voltage 15 V threshold voltage increases. This process occurs while writing "1". When the application information to the tires, dictionary tyres, tyres source and dictionary tires MM2 voltage 10 V does not increase the threshold voltage. This process occurs when "0"is written.

In the above description, the voltages shown only as an example. It is significant that during the recording of the threshold voltage increases relative to the applied voltage accounts for a very short time to the maximum allowable level, and during the erase threshold voltage is reduced relative to the erase voltage for a very short time to the maximum allowable level.

Bus voltage source and information on the local bus storage element in which is written "0", maintains high threshold voltage at the maximum high in relation to the recording of "1" level, and during the read voltage dictionary bus and the voltage of the local data bus limit the increase of the threshold voltage maximum possible low level.

Described in detail below, the read operation performed using elements of MM1 and MM2 memory and auxiliary elements DMM1, DMM2. It is assumed that the information "0" is recorded in the bottom cell MM1 memory, and "1" is recorded in the top cell MM2 memory.

The timing diagram of read operations shown in Fig. First LD1 and DLD1 are under high voltage level, local information bus, the selected MOS transistor M3, and local auxiliary information bus, the selected MOS transistor M1 included, local information bus LDL connected to a common data bus D1, local auxiliary information bus DLDL connected to a common data bus D2. Then PDG sets the high voltage level, the MOS transistors M5, M6 recharge switch and recharge LDL, DLDL, D1 and D2. On SADG is also set to the high level voltage, the amplifier of the read MOS transistor discharging M9, M10 is turned on and the voltage at both inputs D3, D4 of the read amplifier is reduced to the potential of the ground. Then include a dictionary W1 bus and auxiliary dictionary bus DW1, and information bus begins to run. In a memory element MM1 is "0", and its threshold voltage is lower than the auxiliary storage element DMM1, and the faster the voltage drop across D1 than D2, determines a rapid discharge. Then T1G is set to a high voltage, the MOS transistors M7, M8 are included, and General information tire D1 and D2, the voltage supplied to the read amplifier. After that, the voltage on SAP is reduced to a low level, and the SAN rises to high level, thereby turning on the MOS transistors M11 and M12 and the inclusion of the read amplifier, and the voltage difference on the two tires I/o D3 and D4 increases to the voltage of the power source. This process ensures that the data is read from the lower memory element MM1, and read the status of the top element MM2 memory is similar. At this time, as the MOSFETs sampling the local information of tires (tyres signal LD2, DLD2) are used, the transistors M2, M4. Dictionary W1 bus and auxiliary dictionary DW bus are enabled and begins discharging the information bus, because due to the fact that the threshold voltage for MM2 higher than the threshold voltage DMM4, the spacing D1 is slower is about, than D2, and the voltage across it remains high.

The following describes the process of executing the erasing process. Before erasing all of the cells are recorded. This entry is required to prevent excessive erasing cells (threshold should not be exceeded) for continuous recording of "0". On LD1 and LD2 is set to a high voltage, the MOS transistors M1, M2 sampling include local data bus, and the upper and lower local data line LDL and LDU are connected with a common data bus D1. On PDD served low voltage, and the PDG served the high voltage MOS transistors M5, M6 preliminary discharge data bus are in the on state. On the vocabulary of the tire W1 to the point where the voltage between LDL and LDU reaches a high level voltage is applied to the account. The voltage on the PDD increases, and the transistors M1, M2, M5 are included. On the vocabulary of the W1 bus to the high voltage between the upper and lower information tire LDL and LDU voltage erase. This process allows you to simultaneously erase the information in both the upper and lower elements.

The following describes the write operation. It is assumed that in the lower memory element MM1 is "0", and in the upper storage element MM2 written "1". While recording the voltage at the upper and lower information the tires must be different. However, while recording the selection of the memory element must be such that the voltage applied to local information bus, it was constant (unchanged). Therefore, the entry at the top and bottom of the cell must be performed separately. In order to avoid adverse effects on the storage element of the recording process in another cell on the local information bus is supplied with alternating voltage. On the bus D3 input/output of the read amplifier is fed to the low voltage, LD2 served the high voltage MOS transistor (M4) sampling the local data bus is enabled, and the upper local data bus LDU is set to low level. Then LD2 served low voltage, M4 is turned off, and the bus is supplied with alternating voltage. Then on the tires D3 and LD1 is set to the high voltage MOS transistor M3 sampling the local data bus is enabled and the voltage at the lower local tire LDL transmission increases. Then on the vocabulary of the bus W1 is set to a high voltage records, and M3 is on. This process allows you to record "0" in MM1. In this case, M2 should be in such a condition that the voltage on the LDU has increased, and the write "1" in MM2 was impossible.

Then the voltage on LD1 is reduced, and LDL, when the switch M3, the applied AC voltage is. After that, the voltage on the D3 is falling and LD2 increases, the transistor M4 is turned on and the voltage on the LDU is reduced. At W1 is energized records. This voltage in MM2 is written "1". While MM1 is enabled and the voltage LDL does not change, and in MM1 is written "0".

This embodiment of the invention differs in that the local data bus for each of the located one after the other storage elements are connected to one common data bus MOS transistor sampling and switches in a certain order during the operation of writing and reading, which eliminates the need to increase the number of General information tire or amplifiers read, even if memory cells form a multilayer structure, and it allows to increase the surface area (or size) of the peripheral elements of the integrated circuit.

The memory element in this embodiment includes two layers, but it can run sandwich. In addition, local information bus can be placed on the plane and not on the multi-layer structure. It is also possible combined solution with the placement of the multilayered structure of the local information of the tire on a flat surface.

Twenty fourth option

Below with reference to Fig described scheme of reading, writing, and erasing semiconductor application : nausea device according to the twenty-fourth variant implementation of the invention. This variant differs from that shown in Fig the fact that the storage elements are made in all points of intersection of the dictionary and tire information the tires.

Currently known methods relative position of the read amplifier and a data bus so that data bus on both sides of the amplifier readout were performed either straight or bent in the same direction. The advantage of direct forms of tires is that the storage elements can be placed at all points of intersection of information tires and dictionary tire that provides a high degree of integration, but it has a drawback that is associated with a high level of noise generated in the dictionary tires. The advantage of the bent shape of the tire, on the contrary, is the low level of noise in the dictionary the tires, and its shortcomings are related to the fact that in this form of tire storage elements cannot be placed at all points of intersection of information tires and vocabulary tires. In this embodiment of the invention the storage elements are located at all points of intersection of information tires and dictionary tire information the tires made bent. When reading from the memory element MM1 memory elements M and M also excited. However, the MOS transistors M7 and M8 sampling the local information of the tires while off and on the common information bus D2 no interference does not occur. The storage element when the read is non-volatile, and therefore no change in the data recorded in MM and MM, not happening. The advantage of single-electron memory blocks is very small patterns, and deficiencies associated with the work on low current and high sensitivity to noise. In the proposed invention the device data bus is made bent and is not sensitive to noise, and therefore, such a storage element has the advantages of high level of integration.

In this embodiment, the reading of information from all storage elements in the same dictionary the bus is performed in four steps. However, the information recording can be performed in two steps, as in the twenty-third embodiment, and wipe - in one step, since the common data bus is made separate.

In this embodiment used a two-layer storage elements, however, they can be run with three or more layers. The local data bus can be placed on a plane without using a multilayer structure. You may also combine these solutions with a multilayer structure of the local information of tyres placed on the plane. In the proposed device is quite COI is lesofat only one local information bus. The principal aspect is the placement of storage elements in all the intersections of the respective General information tires and dictionary tires.

The operation of the device in accordance with this option was discussed above with the use of single-electron memory, however, when reading from non-volatile memory cells other elements can be performed in the memory cells with a floating gate or blocks of the flash memory.

Twenty-fifth option

Scheme I/o and test semiconductor memory device in accordance with the twenty-fifth variant shown in Fig. Diagram of input/output and check contains the schema migration, which transmits data from the read amplifier to the shift register circuit A11 (discriminator) identify all "0", checking whether all the data when reading "0", the circuit A11 (discriminator) identify all "1", which determines whether all the read data is "1", and the shift register, which temporarily stores data from the read amplifier, and then sequentially outputs the data to an external device. The shift register is used to enter the recording data from the external circuit and sending them to write to the memory cells. The shift register also determines the state of the checkbox svidetelstvo is about the end of the record when performing a validation operation. The device has four shift register corresponding to the upper and lower memory cells, two shift register for each shared data bus.

Circuit shift registers 2, 3 and 4 on Fig not shown, but shown only the signal bus. As a matrix of memory cells is used with the structure shown in the twenty-fourth embodiment of the invention, however, you can also use other patterns.

Below is the description read, write, erase verify, and validate the entry.

First reviewed the read operation. When reading data from a memory element MM1 according to the procedure described for the twenty-third and twenty-fourth embodiment of the invention, the information appears on the bus D3 input/output of the read amplifier. Then on the bus P0 transfer is set to a high voltage, and on the bus P1 is set to low voltage, and includes transistors M21 and M22. If the information in D3 is equal to "0", the M23 is enabled, and this "0" through M21 and M23 appears on the bus D5 I/o shift register. If the information in D3 is "1", the M24 is included, and this information appears on the bus I/o in the form of "1" of the shift register through M22 and M24. Then SRMF served low voltage and turns off the main feedback shift register 1. At high voltage the research Institute of signal SRI1 included m, and data is fed to the shift register 1. At high voltage SRMF1 included M41, and the data held in register with the main feedback shift register 1. This procedure is repeated for MM2, MM and MM, and relevant data is entered to the shift registers 2, 3 and 4. In conclusion, SRMF and SRSF1, SRSF2, SRSF3 and SRSF4 alternately inverted, with all four shift register simultaneously and display the information to an external device.

Here's the write operation. Data input in the shift register are in DI1, DI2, DI3 and DI4, alternately inverted in SRMF and SRSF1, SRSF2, SRSF3 and SRSF4, all four shift register simultaneously and data is transferred to the appropriate information bus. At the end of data transfer on SRSF set low voltage, and SRMF1, SRSF2, SRSF3 and SRSF4 is set to a high voltage, and feedback is formed only in the leading of the device. After this step, the voltage on SRO1, SRI1, T2G rises, as described for the second variant implementation of the invention, M44, m and M25 are included, the data is transmitted on the bus D3 input/output of the read amplifier, and recording is performed.

Below is the verification operation erase. Check erase is reading information from the memory elements, in which it was erased, confirmation (verification that the that the erasing has been completed, and re-erasing those memories, in which the erasing has been performed not to the end. Erasing can be done simultaneously in both, top and bottom, the memory cells, as in the second embodiment, but when the erase verification mode it must be run separately for the upper and lower memory elements. First is read and the data input into the shift register. Then A0G is set to a high voltage, are included M31, m, and bus D5, D6 I/o shift register are grounded. After installation on AL0 high voltage creates a high resistance state. Then SRO1 is set to high voltage, is included M44, and the data is output from the shift register 1. The data from the shift registers from the 2nd to 4th are sequentially displayed in the external circuit in exactly the same way. When all output data "0", the high voltage on AL0 supported without turning off the M32, M. If even one bit of the output is equal to "1", the M32 is turned on and the voltage at AL0 falls. The voltage at AL0 is, therefore, control, and his fall means that the erasing is not fulfilled.

The following describes the operation of the checking account. Proof that all the read data is equal to "0", the verification of Erasure, however, when examining the record the record data for each memory element are different from each other, and so you must have a graph that shows whether completed an entry for each storage element. In this embodiment of the invention, this count is recorded in the shift register. During initial operation, the write data written in the shift register represent the inverted data (this method is convenient because of the need for adjusting the voltage on the local information of the tire with the values of signals a shift register). These inverted data are interpreted as "1" on the graph end the recording. In other words, "0" indicates that the entry "1" is not fulfilled, on the other hand, the "1" indicates that the entry "1" is executed completely or having to start recording the beginning it was not recorded "0"). While reading perform after it was recorded, and the data shift register overwrite as "1" only when reading "1"and the scan may be performed in the case when all the data shift register is equal to "1". The data shift register is overwritten to "1" only when the read data is "1". During reading after recording unlike conventional read P1 is set at a low voltage, but high voltage P0 is not installed. High voltage is transmitted through the transistors M22 and M24 when reading "1", but when reading "" M21 and M24 are turned off, and the data stored in the shift register. At the end of the update flag, which indicates the end of recording, the system checks whether all the data "1". For this first A1G is set to high voltage, the transistors M35, Me included, and pre-charging the tires D5 and D6 I/o shift register. Then, after reducing the voltage at AL1 scheme goes into the high impedance state. After increasing the voltage on SRO1 data from the shift register are output to the external circuit. While in the external circuit are sequentially displayed in the same way and the data from the shift registers from 2nd to 4th. If all the output will be equal to "1", the low voltage at AL1 supported without switching transistors m, M38. If even one of these outputs will be equal to "1", the transistor M32 is turned and the voltage at AL1 will increase. The voltage at AL1 therefore, is a control, and its increase indicates that the record is not yet fully implemented.

In this embodiment, the overwrite values check box, which indicates the end of recording is carried out using one side of the circuit transfer only when the read data is "1". At the same time, feeding the signal from the box, which indicates the end of recording on the bus input/output shift register sizes peripheral circuits, mo is but not increase. In addition, using the threshold voltage of the auxiliary element as a reference for a read operation, a verify operation after the write and verify operation after the erase, you can create a device with high resistance to noise.

As a shift register, in addition to the device, the structure of which is shown in Fig, you can use any device that provides static information storage. In addition, when the secondary key data to the memory cell as a shift register, you can use dynamic shift register.

The twenty-seventh option

General diagram of the device according to the twenty-seventh variant implementation of the invention depicted in Fig. The semiconductor memory device in accordance with this variant is essentially the same as the device according to the twenty-sixth option and supplemented by the decoder, a driving device and a control circuit. In the center of this device are a large number of memory blocks, one of which is an auxiliary memory unit. The following describes the operation of the device. First input pre-decoder command (predestinator) command that specifies the type of operations: read, erase or write. Then, the voltage corresponding to each t is coy team transmitted in each specifies the device through the switch voltage on the team that submitted on its entrance. Then at a signal, which is input to the address decoder, the selected memory cell. When the signal on the input timing diagram specified for the twenty-fifth variant implementation of the invention, the respective cell is a read operation, erase or write.

Below is described the method for selecting the memory element. The address signal is fed to the input of predestinator address and the local decoder data bus. Signals from predestinator addresses are divided into two groups of signals which are fed to the inputs of the decoder block and the decoder dictionary tires. This process allows you to select one unit one vocabulary bus.

Choose the upper and lower information of the tire is performed using signals from the decoder's local data bus. The upper and lower local data bus can be selected separately or simultaneously in the order determined by predesignation team. This variant of the invention allows to create large-scale semiconductor storage device.

The twenty-eighth option

Structural scheme of the twenty-eighth variant implementation of the invention shown in Fig. In this embodiment, there is one additional is sustained fashion shift register, which added to the shift register from the twenty-seventh variant of carrying out the invention and which allows the operation of the regeneration data.

Thus, in the present invention according to the above description features compact semiconductor memory device with high integration, and opened the way for its operation.

1. Semiconductor memory device containing a large number of memory elements, each of which contains a region of the source and drain region, located one above the other, an insulating film located between the areas of the drain and the source, channel region contained in the semiconductor connecting region of the source with the drain region, the gate electrode to create an electric field in the channel region, a region for storing electric charges, separated from the channel region by a potential barrier, in which is stored a specified large number of memory elements when changing the conductivity of the specified channel region in accordance with the number of charges, while the semiconductor storage device also contains a large the number of peripheral circuits, designed for transmission of signals to the information and vocabulary tires and contains the amplifier readout register to save the backgrounds of the information of the memory elements, the register that holds the flag which indicates the end of recording during the test, and the scheme that after the write operation compares the value read from the memory cell with the value recorded by the box in the end of the record, and rewrites a value that indicates the box, and at least part of these peripheral circuits is a CMOS elements, consisting of the n-channel MOS transistors and p-channel MOSFETs.

2. Semiconductor memory device having a multi-layered structure and containing the first local information bus, the first intermediate layer over the first local data bus, the bus source above the first intermediate layer, second intermediate layer over the bus source, the second local information bus over the second intermediate layer, and the first and second intermediate layers are insulating films, the first channel region connected to the bus of the source and the first local data bus and located on the side of the multilayer structure, and the second channel region connected with the second bus source and a second local data bus and located on the side surface of the multilayered structure over the first channel region, the grip area of the electric charge, surrounded by potential baranami located in close proximity to the first and second channel regions or within the channel region, located on the side of the multilayer structure, vocabulary bus that is connected to the channel region through an insulating film shutter, and two semiconductor memory element located above the points of intersection and under the points of intersection of the first and second local information tire and dictionary tires, in which information is stored by changing the threshold voltage of the semiconductor due to controlled changes in the number of carriers in the capture area of the electric charge, while the semiconductor memory elements combined sequentially in a matrix of a large amount of local information tire and dictionary tires, and the first and second local data bus connected to the same common data bus via transistors sample.

3. Semiconductor storage device according to claim 2, in which the sampling transistors are controlled individually electrodes of the shutter.

4. Semiconductor storage device according to claim 2, in which General information tire covers these first and second local data bus.

5. Semiconductor storage device according to claim 2, in which the contact hole connecting the common information bus with sampling transistor is located between the contact holes connecting the first and second l is the local data bus with the transistor of the selection.

6. Semiconductor storage device according to claim 2, in which the first and second local data bus connected to the same common data bus through a separate MOSFET selection, have a separate structure of the diffusion layer of the transistor of the sample and in which a contact hole for a common data bus and a separate plot of the diffusion layer passes at least one local information bus.

7. Semiconductor storage device according to claim 2, having the auxiliary information bus, which is made of the same material as the main local information bus is parallel to it, is essentially equal to it's width and is not used for information storage.

8. Semiconductor storage device according to claim 2, having an insulating film made on the inner wall of the contact hole bus source or a local data bus.

9. Semiconductor storage device according to claim 2, in which the semiconductor material is deposited on the side surface of the insulating film that separates the bus source from the local data bus is oxidized insulating film.

10. Semiconductor storage device according to claim 2, which has a semiconductor element made the and the surface of the semiconductor substrate, and in which the contact hole overlaps the gate electrode or the diffusion layer of the semiconductor element is performed on the semiconductor substrate, and at least the bus source or local information bus.

11. Semiconductor storage device according to claim 2, in which an auxiliary structure that is not used as a local data bus, but made of the same material as the local information bus, and the structure in which the contact hole dictionary tire is located on the auxiliary structure.

12. Semiconductor storage device according to claim 2, in which an auxiliary structure that is not used as a local data bus, but made of the same material as the local information bus, and a semiconductor film that overlaps by 1 μm or more in the longitudinal direction of the side insulating film supporting structure.

13. Semiconductor storage device according to claim 2, in which the bus from the power source, whereby the voltage supplied to the circuit reading data from the semiconductor memory element runs parallel to the dictionary the bus.

14. Semiconductor storage device according to claim 2, in which as a General informational Shi is s used for the second layer from the bottom or the top layer is made of metal interconnects.

15. Semiconductor storage device according to claim 2, which includes a readout circuit information of the semiconductor memory element which is connected to the common data bus through a layer made of metal interconnects below the common information bus.

16. Semiconductor storage device according to claim 2, in which local information bus connected to a common data bus MOS transistor.

17. Semiconductor storage device according to claim 2, in which the first and second local data bus connected to the same shared data bus separate MOS transistors samples that have different gate electrodes, with the input of the first and second local information of the tire through the respective gate electrodes are served vzaimodeisvie signals.

18. Semiconductor storage device according to claim 2, having a control device that is designed to perform the first operation of erasing information stored in the semiconductor memory element, the second operation is repeated deletion, remaining in this semiconductor memory element by the incomplete erasing of information during the first erase operation, the third operation recording information of 0 or 1 in this semiconductor memory element, the fourth operation and re-write information in this semiconductor memory element with incomplete information is recorded during the third operation and the fifth read operation information, stored in the semiconductor memory element, and having a register for storing information of 0 or 1 in the outer part of the semiconductor device, and a device for storage of the list of semiconductor memory elements, in which the erasing of the information has been fully implemented, or list of semiconductor memory elements, in which the erasing data after the first erase operation was performed incompletely, the device for storing data stored in the semiconductor memory element during a third write operation, and a device for storage of the list of semiconductor memory elements, in which the erasing of the information was made fully or list of semiconductor memory elements, in which after the third operation wipe was performed incompletely, and the device that uses this register for storing data read from the semiconductor memory element during the fifth read operations.

19. Semiconductor storage device according to claim 2, which performs a first write operation in the semiconductor element information 0 or 1, the second operation record information in the semiconductor element with an incomplete recording of information during the first write operation, and which has a register for storing the list of semiconductor elements p is mate, in which information was recorded completely, or list of semiconductor memory elements, in which information has been recorded incompletely after the first write operation, and which has a device for re-entry register values in the semiconductor memory elements, in which the information was recorded.

20. Semiconductor storage device according to claim 2, in which the device to overwrite the values of the register is performed in the case where information indicating that a complete record of information, is a high-level voltage, consists of one p-channel MOS transistor and one n-channel MOS transistor in which the source of n-channel MOS transistor is connected to a source of high voltage level, the drain of the p-channel MOS transistor is connected to the drain of n-channel MOS transistor, evidence of the full recording information is input to the gate of n-channel The MOS transistor, the drain of n-channel MOS transistor is connected to the input of the register storing information indicating that the write data has been fully implemented, and the control signal is input to the gate of the p-channel MOSFET.

21. Semiconductor storage device according to claim 2, in which the device to overwrite the values of the register, running the th in that case, when evidence of a complete recording information is a low level voltage, consists of one n-channel MOS transistor and one p-channel MOS transistor in which the source of the p-channel MOS transistor is connected to a source of low voltage level, the drain of n-channel MOS transistor is connected to the drain of the p-channel MOS transistor, evidence of the full recording information is input to the gate of the p-channel MOS transistor, the drain of the p-channel MOS transistor is connected to the input of the register, which stores information, showing that the account information has been fully implemented, and the control signal is input to the gate of n-channel MOS transistor.

22. Semiconductor memory device is performed on the substrate and composed of a large number of memory cells for storing data by accumulating or discharging electric charges and in which a group of two memory cells located vertically on the substrate, and these memory cells are properly connected to the information tires and dictionary tires, and in which selecting at least one of all memory cells of the address signal is fed to the input of predestinator address decoder local data bus, and the signal from pride is imator address selects one word bus, on a signal from the decoder to the local data bus is selected information bus, and when the sample is suitable for use of information the information bus for a group of two vertically arranged memory cells in cases erase selected simultaneously, and reading are selected separately.

23. Semiconductor memory device containing a large number of memory elements, each of which contains a region of the source and drain region, channel region, contained in the semiconductor connecting region of origin and region of the drain region for storing electric charges, separated from the channel region by a potential barrier, in which is stored a specified large number of memory elements when changing the conductivity of the specified channel region in accordance with the number of charges, while the semiconductor storage device also contains a large number of local information of tyres and General information bus, and a large number of memory elements includes spaced one above the other memory elements specified the local data bus includes spaced one above the other and separated by an insulating film local data line, and the drain region or the source of the memory element, located in Rheem layer of memory elements, connected to the local data bus, located in the specified upper layer, and the drain region or the source of the memory element located in the lower layer of the memory elements that are connected to local data bus specified lower layer, these local data bus these layers are connected to a common data bus via the MOS transistors of the sample having different length electrodes of the shutter.

24. A semiconductor storage device that contains the blocks of memory cells, each of which consists of a large number of memory cells located at intersections of the intersecting dictionary and tire information tire, and peripheral circuits, the input signals to the vocabulary and information to the tires, and the memory cell consists of a substrate, the first multilayer region located on the substrate, the second multilayer region above the first region, an insulating film located between the first and second regions, a channel region connecting with each other of the first and second region, the gate electrode that generates an electric field in the channel region, and the capture area of the electric charge, the peripheral circuit includes a read amplifier, a register for storing information of the memory elements, the register that holds the box shows the Mering stop recording when you check it, and the scheme that after the write operation compares the value read from the memory cell with the value recorded by the box in the end of the record, and rewrites a value that indicates the box, and the storage charge is carried out by changing the threshold voltage of a semiconductor controlled change in the number of charge carriers in the capture area of the electric charge, and at least part of the peripheral circuits are complementary MOS structure consisting of the n-channel MOS transistors and p-channel MOSFETs.

25. The semiconductor device according to paragraph 24, in which the grip area of the electric charge formed by fine particles of metal or semiconductor material with an average size of 10 nm.

26. Semiconductor memory element according to paragraph 24, in which the channel region is a thin layer of semiconductor material, the average thickness of which does not exceed 10 nm.

27. Semiconductor storage device according to paragraph 24, in which the channel region performs the function of the capture area of the electric charge.

28. Semiconductor storage device according to paragraph 24, in which at least the first or second region formed in the substrate.

29. Semiconductor memory element according to paragraph 24, in which the first region or the drain region is made of polik is istoricheskogo silicon.

30. Semiconductor memory element according to paragraph 24, in which the minimum value of the effective width of the channel region does not exceed 20 nm.

31. Semiconductor memory element according to paragraph 24, in which the unit consisting of a large number of memory cells is a multi-layered structure of two or more layers.

32. Semiconductor storage device according p, in which two memory cells of the first region, located one above the other, connected to the same data bus via a corresponding transistor of the selection.

33. Semiconductor storage device according to paragraph 24, which has a control circuit that performs three operations, including the first operation consists in applying a voltage of a write to the memory cell, the second operation consists in reading the information stored in the memory cell after performing the first operation and the third operation consists in re-applying to the memory cell voltage recordings in that case, if the second operation is determined that the information in the memory cell was not recorded in full.

34. Semiconductor storage device according p with the circuit information storage that stores written in the memory cell information (or list of elements for recording information 0 or 1) in the outer part of the cell p is mate, when this write operation is performed again, if it is determined that the information stored in the storage schema, after voltage application record does not match the status information of the semiconductor memory element.

35. Semiconductor storage device according p in which by supplying the memory cell different stress value entries in this cell can store two or more bits of information.



 

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FIELD: semiconductor memory devices.

SUBSTANCE: device has a lot of memory elements, each of which contains input and output areas, isolating film, channel area, shutter electrode, area for storing electric charges, device also contains large number of periphery circuits, containing reading amplifier, register for storing recorded data of memory elements, register, which preserves the flag, indicating end of record during its check, and circuit, which after recording operation compares value, read from memory cell, to value, fixed by flag at the end of record, and overwrites value indicated by the flag.

EFFECT: higher reliability of operation.

5 cl, 71 dwg

FIELD: data carriers.

SUBSTANCE: device for determining logical state of selected memory cells in memory device with passive matrix addressing is made with possible connection to ferroelectric memory device or forming its portion and contains reading amplifying contours, synchronous amplifier, combined source of shift voltage and signal, active control line driver, multiplexer, a set of routers. Other variant of aforementioned device is additionally equipped with second set of routers. Method describes operation of aforementioned devices.

EFFECT: higher efficiency, broader functional capabilities.

3 cl, 12 dwg

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