Flip-flop device


H03K3/286 - PULSE TECHNIQUE (measuring pulse characteristics G01R; mechanical counters having an electrical input G06M; information storage devices in general G11; sample-and-hold arrangements in electric analogue stores G11C0027020000; construction of switches involving contact making and breaking for generation of pulses, e.g. by using a moving magnet, H01H; static conversion of electric power H02M; generation of oscillations by circuits employing active elements which operate in a non-switching manner H03B; modulating sinusoidal oscillations with pulses H03C, H04L; discriminator circuits involving pulse counting H03D; automatic control of generators H03L; starting, synchronisation, or stabilisation of generators where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
H03K3/037 - PULSE TECHNIQUE (measuring pulse characteristics G01R; mechanical counters having an electrical input G06M; information storage devices in general G11; sample-and-hold arrangements in electric analogue stores G11C0027020000; construction of switches involving contact making and breaking for generation of pulses, e.g. by using a moving magnet, H01H; static conversion of electric power H02M; generation of oscillations by circuits employing active elements which operate in a non-switching manner H03B; modulating sinusoidal oscillations with pulses H03C, H04L; discriminator circuits involving pulse counting H03D; automatic control of generators H03L; starting, synchronisation, or stabilisation of generators where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flops 3, 16, EXCLUSIVE OR gates 1, 2, NAND gates 5, 6, NOR gates 10, 11, resistors 4, 7, 12, 13, capacitors 14, 15, memory items 8, 9 built around magnetic core with rectangular hysteresis loop and single center-tapped coil, input bus 21, and common bus 22. Combining read and write coils of memory items 8, 9 makes it possible to increase turn number in read and write coils by 1.5 times, in each of half-coils of memory items 8 and 9, which reduces magnetizing current through cores of memory items 8 and 9 approximately by 1.5 times due to enhancing ratings of limiting resistors 4 and 7.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

 

The invention relates to a pulse technique and can be used in computer equipment and control systems.

Known trigger device (see USSR author's certificate No. 1753919 from 05.10.90, MKI: N 03 To 3/037 "Trigger device", the authors Lbero, Geesken, publ. 10.09.97, bull. No. 25), containing the first and second memory elements, magnetic cores, the outputs of the windings reading which is connected with the common bus, the input windings record connected respectively with direct and inverse outputs of the EXCLUSIVE OR element, the first and the second input of which is connected to the input bus and the output of the RS - flip-flop, respectively, the inputs set and reset which are connected respectively through first and second resistors to the input windings of the read first and second memory elements, respectively. The first control unit is connected to the input bus, the second and third inputs of the control unit are connected respectively with direct and inverse outputs of the EXCLUSIVE OR element, and first and second outputs of the control unit respectively through the third and fourth resistors connected to the outputs of the windings recording respectively the first and second memory elements.

The disadvantage of this trigger device is relatively large current consumption from the power source.

Known trigger of mouth is austo (see RF patent №2106742 from 16.08.95, MKI: N 03 To 3/286 "Trigger device", the authors Eyiah, Geesken, publ. 10.03.98, bull. No. 7), which is the closest to the technical nature of the claimed object and selected as a prototype, containing RS-trigger inputs set and reset which are connected with the first pins of the first and second resistors, respectively, and respectively through the first and second capacitors with a common bus, and direct and inverted outputs connected to first inputs respectively of the first and second XOR, second input which is connected to the input bus trigger device, and outputs connected to inputs of the windings recording respectively the first and second memory elements, magnetic cores, an input winding reader which is connected with a shared bus, the first and second elements, the third and fourth XOR, third, fourth, fifth and sixth resistors. RS-trigger executed on the elements. The outputs of the first and second XOR is connected with the first inputs respectively of the third and fourth XOR the outputs are after, respectively, the third and fourth resistors connected to the outputs of the windings recording respectively the first and second memory elements, the outputs of the windings reading through which respectively the heels of the fifth and sixth resistors connected to the first inputs respectively of the first and second elements AND IS NOT, the outputs of which are connected with the second pins respectively of the second and first resistors and second inputs, respectively, the third and fourth XOR. The second inputs of the first and second elements AND IS NOT incorporated and is connected to the input bus trigger device.

The disadvantage of the prototype is relatively large current consumption from the power source.

The problem solved by the claimed invention is to reduce current consumption from the power source.

This technical result is achieved in that the trigger device comprises a first RS-flip-flop, the inputs set and reset which are connected respectively with the first findings of the first and second resistors and after, respectively, the first and second capacitors with a common bus, and direct and inverted outputs connected to first inputs respectively of the first and second XOR, the second inputs are combined and connected to the input bus, the first and second memory elements on magnetic cores with rectangular hysteresis loop, the first and second elements, the first inputs of which are connected with the first pins respectively of the third and fourth the resistors. What is new is the fact that additionally introduced the second RS-flip-flop, the first and second elements OR NOT, the outputs of which are connected respectively the state with the second pins of the first and second resistors, the first and second memory elements on magnetic cores with rectangular hysteresis loop contain one winding, the midpoints of which are connected with the second pins, respectively, the third and fourth resistors, the outputs of the windings of the first and second memory elements are connected respectively to the first inputs of the first and second elements OR NOT and with the second inputs of the first and second elements AND IS NOT, respectively, the outputs of which are connected with inputs of the windings of the second and first memory elements, respectively, the inputs set and reset of the second RS-flip-flop are connected respectively to the outputs of the second and the first XOR, and direct and inverted outputs are connected with the first inputs of the first and second elements AND IS NOT, respectively, the second inputs of the first and second elements OR IS NOT connected to the input bus, the first and second RS-trigger executed on the items OR NOT.

This set of essential features can reduce the current consumption of the trigger device from the power source due to the possibility of reducing the bias current of the cores by increasing the number of turns in the windings write memory elements.

The drawing shows a circuit diagram of a trigger device. The trigger device includes items 1 and 2 XOR, RS-TRIG is a career 3 and 16, the resistors 4, 7, 12 and 13, the elements 5 and 6 AND IS NOT, items 8 and 9 memory on magnetic cores with rectangular hysteresis loop with a single winding having a tap away from the midpoint, the elements 10 and 11 OR NOT, the capacitors 14 and 15, the input bus 21 and bus 22. RS-trigger 3 contains elements 17 and 18 OR NOT, the first inputs of the elements 17 and 18, OR are NOT, respectively, the reset inputs and an RS-flip-flop 3, the outputs of the elements 17 and 18 OR NOT are respectively the direct and inverse outputs RS-flip-flop 3, the second inputs of the elements 17 and 18 OR IS NOT connected respectively to the outputs of the elements 18 and 17 OR NOT. RS-trigger 16 includes items 19 and 20 OR NOT, the first inputs of the elements 19 and 20 OR NOT are respectively reset inputs and an RS-flip-flop 16, the outputs of the elements 19 and 20 OR NOT are respectively the direct and inverse outputs of the RS flip-flop 16, the second inputs of the elements 19 and 20, OR IS NOT connected respectively to the outputs of the elements 20 and 19 OR NOT. The outputs of the elements 1 and 2 XOR respectively connected to the reset inputs and an RS-flip-flop 3, and the outlet of which is connected to the first input element 5 AND NOT through the resistor 4 is the mid-point of the winding element 8 to the memory, the input winding of which is connected with the output element 5 AND IS NOT, and the output winding element 8 memory connected to the first input element 10 OR NOT and with the second input element 6 is NOT. Inverted output of the RS flip-flop 3 is connected to the first input element 6 AND NOT through the resistor 7 to the mid-point of the winding element 9 to the memory, the input winding of which is connected with the output element 6 AND IS NOT, and the output winding of the memory element 9 connected to the first input element 11 OR NOT and with the second input element 5. The reset input of RS flip-flop 16 through a resistor 12 is connected to the output of the element 10 OR NOT, and through a capacitor 14 to the common bus 22. The input of the RS flip-flop 16 through a resistor 13 is connected to the output element 11 OR NOT, and through a capacitor 15 to the common bus 22. Direct and inverted outputs of the RS flip-flop 16 is connected respectively to the first inputs of the elements 1 and 2, EXCLUSIVE OR, and the second inputs are combined and connected to the second inputs of the elements 10 and 11 OR NOT and with the input bus 21.

The trigger device operates as follows. At power-up trigger device will be set to the state corresponding to the state of the elements 8, 9 memory, which they acquired in the previous cycle. Consider the case when the elements 8 and 9 memory were magnetized in the state of logical "0"which corresponds to the direction of current flow in the winding element 8 memory from the midpoint to its input, and in the winding element 9 memory - from the entrance to the middle point (the input windings are marked on the drawing by an asterisk ( * ). In the absence of the clock signal on the input Shi is e 21 is a signal of logical "0". If, for example, after power RS-trigger 16 is established in the zero state, in which its direct output (Q) signal is a logical "0"at its inverted output (- the logical signal "1", the outputs of the elements 1 and 2 EXCLUSIVE OR will be, respectively, the signals of logical "0" and logical "1", under the action of which is to direct the output (Q) of the RS-flip-flop 3 and the output element 6 AND are signals of logical "1", and the inverted output () and the output element 5 AND IS NOT a signal of logical "0". The direction of the current flowing through the coil of the element 8 memory coincides with the direction of its magnetization, in this case, the output winding element 8 memory occurs a short pulse interference of positive polarity relative to a common bus 22 that is associated with nephrourology of the hysteresis loop of the core. The specified pulse interference will not affect the state of the RS-flip-flop 16 as it is determined by the voltage on the charging capacitor of the integrating RC circuit consisting of resistor 12 and capacitor 14. Next, the output element 8 memory and the output element 11 OR are the signals of logical "0"and the output of the memory element 9 and the output of the element 10 OR-NOT - signals of logical "1", there will be a charge of the capacitor 14, the capacitor 15 will save time is agendae state, RS-trigger 16 retains its zero state, thus, trigger the device will acquire a steady state logical "0".

If after power RS-trigger 16 has been established in one state, in which its direct (Q) output signal of logical "1", and the inverted output () signal is a logical "0", the outputs of the elements 1 and 2 EXCLUSIVE OR will be, respectively, the signals of logic "1" and logical "0", under the action of which is to direct the output (Q) of the RS-flip-flop 3 and the output element 6 AND IS NOT located signal of logical "0", and the inverted output () and the output element 5 AND a-NOT - a logical signal "1". In the windings of the elements 8 and 9 memory will flow currents whose direction does not coincide with the direction of magnetization of the cores of the memory elements 8 and 9, in this case, initially the output winding element 8 memory will be generated signal is a logical "0"and the output winding of the memory element 9 is formed a signal of logical "1". This is because the resistance values of the resistors 4 and 7 are selected so that the magnetization switching of cores in Polubotko memory elements arose the voltage pulse amplitude E/2 where E is the supply voltage of the circuit. The logical signal "0" from the output winding 8 of the memory switch elements 6 And The E and 10 OR NOT in the state of logical "1", the winding element 9 memory will be de-energized and its output is supported by the logical signal "1". Under the action of the output signal of the element 10 OR NOT begins the charging process of the capacitor 14, the capacitor 15 also maintains a discharged condition. After the charge of the capacitor 14 to the level of logical "1" will switch RS-flip-flop 16 in the state of logical "0" and then trigger the device will fully restore its state in accordance with the States of the elements 8 and 9 of the memory.

To switch the trigger device on the input bus 21 is supplied clock signal with a logical level "1". In this case, if the trigger device is in the state of logical "0", the outputs of the elements 1 and 2 XOR are respectively the signals of logic "1" and logical "0", the outputs of the elements 10 AND 11 OR-NOT are all signals of logical "0", the capacitor 14 begins to run, but this does not affect the output signals of the RS-flip-flop 16, he retains the zero state. Under the action of the output signal of element 1 EXCLUSIVE OR switch RS-flip-flop 3 and the direct output and the output of the element 6 OR NOT signals are formed logical "0", and the inverted output of the RS flip-flop 3 and the output unit 5 OR NOT signals are formed logical "1". Then alternating magnetization of the cores e the elements 8 and 9 memory status, opposite to that which they had in the previous step, and the process state changes of items 8 and 9 of the memory sequentially, as in the initial moment of the magnetization reversal element 8 memory output windings is formed by a logical signal of "0", which returns the element 6 AND IS NOT in the state of logical "1" and the element 9 memory retains the same state as the current in the winding is missing. After the magnetization reversal element 8 memory output windings is formed by a logical signal "1"which gives permission to alternating magnetization of the memory element 9. By the end of the clock signal on the input bus 21 alternating magnetization of the core elements 8 and 9 of the memory ends and the output winding element 8 memory present signal is logical "1", the output winding element 9 memory signal is a logical "0". These signals through the elements 10 and 11 is not transmitted, because the status of the latter is a clock signal on the input bus 21, the condenser 14 by this time completely discharged. After the expiration of the clock signal at the output of the element 10 OR NOT is set to a logical signal "0"at the output of the element 11 OR-NOT - a logical signal "1", starts the charge of the capacitor 15. The outputs of the elements 1 and 2 XOR at this time are respectively signals to logical 0" and logical "1", RS-trigger 3 is returned to its original condition at the output of the element 6 AND IS NOT set to a logical signal "1", the output winding of the memory element 9 is formed a signal of logical "0", under which the output element 5 AND IS NOT set to a logical signal "1", the winding element 8 memory de-energized and its output is a logic signal "1". The output States of the elements 10 and 11, OR NOT being saved. After the charge of the capacitor 15 (the time constant of the integrating circuits the resistor 12, capacitor 14 and resistor 13, the capacitor 15 is determined on the basis of suppression of short noise and interference signals and a lot less time of magnetization reversal of items 8, 9 memory) will switch RS-flip-flop 16, with direct output will be a logical signal "1", and the inverse signal of a logical "0". Next on the output of the element 1 EXCLUSIVE OR, to invert the output of the RS flip-flop 3 and the output element 5 AND NO signals are logic "1", and the output of the EXCLUSIVE OR element 2, to direct the output of the RS flip-flop 3 and the output element 6 AND IS NOT installed signals of logical "0". In the windings of the elements 8 and 9 memory will flow currents, the direction of which coincides with the direction of magnetization of the cores. In the winding element 8 memory current will flow from the entrance to the middle point, in the winding element 9 memory current Patchett mid-point to the entrance. Thus, the trigger device will have a new steady state logical "1". Similarly switches the trigger device from the state of logical "1" state to a logical "0".

Restoring the state of the trigger device, if it fails under the influence of the distortion in the storage of information is performed in accordance with the state of the elements 8 and 9 memory similar to how it is recovered by the power supply.

Normal operation of the trigger device is provided with equal number of turns in Polubotko elements 8 and 9, a memory, and one Polubotko (between the entrance and the middle point of the winding) by analogy with the prototype performs the role of a winding of a record, and both are connected in series Polubotko perform the role of windings reading. In the schema of the prototype for its normal functioning of the winding of the reader should contain approximately 2 times more turns than the winding of the recording, therefore, in the inventive device, taking into account the overlapping of the windings of the read and write at the selected sizes of cores it is possible to increase 1.5 times the number of turns in the windings of the read and write (in each of Polubotok elements 8 and 9 memory), and then decrease to about 1.5 times the magnetizing current of the core e is the memory elements by increasing resistance limiting resistors 4 and 7. As a result, reduces the current consumption of the trigger device from the power source in static and dynamic modes.

Thus, as follows from the description of work, declare the trigger device has a lower current consumption from the power source.

Testing laboratory layout trigger device confirmed the feasibility and practical value of the claimed device.

The trigger device containing the first RS-flip-flop, the inputs set and reset which are connected respectively with the first findings of the first and second resistors and after, respectively, the first and second capacitors with a common bus, and direct and inverted outputs connected to first inputs respectively of the first and second XOR, the second inputs are combined and connected to the input bus, the first and second memory elements on magnetic cores with rectangular hysteresis loop, the first and second elements, the first inputs of which are connected with the first pins respectively of the third and fourth resistors, wherein the introduced the second RS-flip-flop, the first and second elements OR NOT, the outputs of which are connected respectively with the second pins of the first and second resistors, the first and second memory elements on magnetic cores with rectangular loop is the hysteresis contain one winding, midpoints are connected with the second pins, respectively, the third and fourth resistors, the outputs of the windings of the first and second memory elements are connected respectively to the first inputs of the first and second elements OR NOT and with the second inputs of the first and second elements AND IS NOT, respectively, the outputs of which are connected with inputs of the windings of the second and first memory elements, respectively, the inputs set and reset of the second RS-flip-flop are connected respectively to the outputs of the second and the first XOR, and direct and inverted outputs connected to first inputs of the first and second elements AND IS NOT, respectively, the second inputs of the first and second items OR IS NOT connected to the input bus, the first and second RS-trigger executed on the items OR NOT.



 

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