Flip-flop device


H03K3/286 - PULSE TECHNIQUE (measuring pulse characteristics G01R; mechanical counters having an electrical input G06M; information storage devices in general G11; sample-and-hold arrangements in electric analogue stores G11C0027020000; construction of switches involving contact making and breaking for generation of pulses, e.g. by using a moving magnet, H01H; static conversion of electric power H02M; generation of oscillations by circuits employing active elements which operate in a non-switching manner H03B; modulating sinusoidal oscillations with pulses H03C, H04L; discriminator circuits involving pulse counting H03D; automatic control of generators H03L; starting, synchronisation, or stabilisation of generators where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
H03K3/037 - PULSE TECHNIQUE (measuring pulse characteristics G01R; mechanical counters having an electrical input G06M; information storage devices in general G11; sample-and-hold arrangements in electric analogue stores G11C0027020000; construction of switches involving contact making and breaking for generation of pulses, e.g. by using a moving magnet, H01H; static conversion of electric power H02M; generation of oscillations by circuits employing active elements which operate in a non-switching manner H03B; modulating sinusoidal oscillations with pulses H03C, H04L; discriminator circuits involving pulse counting H03D; automatic control of generators H03L; starting, synchronisation, or stabilisation of generators where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flop 1, EXCLUSIVE OR gates 2,3, NOR gates 4, 5, inverters 6, 7, 8, diodes 15, 16, resistors 9 through 12, capacitors 13, 14, memory items 17, 18 built around magnetic cores with rectangular hysteresis loop and single coil, input bus 19, and common bus 20. Combining write and read coils of memory items 17 and 18 makes it possible to increase coil number of write and read coils by 1.5 times, in each of half-coils of memory items 17 and 18, which reduces magnetizing current through cores of memory items 17 and 18 by approximately 1.5 times due to enhancing ratings of limiting resistors 11 and 12.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

 

The invention relates to a pulse technique and can be used in computer equipment and control systems.

Known trigger device (see USSR author's certificate No. 1753919 from 05.10.90, MKI N 03 To 3/037 "Trigger device", the authors Lbero, Geesken, publ. 10.09.97, bull. No. 25), containing the first and second memory elements, magnetic cores, the outputs of the windings reading which is connected with the common bus, the input windings record connected respectively with direct and inverse outputs of the element "Exclusive OR", the first and the second input of which is connected to the input bus and the output of the RS-flip-flop, respectively, the inputs set and reset which are connected respectively through first and second resistors to the input windings of the read first and second memory elements, respectively. The first control unit is connected to the input bus, the second and third inputs of the control unit are connected respectively with direct and inverse outputs of the element "Exclusive OR", and the first and second outputs of the control unit respectively through the third and fourth resistors connected to the outputs of the windings recording respectively the first and second memory elements.

The disadvantage of this trigger device is relatively large current consumption from the power source.

Known trigger condition is the device (see RF patent №2106742 from 16.08.95, MKI N 03 To 3/286 "Trigger device", the authors Eyiah, Geesken, publ. 10.03.98, bull. No. 7), which is the closest to the technical nature of the claimed object and selected as a prototype, containing RS-trigger inputs set and reset which are connected with the first pins of the first and second resistors, respectively, and respectively through the first and second capacitors with a common bus, and direct and inverted outputs connected to first inputs respectively of the first and second elements of the "Exclusive OR", second input which is connected to the input bus trigger device, and outputs connected to inputs of the windings recording respectively the first and second memory elements, magnetic cores, an input winding of reading which are connected to a common bus, the first and second elements, the third and fourth elements of the "Exclusive OR", third, fourth, fifth and sixth resistors. RS-trigger executed on the elements. The outputs of the first and second elements of the "Exclusive OR" is connected with the first inputs respectively of the third and fourth elements of the "Exclusive OR", the outputs of which respectively through third and fourth resistors connected to the outputs of the windings recording respectively the first and second memory elements, the outputs of the windings reading through sootvetstvenno and sixth resistors connected to the first inputs respectively of the first and second elements AND IS NOT, the outputs of which are connected with the second pins respectively of the second and first resistors and second inputs, respectively, the third and fourth elements of the "Exclusive OR". The second inputs of the first and second elements AND IS NOT incorporated and is connected to the input bus trigger device.

The disadvantage of the prototype is relatively large current consumption from the power source.

The problem solved by the claimed invention is to reduce current consumption from the power source.

This technical result is achieved in that the trigger device containing the RS-flip-flop, the first and second elements of the "Exclusive OR", the first inputs are combined and connected to the input bus, the first and second memory elements on magnetic cores with rectangular hysteresis loop (BCP), the first and second resistors, the first conclusions which are connected to a common bus through the first and second capacitors, respectively, the third and fourth resistors, what is new is the introduction of the first and second elements OR NOT, the first, second and third inverters, first and second diodes, the first and a second memory elements on magnetic cores with BCPs contain one winding, the midpoints of which are connected with the cathodes of the first and second diodes, respectively, and respectively through the third and fourth resistors is uedineny with the outputs of the first and second inverters, respectively, the inputs of which are connected with inputs of the windings of the first and second memory elements, respectively, and respectively direct and inverse outputs RS-trigger, and reset inputs of the installation which is connected to the outputs of the first and second elements of the "Exclusive OR", respectively, the second inputs of which are connected with the first pins of the first and second resistors, respectively, the latter findings are connected to the outputs of the first and second elements OR NOT, respectively, the first inputs of which are connected to the outputs of the windings of the second and first memory elements, respectively, and second inputs are combined and connected to the output of the third inverter, whose input is connected to the input bus RS-trigger executed on the items OR NOT.

This set of essential features can reduce the current consumption of the trigger device from the power source due to the possibility of reducing the bias current of the core by increasing the number of turns in the windings account cores.

The drawing shows a circuit diagram of a trigger device. The trigger device has an RS-trigger 1, items 2 and 3 of the "Exclusive OR", items 4 and 5 OR NOT, the inverters 6, 7 and 8, resistors 9, 10, 11 and 12, the capacitors 13 and 14, the diodes 15 and 16, the elements 17 and 18 memory on magnetic cores with BCPs with one winding having features is from the mid-point, input bus 19 bus 20. The first inputs of the elements 2 and 3 "Exclusive OR" of the joint and is connected to the input bus 19 and to the input of the inverter 8. The second input element 2 "Exclusive OR" through the condenser 13 is connected to the common bus 20 and through a resistor 9 with the output element 4 OR NOT, the first input connected to the output winding of the memory element 18. The second input element 3 "Exclusive OR" through the condenser 14 is connected to the common bus 20 and through resistor 10 with the output element 5 OR NOT, the first input connected to the end of the winding of the memory element 17. The second inputs of the elements 4 and 5 OR are NOT integrated and connected to the output of the inverter 8. The outputs of the elements 2 and 3 are connected respectively to the reset inputs and an RS-flip-flop 1. Direct RS-flip-flop 1 is connected to the input of the inverter 6, the anode of the diode 15 and to the input winding of the memory element 17. Inverted output of the RS flip-flop 1 is connected to the input of the inverter 7, the anode of diode 16 and to the input winding of the memory element 18. The output of the inverter 6 through the resistor 11 is connected to the cathode of the diode 15 and to the middle point of the winding of the memory element 17. The output of the inverter 7 through a resistor 12 is connected to the cathode of the diode 12 and to the middle point of the winding element 18 of the memory. RS-trigger 1 contains elements 21 and 22 OR NOT, the first inputs of the elements 21 and 22 are respectively reset inputs and an RS-flip-flop 1, the outputs of the elements 21 and 22 having Auda respectively the direct and inverse outputs RS-flip-flop 1, the second inputs of the elements 21 and 22 are connected respectively to the outputs of the elements 22 and 21.

The trigger device operates as follows. At power-up (power circuit logic elements 2, 3, 4, 5, 6, 7, 8, 21, 22 to simplify the drawing not shown), the trigger device will be set to the state corresponding to the state of the elements 17, 18 memory, which they acquired in the previous cycle. Consider the case where the elements 17 and 18 memory were magnetized in the state "log.0"that corresponds to the direction of current flow in the winding of the memory element 17 from the midpoint to its input, and the coil element 18 memory - from the entrance to the middle point (the input windings on the drawing marked with( *)). If after power RS-trigger was set to the zero state, in which its direct output (Q) signal "log.0"on its inverted output (- signal "log.1", the outputs of the inverters 6 and 7 signals "log.1" and "log.0" respectively. The direction of the current flowing through the coil of the memory element 17, which coincides with the direction of its magnetization, in this case, the output winding element 17 memory occurs a short pulse interference of positive polarity relative to a common bus 20 that is associated with nephrourology of the hysteresis loop of the core. The diode 15 is closed to zero (pulse - negative) voltage is eat, present on half of the windings of the memory element 17. In the absence of the clock signal on the input bus 19 is the signal "log.1", the inverter output 8 signal "log.0", so this impulse noise appears on the output element 5 OR NOT, but on the input element 3 "Exclusive OR" will not be impacted, as the latter is determined by the voltage on the charging capacitor of the integrating RC circuit consisting of resistor 10 and capacitor 14. When the device is switched on until the voltage on the capacitor 14 is not increased to the level of "log.1", the output element 3 "Exclusive OR", and hence on the input set (S input) RS-flip-flop 1, a short time will be the signal "log.1". This will cause intermittent appearance of the signal "log.0" inverse output () RS-flip-flop 1 and the signal "log.1" at the output of the inverter 7, the winding current of the memory element 18 changes direction at the output winding of the memory element 18 will receive a pulse of positive polarity, confirming discharged condition of the capacitor 13; the output element 2 "Exclusive OR" and the reset input (R input) RS-flip-flop 1 is the signal "log.1"confirming signal "log.0" direct (Q) output RS-flip-flop 1. After the charge of the capacitor 14 at the output of the element 3 and the input set (S input) RS-trigger 1 set signal "log.0" -output RS-trigger 1 signal "log.1", the inverter output 7 signal"log.0". As a result, after the end of the transient processes in the memory elements 17 and 18, the direction of the current flowing through the coil of the memory element 18, also coincides with the direction of its magnetization with the difference that the voltage on Polubotko element 18 of the memory, that is, between the entrance and the middle point of the winding is shunted open diode 16. Therefore, the amplitude of the impulse noise on the output winding of the memory element 18 relative to its input will not exceed the value 2 Udwhere Ud- the voltage drop across the open diode 16 (with equal number of turns in Polubotko elements 17 and 18 of the memory, that is, with equal number of turns between the entrance and the middle point of the winding and between the middle point and the output winding). The output winding of the memory element 18 relative to the common bus 20 will set the signal "log.1", the output element 4 - signal "log.0". The capacitor 13 is supported in a rarefied state at the output of the element 2 and the reset input of RS flip-flop is the signal "log.1". Thus, the transients after switching on the supply voltage RS-flip-flop will remain in the zero state.

If after power RS-trigger has been established in one state, in which its direct (Q) output signal "low", in the windings of the elements 17 and 18 is Amati currents will flow, the direction which does not coincide with the direction of magnetization of the cores of the memory elements 17 and 18, in this case, initially the voltage at the output winding of the memory element 17, taking into account the shunting effect of the diode 15, is equal to E-2Udwhere E is the supply voltage of the circuit, Udthe falling voltage on the open diode 15; output winding element 18 memory voltage close to the value of E. the Latter circumstance is due to the fact that the resistance values of the resistors 11 and 12 are selected so that the magnetization switching of cores in Polubotko memory elements arose the voltage pulse amplitude ≈ F/2. At the output of the element 4 is formed by the signal "log.0"supporting the condenser 13 in the rarefied state at the output of the element 2 and the reset input (R) of the RS-trigger 1 signal "log.1"; output element 5 is formed by the signal "log.0"supporting the condenser 14 in the rarefied condition. As a result, the outputs of the elements 2 and 3 and the R and S inputs of the RS-flip-flop 1 signals appear "log.1", which leads to the appearance of signals "log.0" on both outputs (Q and) RS-flip-flop 1. As a result, the direction of the current through the coil of the memory element 17 changes its direction coinciding with the direction of magnetization of the core element 17 memory; the output winding of the memory element 17 there will be a short them the pulse interference of positive polarity relative to a common bus 20, which, as was shown above, will not affect the processes in the circuit, then the output winding element 17 memory set signal "log.0". Because the duration of the pulse appearing at the output winding of the memory element 17, is selected larger than the time constant of the integrating circuit (resistor 10, capacitor 14), the capacitor 14 is charged to a voltage "log.1", and the output element 3 and on the S-input of the RS flip-flop 1 with a delay set signal "log.0"inverse () output RS-trigger 1 set signal "log.1". The output winding element 18 of the memory stored signal "log.1". This ends the process of restoring the state of the RS-flip-flop 1. Similarly there is a restoration of the status of the RS-flip-flop 1 in accordance with the States of magnetization of the cores of the elements 17 and 18 of the memory when in the elements 17, 18 of the memory in the previous cycle of operation of the trigger device was recorded state "log.1".

To switch the trigger device on the input bus 19 is supplied clock signal with the level "log.0". At the output of the inverter 8 - signal "log.1", items 2 and 3 of the Exclusive-OR begin to operate in the repeater signals taken from the capacitors 13 and 14, respectively. Consider the process of switching trigger device, which is in the state "log.0", features resouses fact, what the RS-flip-flop 1 is in the state "log.0", the capacitor 13 is attenuated to the level of "log.0", the capacitor 14 is charged to the level of "log.1". With the start switch on the output element 4 is confirmed by the signal "log.0", the output element 5 set signal "log.0", these signals will be transmitted via the repeaters on the elements 2 and 3 on the R and S inputs of the RS-flip-flop 1, but the signal on the S input is transmitted with a delay defined by the time constant of the RC circuit composed of resistor 10 and capacitor 14 so RS-trigger 1 time to switch to state "log.1". Then alternating magnetization of the core elements 17 and 18 of the memory in a state opposite to that which they had in the previous cycle. Current with direct output (Q) of the RS-flip-flop 1 flows through the diode 15 and through the winding of the element 17 of the memory of her entrance to the middle point), through a resistor 11 to the output of the inverter 6, at the output winding of the memory element 17, due to its bypass diode 15, a voltage close to the value E (E-2Ud). Current from the output of the inverter 7 flows through the resistor 12, the coil element 18 memory (from mid-point to its input) inverted output () RS-trigger 1, the diode 16 is shifted in the reverse direction, the output winding of the element 18 to a voltage close to the value that is After the alternating magnetization of the core elements 17 and 18 memory at the output winding ele is enta 17 memory set voltage, equal to the voltage on the direct output of the RS flip-flop 1 (≈ (e)at the output winding element 18 memory set voltage close to zero. These signals through the elements 4 and 5 are not transmitted since the last state is determined by the output signal from the inverter 8, so for the duration of the clock pulse does not change the state of the RS-flip-flop 1. After the clock signal at the input 19 items 2 and 3 pass mode inverters of the signals taken from the capacitors 13 and 14, respectively, at the output of the inverter 8 is again a signal "log.0". Signal "log.0" output winding element 18 of the memory capacitor 13 is charged to a level "log.1", R input of the RS-trigger 1 signal appears briefly "log.1", then the set signal "log.0". Signal "log.1" from the output winding of the memory element 17 is confirmed by the discharged state of the capacitor 14, the S-input of the RS flip-flop 1 is set to signal "log.1". As a result, RS-trigger 1 after the clock pulse will remain in a state of "log.1", items 17 and 18 of the memory magnetized state "log.1". Similarly switches the trigger device from the "log.1" state "log.0".

Restoring the state of the trigger device, if it fails under the influence of the distortion in the storage of information, is carried out according to the according to the state of the elements 17 and 18 of the memory in the same way how is his recovery when the power supply voltage. For example, if the triggering device is in the state "log.0" (on the Q-output of the RS-flip-flop - signal "log.0", the cores of the elements 17 and 18 memory magnetized state "log.0", as shown by arrows in the drawing), and the obstacle will switch RS-trigger 1 status to "log.1" (UQ=l,=0), the output winding of the memory element 17, a signal will appear "log. 1, the output winding element 18 memory will remain alert log. 1″, which was present before switching RS-trigger hindrance. With a delay determined by the discharge of capacitor 14, the signal "log.1" will appear on the S-input of the RS flip-flop 1; R-input of the RS flip-flop 1 will preserve the signal "log.1", which was present before switching RS-flip-flop 1 is a hindrance. Direct (Q) output RS-flip-flop, a signal will appear "log.0"inverse () the output signal will remain "log.0". The direction of the current through the winding of the memory element 17 is restored at the output winding of the memory element 17, a signal will appear "log.0", the capacitor 14 is charged to a voltage "log.1", respectively, will be removed signal "log.1" S input of RS flip-flop 1 and its inverse output () restored signal "log.1".

From the description of the operation of the trigger device can be seen that its normal operation is provided when the RA is Enste the number of turns in Polubotko elements 17 and 18 of the memory, one Polubotko (between the entrance and the middle point of the winding) by analogy with the prototype performs the role of a winding of a record, and both are connected in series Polubotko perform the role of windings reading. In the schema of the prototype for its normal functioning of the winding of the reader should contain approximately 2 times more turns than the winding of the recording, therefore, in the inventive device, taking into account the overlapping of the windings writing and reading, each memory element may contain one-third fewer turns, or when the selected sizes of cores it is possible to increase 1.5 times the number of turns in the windings of the read and write (in each of Polubotok elements 17 and 18 memory), and then decrease to about 1.5 times the magnetizing current of the core memory elements by increasing resistance limiting resistors 11 and 12. As a result, reduces the current consumption of the trigger device from the power source in static and dynamic modes.

Thus, as follows from the description of work, declare the trigger device has a lower current consumption from the power source.

Testing laboratory layout trigger device confirmed the feasibility and practical value of the claimed device.

The trigger device, RS trigger the first and second elements of the “Exclusive OR”, the first inputs are combined and connected to the input bus, the first and second memory elements on magnetic cores with rectangular hysteresis loop, the first, second resistors, the first conclusions which are connected to a common bus through the first and second capacitors, respectively, the third and fourth resistors, wherein the introduced first and second elements OR NOT, the first, second and third inverters, the first and second diodes, the first and second memory elements on magnetic cores with rectangular hysteresis loop contain one winding, medium point which is connected to the cathodes of the first and second diodes, respectively, and respectively through the third and fourth resistors connected to the outputs of the first and second inverters, respectively, the inputs of which are connected with inputs of the windings of the first and second memory elements, respectively, and respectively direct and inverse outputs RS-trigger, and reset inputs of the installation which is connected to the outputs of the first and second elements of the “Exclusive OR”, respectively, the second inputs of which are connected with the first pins of the first and second resistors, respectively, the latter findings are connected to the outputs of the first and second elements OR NOT, respectively, the first inputs of which are connected to the outputs exchange rate up to the current second and first memory elements, respectively, and the second inputs are combined and connected to the output of the third inverter, whose input is connected to the input bus, RS-trigger executed on the items OR NOT.



 

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