Flip-flop device

FIELD: pulse engineering, computer engineering, and control systems.

SUBSTANCE: proposed device has RS flip-flop 1, two NAND gates 2, 3, EXCLUSIVE OR gate 4, inverter 5, four resistors 6 through 9, capacitor 10, memory item 11 built around magnetic core with rectangular hysteresis loop that carries write and read coils, two diodes 12, 13, control input 14, and common bus 15.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

 

The invention relates to a pulse technique and can be used in computer equipment and control systems.

Known trigger device (see USSR author's certificate No. 970650 from 03.04.81, MKI: N 03 To 3/286 "Trigger device" (and its variants), the author Geesken, publ. 30.10.82, bull. No. 40)containing the input bus, a common bus, the power bus, an RS-flip-flop, the first and second memory elements on magnetic cores with rectangular hysteresis loop (BCPs) with windings writing and reading, the first and second diodes, the first and second capacitors, first and second resistors, the first and second logical elements of the "Exclusive OR". The input windings of the read first and second memory elements connected to a common bus and the outputs of the windings reading through respectively the first and second diodes connected in the forward direction relative to the power source are connected respectively to the inputs set and reset the RS flip-flop are connected to a common bus through respectively the first and second capacitors and the power bus through respectively the first and second resistors. The outputs of the windings of the first and second memory elements are connected, and the input windings of the records connected with the outputs respectively of the first and second logic elements, the first inputs of which are connected to the input bus, and the second in the odes - accordingly, direct and inverse outputs RS-trigger.

The disadvantages of this device are its comparative difficulty associated with the use of two memory elements, and a relatively large current consumption of the circuit from the power source.

Known trigger device (see RF patent №1734563 from 02.04.90, MKI: N 03 To 3/286 "Trigger device", the authors Lbero and Geesken, publ. 10.09.97, bull. No. 25), which is the closest to the technical essence and selected as a prototype, containing RS-trigger element Exclusive OR, inverter, two resistors, a capacitor and a memory element on a magnetic core with BCPs with windings writing and reading. The reset inputs and an RS-flip-flop through the first and second resistors connected respectively with the input and output windings reading of the memory element, input and output windings write memory element connected respectively to the output element of the "Exclusive OR" and to the inverter output, the input connected to the output element of the "Exclusive OR", the first input of which is a control input of the trigger device, and a second input connected to the direct output of the RS-flip-flop. The middle point of the winding of the reading of the memory element connected to a common bus. The reset input of the RS-flip-flop through the condenser is connected with its input set.

The disadvantage of the prototype I have is the relatively high current consumption of the circuit from the power source.

The problem solved by the claimed invention is to reduce current consumption from the power source.

This technical result is achieved in that the trigger device containing RS-trigger between inputs reset and installation of which is connected to the capacitor element Exclusive OR, inverter, two resistors and a memory element on a magnetic core with BCPs with the windings of the read and write, and reset inputs of the RS-flip-flop connected with the first pins respectively of the first and second resistors, the input winding of the recording is connected to the input of the inverter and the output element of the "Exclusive OR", the first input of which is a control input of the trigger device; what is new is the introduction of the third and fourth resistors, the first and second diodes, the first and second elements AND the first inputs of which are connected respectively with the inverse and the direct outputs of the RS flip-flop and the second inputs are connected respectively to the outputs of the second and first elements, AND IS NOT, the output of the first element AND IS NOT connected with the second input element of the "Exclusive OR", anodes of the first and second diodes connected respectively to the reset inputs and an RS-flip-flop, and the cathodes are connected respectively with the second pins of the first and second resistors and the corresponding output and input windings reading, midpoint, which is Oh through the third resistor connected to a common bus, the output winding of the recording via the fourth resistor is connected to the inverter output.

This set of essential features can reduce the current consumption of the trigger device from the power source due to the possibility of reducing the bias current of the core.

The drawing shows a circuit diagram of a trigger device. The trigger device has an RS-flip-flop 1, the elements AND NOT 2, 3, item 4 "Exclusive OR", the inverter 5, resistors 6, 7, 8, 9, a condenser 10, item 11 of the memory containing the magnetic core with BCPs with windings writing and reading, the diodes 12, 13, the control input 14, a common bus 15. The reset input of RS flip-flop 1 through the resistor 6 is connected to the output winding of the reading of the memory element 11. The input of the RS flip-flop 1 through the resistor 7 is connected to the input winding of reading. Between the reset inputs and an RS-flip-flop is connected to the capacitor 10. The resistors 6 and 7, the device is activated respectively by diodes 12 and 13, and the cathodes of diodes 12, 13 are connected respectively to the output and input windings reading. The first input element 4 "Exclusive OR" is connected with the control input 14. Direct and inverted outputs of the RS-flip-flop 1 is connected respectively to the first inputs of the elements 2 and 3 AND IS NOT; the second input element 2 is connected with the output element 3; the second input element 3 is connected to the output element 2 and the second is the move item 4 "Exclusive OR", the output of which is connected to the input of the inverter 5 and to the input winding of the recording element 11 memory. The output winding of the recording through the resistor 9 is connected to the output of the inverter 5. The midpoint of the winding read through the resistor 8 is connected to the common bus 15. RS-trigger 16 includes a third and fourth 17 elements AND, thus, the first inputs of the elements 16 and 17 are connected respectively to the inputs set and reset the RS flip-flop, the second input element 16 is connected with the output element 17 and is the inverted output of the RS flip-flop 1, the second input element 17 is connected with the output element 16 and is a direct output of the RS flip-flop 1.

The trigger device operates as follows. At power-up (power circuit logic elements 2, 3, 4, 5, 16, 17 not shown) of the trigger device will be set to the state corresponding to the state of the memory element 11, which he had acquired in the previous cycle. Consider the case where the core element 11 memory was magnetized in the status log. 0" (which corresponds to the current flowing in the winding of the recording from the end of the winding to its beginning, the start winding in the drawing, mark(*)). If after power RS-trigger 1 will be set in a state in which its direct (output element 16) and inverse (output element 17) the outputs are the signals "log.1", RS-flip-flop composed of elements stored is 2 and 3, may be in the condition in which the output element 2 will be either signal "log.0"or the signal "log.1". If item 2 was set signal "log.0"in the absence of a signal at the control input 14 output element 4 is also set signal "log.0", the output of the inverter 5 - signal "log.1". The current flowing in the winding of the recording core element 11 has a direction from the end of the winding to its beginning, that is, confirms the state of the core element 11. In the winding of the read core element 11 thus there is a short pulse interference resulting from nepryamougolnoy of the hysteresis loop of the core element 11.

Impulse noise is applied in addition to the output winding of the reading with respect to its input, while the potential difference between input and output winding of the reading is determined by the ratio between the number of turns of the windings writing and reading. For normal operation of the device the number of winding turns reading should be chosen twice as a large number of turns of winding of the recording, the resistor is selected so that the amplitude of the working pulse to the winding of the recording was approximately equal to half the supply voltage. In this case, the amplitude of the impulse noise on the output winding of reading can reach values close to the magnitude of the supply voltage. the ri calculation of the potential at the input of the RS-flip-flop (on the first input element 16) consider the impact of the diode input protective circuit RS-flip-flop 1 to S-input. With this in mind, the voltage on the R - and S-trigger inputs 1 at the initial moment of time will be:

where Ud is the voltage drop on the diode input protective circuit according to the S-input of the trigger 1.

The voltage on the winding outputs the read will be:

where U, U and Ucp - accordingly, the voltage at the input, output and at the midpoint of the winding of reading, Ud1 - the voltage drop across the diode 13, E - supply voltage of the device. The magnitude of the voltage drops in the diode input protective circuit and the diode 13 accept the same and equal to the value Ud.

Further, as the charge of the capacitor 10, the voltage on the R - and S-trigger inputs 1 will seek to values respectively-2Ud+E and-Ud, because after the charge of the capacitor 10, the current through the resistor 6 will cease. From this it follows that if the time constant of charge of the capacitor 10 is selected greater than the duration of the impulse noise on the output winding of reading, the specified interference will not change the state of the RS-flip-flop, which was defined in the beginning ("log.0" on R - and S-trigger inputs 1 generates a status log. 1" direct and inverse outputs trigger 1). After completion of the pulse interference on the coil of the read voltage on its findings and on R - and S-trigger inputs will be set equal to zero. If after power-output element 2 is established, the signal log. 1', in the absence of a signal at the input 14 output elements 2 and 4 - signal "log.1", the output of the inverter 5 - signal "log.0". In the winding of the recording element 11 through the resistor 9 current flows from the start winding to its end, while the core of the memory element 11 starts paramagnetically in the state "log.1". The output winding of the reading you receive the voltage applied advantage to the input winding of reading, while the voltage on the winding outputs the read will be:

On R - and S-trigger inputs 1 first time will be set voltage:

In this case, the binding of the output winding of reading the potential of the common bus 15 via the diode input protective circuit RS-flip-flop 1 to S-input and the diode 12. Accept the magnitude of the voltage drop across these diodes are identical and equal to the value of Ud. After the charge of the capacitor 10 to the reset inputs and the installation will operate voltage:

At the output of the element 17 will be set signal "log.1", the output element 16 signal "log.0", under the action of these signals at the output of element 2 will be set signal "log.0", is ihade item 3 - the signal "log.1", that is, the RS-flip-flop composed of the elements 2 and 3 will be set to the state corresponding to the state of the memory element 11. The winding current account will change its direction to the opposite. The output winding of reading, this would create a pulse interference, plus applied to the output winding of reading, which is input to the RS flip-flop 1 will not work and will not cause the change of its state. At the end of the impulse noise on all pins of the winding-read-and R - and S-trigger inputs 1 also will be zero volts. Similarly implemented saving and restoring the state of the trigger device when the power is turned on, if the core of the memory element has been pre-magnetized state "log.1", that is, the magnetizing current flowed from the input winding of the record to its output.

Consider the process of switching trigger device under the action of a signal on the control input 14. Let for definiteness, the trigger device is in the state "log.0", while the core of the memory element 11 is magnetized in the state "log.0", RS-flip-flop composed of the elements 2, 3, is in the zero state, in which the output element 2, the signal is present "log.0", R - and S-trigger inputs 1 - signals "log.0". When input 14 signal "log.1" at the output of the element 4 will signal the "log.1", at the output of the inverter 5 - signal "log.0". In the winding of the recording element 11 current flows from the input winding to the output. Because the core is magnetized in the state "log.0", the output winding of the reading will be a full pulse applied advantage to the input winding of reading. Through the time constant set recharge time of the capacitor 10, the S-input trigger 1 will appear voltage "log.1"on its R input will be voltage "log.0". The values of these voltages are determined by the formulas (9) and (10). These signals confirm the zero state of the RS flip-flop composed of the elements 2 and 3, the output element 2 is maintained signal "log.0", the output element 4 - signal "log.1", the output of the inverter 5 - signal "log.0". The winding current account will remain in its direction to the input winding of the reading will remain a pulse of positive polarity. For the duration of the pulse at the input 14 of the core of the memory element 11 must paramagnetics in brand new condition. After removal of the signal at the input 14 of the winding current account will change its direction to the opposite, at the output winding of reading will also change the polarity of the signal. Stresses acting on the winding outputs read, are described by the formulas(2), (3), (4). Because over magnetize the core in the new state, the pulse duration at the output winding autom whom I greatly exceeds the value of the time constant of the charging capacitor 10, as a result, the voltage at the R-input trigger 1 reaches the threshold value of switching on inverse trigger output 1, a signal will appear "log.0", switching RS-trigger of the elements 2, 3 in the state "log.1" ("log.1" output item 2, "log.0" on the output element 3). The winding current account will change its direction to the opposite, the output winding of the reading there will be a short impulse interference, which will not pass to the input of RS flip-flop due to the integrating properties of the capacitor 10. In the steady state on the winding outputs the read and the R and S inputs of the RS-flip-flop will be set to zero voltage by binding the mid-point of the winding of reading to a common bus through a resistor 8.

Similarly is in the process of switching the trigger device from the "log.1" state "log.0" under the influence of the input signal of the control input 14.

Restoring the state of the trigger device under the influence of the distortion is the same as its recovery when the power supply. For example, if the triggering device is in the state "log.0" (output element 2 - signal "log.0", the core of the memory element magnetized from the output to the input winding of the recording, at the input 14 signal "log.0") and disturbance will switch RS-flip-flop composed of the elements 2, 3 in the status log. 1", that is in the winding recording changes direction and the output winding of the read voltage appears, applied plus to its input, which restores the state of the trigger, composed of the elements 2, 3. The recovery process is described by the formula(5)-(10).

Thus, when switching trigger device under the action of the input signal of the control input 14, for the duration of the pulse input signal is alternating magnetization of the core of the memory element 11, the state of the RS flip-flop composed of the elements 2, 3, and does not change, because at the inputs of RS flip-flop 1 are generated voltage, confirming its status; the slicer input signal pulse switch RS-flip-flop composed of the elements 2, 3, in the state of the memory element 11. Failure RS-flip-flop composed of the elements 2, 3, in the absence of a signal at the control input 14 output winding of the reading of the memory element 11 there is tension, switching the specified RS-trigger in the state of the memory element 11.

From the description of the operation of the trigger device can be seen that its normal operation is provided when the ratio of the number of turns of the winding of the recording and the number of winding turns reading 1:2, while in the scheme of the prototype for its normal functioning of the specified value must be chosen equal to 1:4. This is because in the scheme of the prototype with ednea point windings reading rigidly tied to the ground potential common bus, therefore, in order to form the output Polubotko voltage close to the value of the supply voltage (E), when the amplitude of the pulse in the winding of account, equal to the value E/2, it is necessary to have in each Polubotko read the number of turns in 2 times more than in the winding of the recording. In the diagram of the inventive device is useful switching signal to the corresponding input of the RS flip-flop 1 is supplied not with Polubotko, and with all windings reading, due to the fact that the use of new features and links allows you to organize binding output winding of reading, having a lower potential, the potential is close to zero (2Ud). This difference in the ratio of turns of the windings of the read and write of the memory element allows for the chosen dimensions of the core to increase the number of turns of the winding and means to reduce the magnetizing current and to increase the resistance of the resistor 9. This reduces the current consumption of the trigger device from the power source in static and dynamic modes.

Thus, as follows from the description of work, declare the trigger device has a lower current consumption from the power source.

Testing laboratory layout trigger device confirmed the feasibility and practical value of the claimed device.

Trigger is a great device, containing RS-trigger between inputs reset and installation of which is connected to the capacitor element XOR, inverter, two resistors and a memory element on a magnetic core with a rectangular hysteresis loop with the windings of the read and write, and reset inputs of the RS-flip-flop connected with the first pins respectively of the first and second resistors, the input winding of the recording is connected to the input of the inverter and the output of the EXCLUSIVE OR element, the first input of which is a control input of the trigger device, characterized in that it further introduced the third and fourth resistors, the first and second diodes, the first and second elements AND IS NOT the first inputs of which are connected respectively with the inverse and the direct outputs of the RS flip-flop and the second inputs are connected respectively to the outputs of the second and first elements, AND IS NOT, the output of the first element AND IS NOT connected with the second input of the EXCLUSIVE OR element, the anodes of the first and second diodes connected respectively to the reset inputs and an RS-flip-flop, and the cathodes are connected respectively with the second pins of the first and second resistors and the corresponding output and input windings reading, midpoint, which through the third resistor is connected to the shared bus, the output winding of the recording through a fourth resistor connected to the output of the inverter.



 

Same patents:

FIELD: digital pulse engineering.

SUBSTANCE: proposed device designed for shaping pulses of desired length for each of three events during power turn-on in response to off-operation button signal incorporating provision for chatter elimination in case of skip or stop of changes in input pulses on detection enabling has first and second monostable restart multivibrators 1, 4, off-operation button 2, flip-flop 3, shaper 5 of signal responding to button-provided power turn-on which is built around capacitor 12, resistors 13, 14, diode 15 and two NAND gates 6,7, as well as AND gate 8, controllable pulse generator 9, logical 1 input, pulse signal input 10, and control input 11. Controllable pulse generator 9 is built around AND gate 16, NAND gate 17, resistors 18, 19, and capacitor 20. Device can shape input pulse during power turn-on period and function as hardware watch timer implemented in the course of forward and backward automatic interaction with system microcontroller.

EFFECT: enlarged functional capabilities of device.

1 cl, 1 dwg

FIELD: measurement technology; pulse stream generators.

SUBSTANCE: proposed Poisson pulse stream generator has k + 1 memory devices, comparison unit, k digital-to-analog converters, control circuit, register, counter, selector, k bell-shaped pulse generators, adder, voltage-to-current converter, and clock generator.

EFFECT: enlarged generation range of pulses adequate to ionization chamber signals.

1 cl, 2 dwg

The invention relates to a means for information transfer and remote control systems on their basis

The invention relates to a device for charging rechargeable batteries of the network through the converters and can be used to charge energy storage in various automation devices and computing

A threshold device // 2237971
The invention relates to automatic control and computer engineering and can be used to control the level of a single pulse signals and generating voltage pulses with a given amplitude

The trigger device // 2237970
The invention relates to a pulse technique and can be used in devices of computer engineering and control systems

The trigger device // 2237970
The invention relates to a pulse technique and can be used in devices of computer engineering and control systems

The trigger device // 2237969
The invention relates to a pulse technique and can be used in the counting devices of computer engineering and control systems

The trigger device // 2237969
The invention relates to a pulse technique and can be used in the counting devices of computer engineering and control systems

The ternary trigger // 2237968
The invention relates to a pulse technique and can be used in devices of computer engineering and control systems

FIELD: measurement technology; pulse stream generators.

SUBSTANCE: proposed Poisson pulse stream generator has k + 1 memory devices, comparison unit, k digital-to-analog converters, control circuit, register, counter, selector, k bell-shaped pulse generators, adder, voltage-to-current converter, and clock generator.

EFFECT: enlarged generation range of pulses adequate to ionization chamber signals.

1 cl, 2 dwg

FIELD: digital pulse engineering.

SUBSTANCE: proposed device designed for shaping pulses of desired length for each of three events during power turn-on in response to off-operation button signal incorporating provision for chatter elimination in case of skip or stop of changes in input pulses on detection enabling has first and second monostable restart multivibrators 1, 4, off-operation button 2, flip-flop 3, shaper 5 of signal responding to button-provided power turn-on which is built around capacitor 12, resistors 13, 14, diode 15 and two NAND gates 6,7, as well as AND gate 8, controllable pulse generator 9, logical 1 input, pulse signal input 10, and control input 11. Controllable pulse generator 9 is built around AND gate 16, NAND gate 17, resistors 18, 19, and capacitor 20. Device can shape input pulse during power turn-on period and function as hardware watch timer implemented in the course of forward and backward automatic interaction with system microcontroller.

EFFECT: enlarged functional capabilities of device.

1 cl, 1 dwg

Flip-flop device // 2248662

FIELD: pulse engineering, computer engineering, and control systems.

SUBSTANCE: proposed device has RS flip-flop 1, two NAND gates 2, 3, EXCLUSIVE OR gate 4, inverter 5, four resistors 6 through 9, capacitor 10, memory item 11 built around magnetic core with rectangular hysteresis loop that carries write and read coils, two diodes 12, 13, control input 14, and common bus 15.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Flip-flop device // 2248663

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flop 1, EXCLUSIVE OR gates 2,3, NOR gates 4, 5, inverters 6, 7, 8, diodes 15, 16, resistors 9 through 12, capacitors 13, 14, memory items 17, 18 built around magnetic cores with rectangular hysteresis loop and single coil, input bus 19, and common bus 20. Combining write and read coils of memory items 17 and 18 makes it possible to increase coil number of write and read coils by 1.5 times, in each of half-coils of memory items 17 and 18, which reduces magnetizing current through cores of memory items 17 and 18 by approximately 1.5 times due to enhancing ratings of limiting resistors 11 and 12.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Flip-flop device // 2248663

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flop 1, EXCLUSIVE OR gates 2,3, NOR gates 4, 5, inverters 6, 7, 8, diodes 15, 16, resistors 9 through 12, capacitors 13, 14, memory items 17, 18 built around magnetic cores with rectangular hysteresis loop and single coil, input bus 19, and common bus 20. Combining write and read coils of memory items 17 and 18 makes it possible to increase coil number of write and read coils by 1.5 times, in each of half-coils of memory items 17 and 18, which reduces magnetizing current through cores of memory items 17 and 18 by approximately 1.5 times due to enhancing ratings of limiting resistors 11 and 12.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Flip-flop device // 2248664

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flops 3, 16, EXCLUSIVE OR gates 1, 2, NAND gates 5, 6, NOR gates 10, 11, resistors 4, 7, 12, 13, capacitors 14, 15, memory items 8, 9 built around magnetic core with rectangular hysteresis loop and single center-tapped coil, input bus 21, and common bus 22. Combining read and write coils of memory items 8, 9 makes it possible to increase turn number in read and write coils by 1.5 times, in each of half-coils of memory items 8 and 9, which reduces magnetizing current through cores of memory items 8 and 9 approximately by 1.5 times due to enhancing ratings of limiting resistors 4 and 7.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Flip-flop device // 2248664

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flops 3, 16, EXCLUSIVE OR gates 1, 2, NAND gates 5, 6, NOR gates 10, 11, resistors 4, 7, 12, 13, capacitors 14, 15, memory items 8, 9 built around magnetic core with rectangular hysteresis loop and single center-tapped coil, input bus 21, and common bus 22. Combining read and write coils of memory items 8, 9 makes it possible to increase turn number in read and write coils by 1.5 times, in each of half-coils of memory items 8 and 9, which reduces magnetizing current through cores of memory items 8 and 9 approximately by 1.5 times due to enhancing ratings of limiting resistors 4 and 7.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

FIELD: computer science.

SUBSTANCE: device has random numbers source, N-digit selector-multiplexer, RAM, ranges control block, generations number control block, J-input OR element, AND elements block. Because series of given values of data set is broken in ranges and frequency of their appearance is set within certain limits, random series is generated with distribution law, presented in form of ranges.

EFFECT: broader functional capabilities.

3 cl, 7 dwg

Flip-flop device // 2250554

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flops 1, 2 built around NOR gates 22, 23, 26, 27, and also NOR gates 4, 5, control device 3, diodes 10, 11, resistors 12 - 17, capacitors 6 - 9, memory elements 18, 19 built around rectangular hysteresis loop cores each incorporating write winding and read winding, at least one input bus 20, and common bus 21. Newly introduced in device are RS flip-flop 2, diodes 10, 11, and capacitors 8, 9).

EFFECT: enhanced immunity to persistent intensive noise.

1 cl, 2 dwg

Flip-flop device // 2250554

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flops 1, 2 built around NOR gates 22, 23, 26, 27, and also NOR gates 4, 5, control device 3, diodes 10, 11, resistors 12 - 17, capacitors 6 - 9, memory elements 18, 19 built around rectangular hysteresis loop cores each incorporating write winding and read winding, at least one input bus 20, and common bus 21. Newly introduced in device are RS flip-flop 2, diodes 10, 11, and capacitors 8, 9).

EFFECT: enhanced immunity to persistent intensive noise.

1 cl, 2 dwg

Up!