Device for controlling one-crystal microcontroller

FIELD: computers.

SUBSTANCE: device has commutation block, checked microcontroller, block of read-only memory devices of checked microcontroller, block of operative memory devices, PC, controlling microcontroller, block 7 of serial interface, indication block, commutation block of serial interface, block for forming a signal of starting setting of block for forming ROM addresses, block for forming addresses of Rom of checked microcontroller, block for decoding control signals, data-reading block, RAM recording block, block of memory access constants for checked microcontroller, block for forming addresses of checked microcontroller, block for forming start setting signal for controlling microcontroller, RAM reading block, block for forming RAM addresses and power buses.

EFFECT: higher efficiency.

3 dwg

 

The invention relates to digital computing and can be used in automated systems for control of microcomputers containing digital inputs and outputs.

A device control single-chip microcontroller (see A.S. USSR №1578716 from 22.07.88, MKI: G 06 F 11/26, "Device for controlling microcomputers", Tkachenko A. M., Vargo V.L., Tyutyunnikov, NV, publ. 15.07.90, bull. No. 26), containing the block I / o information, two counters, five registers, display, two memory block, the block key, item, unit d / a converters, analog-to-digital Converter, two analog switch block analog switches, a register unit, a digital switch, a comparison circuit, an item OR two block elements And. the Input "start" the device is connected to the inputs of the Reset counters and block I / o information of the first register and an output device for connecting (control) to the microcomputer (microcontroller). The first output block I / o is connected to the input of the second counter and an information input of the first memory block. The second output unit I / o is connected to the input of the input information of the second memory block. The first information output of the second memory block through the block of keys connected to the inputs - outputs of the device to connect the computer and information input of the second reg the country. The address input of the first memory block is connected to the output of the second counter. The counting input of a second counter connected to the clock input of the device for connecting the microcomputer. Enter "Reading" of the first memory block is connected to the input Query I / o devices for connecting the microcomputer. Entrance sign "Enter" device for connecting the microcomputer connected to the first input element And the control input of the unit keys. Input characteristic Output device for connecting the microcomputer is connected with the second input element And synchronator second register. The information output of the first memory block and the second information output of the second memory block are connected to the corresponding information to the inputs of the first register. The outputs of the first counter and a second register connected to the corresponding address inputs of the second memory block. Enter "Reading" of the second memory block is connected to the input query I / o device to connect the computer. The output element And is connected to the control input of the first register. The output of the first register is connected to the input of the indicator. The input "start" the device is connected to the input "Reset" of the third, fourth and fifth registers. The output of the third register is connected to the third address input of the second memory block. Third information input of the second memory block is connected to the control wchodzacego switch the first and second analog switches, to the information inputs of the fourth and fifth registers to the input of the start block of registers to the first inputs of the first and second block elements And. the Information input of the third register connected to the output of the digital switch. The outputs of the second register and the analog-to-digital converters are connected to the appropriate information inputs digital switch. The first and second inputs of the comparison circuit are connected, respectively, to the outputs of the third and fourth registers. The output of the comparison circuit connected to the data input of the register unit. Digital output register unit is connected to the first information input of the digital-to-analog converters. Output "End of conversion" block registers is connected to the first input of the OR element. The output of the fifth register is connected with the second information input unit digital-to-analog converters. The analog output of digital-to-analog converters via the first analog switch and a block of analog switches connected to the inputs - outputs of the device for connecting the microcomputer. The input - output device to connect the computer through the second analog switch is also connected to an analog input unit analog-to-digital converters. The second inputs of the first and second block elements And elemental connected, accordingly, the output "Output" "Input" and Request "input / output device for connecting the microcomputer. The outputs of the first and second block elements And element OR connected, respectively, to the input "start" of the analog-to-digital converters, managing input unit analog switches and a counter input of the first counter.

A disadvantage of the known devices is the inability to determine the specific test commands executed incorrectly, due to the lack of detailed comparison and display for a user specified commands.

A device control single-chip microcontroller (see SCM 1.142.025 THEN appr. 1986, JSC “December”, Voronezh), taken as a prototype and containing the measuring head (check the microcontroller), the unit of the digital summation unit test sequences (block permanent storage devices scanned microcontroller), memory block errors (block RAM), a programmable pulse generator, the generator of random sequences, the control unit, the unit of measure source, the analog-to-digital Converter, a switch matrix (switching unit)unit-set level, a personal electronic computer (PC). The output of the switching matrix connected to the PE the new entrance of the measuring head, the first output of which is connected to the first input unit of the digital summation, the first input of the control unit, the first input block of the test sequence, the second output programmable pulse generator, the input-output generator arbitrary sequences, the output of the analog-to-digital Converter, the first input of the switching matrix and the input unit of job levels, the output of which is connected with the second input of the measuring head. The first output unit of the digital summation connected with the third input of the measuring head, the second output of which is connected with the second input unit of the digital summation, the second output of which is connected to the fourth input of the measuring head. The first output of the unit test sequences connected to the first input of the block of memory errors. The second output of the unit test sequences connected with the third input unit of the digital summation, the third output of which is connected with the second input of the control unit, the third input of the block of memory errors and the first input of the programmable pulse generator, the first output of which is connected with the second input of the test sequences and the fifth input of the block of memory errors. First, second and third outputs of the generator arbitrary sequences, respectively, connected to the fourth toe is m and the eighth input unit of the digital summation. The fourth output of the generator arbitrary sequences connected with the second input of the block of memory errors. Group outputs programmable pulse generator connected to the respective group of input unit of the digital summation. The first output control unit connected with the second input of the programmable pulse generator, the second output control unit connected to the input of the power source, the first output of which is connected to a second input of the switching unit. The second output unit of measure source connected to the first input of the analog-to-digital Converter, input-output control unit is connected to the output-input personal computers.

The disadvantages of the known devices is the complexity for the user, since the user needs to purchase special skills, and the inability of service (repair) by the user, because the known device has a very complex electrical circuit.

The problem solved by the invention is a device control single-chip microcontroller with simplicity for the user's control and maintenance.

The technical result consists in the ease of management for user and service capabilities, is achieved by the fact that in the device pin is Olya single-chip microcontroller, containing the switching unit, the first output of which is connected to the first input of the scanned microcontroller unit permanent storage devices (ROM) of the scanned microcontroller, block random access memory devices (RAM), personal computers and the power bus entered the control microcontroller unit serial interface, a display unit, switching unit serial interface, the processing unit initial installation of the unit address generation ROM, block address generation ROM scanned microcontroller, a decryption unit control signals, the unit reading data, the write block RAM block constants memory access check of the microcontroller, the shaping unit addresses scanned microcontroller, the shaping unit signal initial setup of the control of the microcontroller unit reading the RAM and the block address generation RAM switching unit is equipped with input and an additional output, check the microcontroller is equipped with five additional inputs, two additional groups of inputs and three outputs, and the block ROM scanned microcontroller has three additional inputs and additional output, with the input and output of personal computers are connected, respectively, with the first output and the input of the serial interface, is that the input and output of which are connected, accordingly, with the first output and the input of the switching unit serial interface, the second input and output of which are connected, respectively, with the first output and the control input of the microcontroller, the third input and output are connected, respectively, with the first output and the second input of the scanned microcontroller, and a fourth input connected to the first input of the block constants memory access scanned microcontroller and a second output of the control of the microcontroller, a second input connected to the second output of the switching unit, the input processing unit initial installation of the unit address generation ROM, the third input of the scanned microcontroller and the first input of the display unit, the second, third,the fourth and fifth inputs of which are connected to respective power bus device, the output processing unit initial installation of the unit address generation ROM connected to the first input of the block address generation ROM check of the microcontroller, a second input and multiple outputs which are connected, respectively, with the second output of the scanned microcontroller and a group of inputs of the block ROM check the microcontroller, the input and the first auxiliary input of which is connected, respectively, with the third and fourth outputs of the control of the microcontroller, the fifth vyhodnotila connected to the first auxiliary input checked microcontroller, the third output of which is connected to the input of the switching unit, the third and additional outputs which are connected, respectively, with the second and third additional verifiable inputs of the microcontroller, the first additional input connected to the second auxiliary input block ROM scanned microcontroller, third additional input connected to the fourth auxiliary input checked microcontroller, the first input record block RAM and the sixth output of the control of the microcontroller, the first group of outputs of which are connected with inputs of the block decoding control signals, the group of outputs of which are connected with inputs of the switching unit, the seventh and eighth outputs of the control of the microcontroller are connected, respectively, to the input of the block read data and the second input record block RAM, ninth and tenth terminals are connected, respectively, with first and second inputs of the block address generation RAM, eleventh and twelfth terminals are connected, respectively, with the second and third inputs of the block constants memory access check of the microcontroller, the thirteenth output connected to the input of the processing unit addresses scanned microcontroller, a third input coupled to the output processing unit initial setup of the control of the microcontroller, h is twenty input is connected to the output of the ROM check microcontroller, and a group of inputs connected to the group of outputs of block read data and outputs of the block RAM read, the first group of inputs of which are connected with a group of outputs of the block RAM, and the second group of inputs connected with the first group of inputs of the block RAM and the second group of control outputs of the microcontroller, the third group of outputs of which are connected with inputs of the block constants memory access check of the microcontroller, the first group of outputs of which are connected with the first group of inputs of the scanned microcontroller and the first group of outputs of the shaping unit addresses scanned microcontroller, the second group of outputs of which are connected with the second group of inputs of the scanned microcontroller and the second group of outputs of the block constants memory access check of the microcontroller, and a group of inputs connected to the group of inputs of the block address generation RAM, the second group of inputs of the block RAM, the third group of inputs of which are connected with a group of outputs of the write block RAM, a third input connected to the second additional output scanned microcontroller, third additional output of which is connected to the input of the block RAM and the third input of the block address generation RAM, the fifth auxiliary input and a third group of inputs connected, respectively, with additional output and outputs the block is and ROM scanned microcontroller, the first group of outputs connected to the group of inputs of the block of data is read and the first group of inputs of the write block RAM, and the second, third and fourth group of terminals are connected, respectively, with the second, third and fourth groups of inputs of the write block RAM.

This set of features allows you to achieve simplicity for the user's control due to the possibility of comparison, processing and displaying the received information, and service capabilities due to the simplicity of the schema.

Figure 1 shows a functional diagram of the device control single-chip microcontroller; figure 2 and figure 3 shows the flowchart of the algorithm, respectively, of the control of the microcontroller and a personal computer (PC).

The control device single-chip microcontroller contains (see figure 1) block 1 switching (Bq), check the microcontroller 2 (PM), unit 3 permanent storage devices scanned microcontroller (BSOPM), block of 4 RAM (BOZ), the PC 5, the controlling microcontroller 6 (MIND), block 7 serial interface (BPI), the display unit 8 (B), block 9 switching the serial interface (BKI), block 10 signal initial setup of the unit address generation ROM (NFSNOBODY), block 11 address generation ROM scanned microcontroller (VAPSUP), block 12 desif the emission control signals (BDUS), unit 13 read data (BCD), block 14 write RAM (BTSU), block 15 constant memory access scanned microcontroller (BCDCP), block 16 forming addresses scanned microcontroller (BFPM), block 17 signal initial setup of the control of the microcontroller (BTSNOOP), block 18 read RAM (BCSU) and the block 19 address generation RAM (BFOSU).

The first output Bq 1 connected to the first input 2 PM. The input and output of the PC 5 are connected, respectively, with the first output and the input of the power supply unit 7. Second input and output power supply unit 7 are connected, respectively, with the first exit and entrance of BKI 9. Second input and output BEKHTI 9 are connected, respectively, with the first exit and entrance the MIND 6. The third input and output BCPI 9 are connected, respectively, with the first output and the second input 2 PM, and the fourth input BCPI 9 connected to the first input BCDCP 15 and the second output of the MIND 6. Second input of the MIND 6 is connected with the second output Bq 1, entrance NFSNOBODY 10, the third input 2 PM and the first input of the BI 8. The second, third, fourth and fifth inputs B 8 connected to respective power bus device. Output NFSNOBODY 10 connected to the first input VAPSUP 11. Second input and multiple outputs VAPSUP 11 are connected, respectively, with the second output 2 PM and a group of inputs BSOPM 3. The entrance and the first auxiliary input BSOPM 3 are connected, respectively, with the third and fourth outputs of the MIND 6. Toe is the first release of the MIND 6 connected to the first auxiliary input 2 PM. The third output of the PM 2 is connected to the input of BC 1. Third and additional outputs Bq 1 are connected, respectively, with the second and third auxiliary inputs 2 PM. The first additional output PM 2 connected to the second auxiliary input BSOPM 3. The third auxiliary input BSOPM 3 is connected to the fourth auxiliary input 2 PM, the first input BTSU 14 and the sixth output of the MIND 6. The first group of outputs MIND 6 are connected with the inputs of BUS 12. Group outputs BUS 12 is connected with a group of inputs Bq 1. Seventh and eighth outputs MIND 6 are connected, respectively, to the input BCD 13 and a second input BTSU 14. The ninth and tenth outputs MIND 6 are connected, respectively, with first and second inputs BFOSU 19. The eleventh and twelfth outputs MIND 6 are connected, respectively, with the second and third inputs BCDCP 15. The thirteenth release of the MIND 6 connected to the input BFPM 16. The third entrance the MIND 6 connected to the output of BTSNOOP 17. The fourth input of the MIND 6 is connected to the output BSOPM 3, and a group of inputs connected to the group of outputs BCD 13 and outputs BCASW 18. The first group of inputs BCASW 18 is connected to the group outputs to the BOSE 4. The second group of inputs BCASW 18 is connected with the first group of inputs to the BOSE 4 and the second group of outputs of the MIND 6. The third group of outputs MIND 6 is connected with a group of inputs BCDCP 15. The first group of outputs BCDCP 15 is connected with the first group of inputs 2 PM and the first group of outputs BF is 16 PM. The second group of outputs BFPM 16 is connected with the second group of inputs 2 PM and the second group of outputs BCDCP 15. Group inputs BFPM 16 is connected with a group of inputs BFOSU 19, the second group of inputs to the BOSE 4. The third group of inputs to the BOSE 4 is connected with a group of outputs BTSU 14. The third entrance BTSU 14 is connected to a second additional output 2 PM. The third auxiliary output 2 PM connected to the input of the BOSE 4 and the third input BFOSU 19. The fifth auxiliary input and a third group of inputs GR 2 are connected, respectively, with additional output and outputs BSOPM 3. The first group of outputs of the PM 2 is connected with a group of inputs BCD 13 and the first group of inputs BTSU 14. Second, third and fourth output groups 2 PM are connected, respectively, with the second, third and fourth groups of inputs BTSU 14.

Bq 1 can be performed in three relays RPS, two chips KB, six diodes DA, two quartz resonators and four capacitors, and the output circuits CT connected to the negative poles of relay coils, diodes are connected in parallel to the windings of the relay, and the cathodes of the diodes connected to the positive pole winding of the associated relay, to the conclusions of quartz resonators connected by two condenser, the latter findings are connected to the bus "earth", in turn, the findings of quartz resonators are connected to different groups, one is from the relay. PM 2 may be performed on the chip NVE (NVE), ILE NOT LL and eight resistors, each of the eight inputs-outputs ADO-AD7 chip NVE connected to the resistors, the outputchip NVE connected to the first input L, the first output LL connected to the third and fifth input LL. BSOPM 3 can be implemented in two chips S and register IR, and the data bus of the first chip IS connected to information inputs of the register IR. The BOSE 4 can be performed on four chips CRRU 10. The PC 5 may be performed on the computer type IBM PC with operating system Windows 95/98, Windows NT 4.0 or Windows 2000. MIND 6 can be performed on the chip NVE, LA, 2I-NOT LA, 2I LI, OR NOT LN, quartz resonator, two capacitors, the conclusions of the quartz resonator connected two condenser, the latter findings are connected to the bus "earth", in turn, the conclusions of the quartz resonator is connected to the inputs of the chip NVE X1 and x2, outputsandchip H1830BE51 connected, respectively, to first and second inputs LN, the first output of which is connected to the second, fourth, sixth, eighth inputs of the first chip A and the second input of the second chip LA, the second output LN connected to the second and the third is the inputs LI, outputs A12-A15 chip H1830BE51 connected, respectively, to the first, third, fifth and seventh inputs of the first chip LA, outputs A15, A14 chip H1830BE51 connected, respectively, to the first and third inputs LI, the outputs A11, P1.7 chip NO connected, respectively, to the first and third inputs of the second chip LA exitchip H1830BE51 connected to the first and second inputs LA. Power supply unit 7 may be performed according to the scheme presented in the book "the Art circuitry" Horovitz P. and hill, U., publishing house "MIR", 1998, str, 631, RES. BI 8, can be performed on five LEDs LG and five resistors, while the cathodes of the LEDs are connected to the resistors, the second terminals of the resistors connected to the bus "earth". BCPI 9 can be performed on the chip ILI L and 2I LI, while the first and second outputs ALL connected, respectively, to first and second input LE. NFSNOBODY 10 can be performed on the chip TL, LA and integrating chain of resistor and capacitor, and the output of the integrating chain connected to the first input circuit TL, the first output circuits TL connected to the second input circuit TL, the second output chip TL is connected to the input circuit LA. VAPSUP 11 can be performed on three binary counters IE, s is the R between themselves consistently. BUS 12 can be performed on the chip ID and LN, while the outputs of the decoder ID inverted by nor circuits LN. BCD 13 can be performed on the register IR. BTSU 14 can be performed on three chips IN and chip IN. BCDCP 15 can be performed on two chips IN. BFPM 16 can be implemented in two chips IN. BTSNOOP 17 can be performed on the chip TL, LA and integrating chain of resistor and capacitor, and the output of the integrating chain connected to the first input circuit TL, the first output circuits TL connected to the second input circuit TL, the second output chip TL connected to the input circuit LA. BCASW 18 can be performed on four chips IN and four resistors, each input chip “write permission” is connected to the power bus through a resistor. BFOSU 19 can be performed on the chip 2I-NOT US and three binary counters A, while the output element 2I IS NOT connected to the counting input of the first counter, all counters IE included among themselves consistently. The fulfilment of the above blocks in figure 1 are not shown.

The control device single-chip microcontroller operates as follows.

Run the program on the PC 5, the block diagram of the program, not only is on figure 3. The program provides a choice of operating modes, the delivery on the device corresponding control commands, receiving information from the device and comparing it with a reference. The operation modes include a self-control device, the internal control program of the microcontroller 2 (NVE without a bit of protection / with a bit of protection and control of the microcontroller 2 (NO) at the selected frequency and the number of the test data.

Powering the device. BI 8 shows that the power is turned on and BTSNOOP 17 generates a reset signal for the MIND 6. Then the MIND 6 begins to work inside the program, which is presented as a flowchart in figure 2. This program provides for the operation of the device depending on the selected mode, the transfer to PC 5 information from the device to compare it with a reference. The operation modes include a self-control device, the internal control program of the microcontroller 2 (NVE without a bit of protection / with a bit of protection and control of the microcontroller 2 (NO) at the selected frequency and the number of the test data. The modes are selected by a command from the PC 5.

The MIND 6 issues a control sequence in BKI 9, which indicates the device is ready. BCPI 9, in turn, translates this sequence in the PC 5 through the power supply unit 7. Mode control NO (self) PC 5 gives the MIND 6 through the power supply unit 7 and BKI 9 Coman is in control NO (self-control), the block number and the selected frequency. MIND 6 generates signals for BFOSU 19 (thereby leading it to its original state), BUS 12, which, in turn, deshifriral them for BC 1. Bq 1 signals for BI 8 (which gives an indication of control mode), GR 2, BISNOVAT 10 and MIND 6. MIND 6 generates a reset signal to 2 PM. PM 2 starts to execute the test program, which is BSOPM 3. Address for BSOPM 3 comes with VAPSUP 11. The status of all four ports PM 2 snap in BTSU 14, and then the entry in the BOSE 4 on a signal recording from 2 PM. Addresses for the BOSE 4 comes with BFOSU 19. MIND 6 waits for the signal of the end of the control from BSOPM 3. As soon as the MIND 6 receives this signal, it generates signals for BFOSU 19 (thereby leading it to its original state), BUS 12, which, in turn, deshifriral them for BC 1. Bq 1 removes all power from 2 PM and signals for BI 8 (which removes the indication on the control). In the next step the MIND 6 reads the data stored in the BOSE 4. Treatment of the MIND 6 to the BOSE 4 occurs through BCASW 18. When the MIND 6 beeps and BFOSU 19. BFOSU 19 generates addresses for the BOSE 4. MIND 6 after reading each byte of stored data in the BOSE 4 translates it into the PC 5 through BCPI 9 and power supply unit 7. After receiving all the information the program on the PC 5 processes it and produces a visual result of the checked microcontroller 2. Next you about is the input of a control for another controller.

Mode control NVE bit without protection, the PC 5 through the power supply unit 7 and BKI 9 gives the MIND 6 command control. MIND 6 generates signals for BFOSU 19 (thereby leading it to its original state), BUS 12, which, in turn, deshifriral them for BC 1. Bq 1 signals for BI 8 (which gives an indication of the mode control), 2 PM and MIND 6. MIND 6 generates a reset signal to 2 PM. Address BFOSU 19 through BFPM 16 placed on P2. Next UM through BCD 13 reads codes internal program 2 PM and sends them to the PC 5 through BCPI 9, block 7 for further comparison. After receiving all the information the program on the PC 5 processes it and produces a visual result of the checked microcontroller. Next, you can check for other microcontroller.

Mode control NVE with a bit of protection, the PC 5 through the power supply unit 7 and BKI 9 gives the MIND 6 command, control, constants, memory access check of the microcontroller and the first code in the scanned microcontroller 2. MIND 6 records constants memory access scanned microcontroller in BCDCP 15 and adjusts its serial link using BKI 9 at 2 PM. MIND 6 generates signals for BFOSU 19 (thereby leading it to its original state), BUS 12, which, in turn, deshifriral them for BC 1. Bq 1 signals for BI 8 (which gives an indication of the mode control, PM 2 and the MIND 6. MIND 6 generates a reset signal to 2 PM. Then the MIND 6 through BCPI 9 gives 2 PM the first byte of the program. PM 2 answers “YES”, if the byte coincided and “NO”if not matched. MIND 6 configures a serial link to the PC 5 through BCPI 9 and transmits the response from 2 PM on the PC 5 through BCPI 9 and BPI 7.

In response, the MIND 6 receives the next byte of the program 2 PM and the operation repeated until a full inspection of the internal program check microcontroller 2. After receiving all the information the program on the PC 5 processes it and produces a visual result of the checked microcontroller 2. Next, you can check for other microcontroller.

Thus, the description of the work confirms the operability of the claimed device. Easy operation for the user is achieved by comparison, processing and displaying the received information. Serviceability is achieved due to the simplicity of the scheme. In addition, the device has small overall dimensions and mass properties by replacing obsolete element base on the new one.

Prototype, tests confirmed the feasibility and practical value of the proposed object.

The control device single-chip microcontroller containing the switching unit, the first output of which is connected with the first choice of the input scanned microcontroller, ROM block checked microcontroller, block RAM, personal computers and the power bus, characterized in that it introduced the control microcontroller unit serial interface, a display unit, switching unit serial interface, the processing unit initial installation of the unit address generation ROM, block address generation ROM scanned microcontroller, a decryption unit control signals, the unit reading data, the write block RAM block constants memory access check of the microcontroller, the shaping unit addresses scanned microcontroller, the processing unit initial setup of the control of the microcontroller unit reading the RAM and the block address generation RAM switching unit is equipped with input and more output, check the microcontroller is equipped with five additional inputs, two additional groups of inputs and three outputs, and the block ROM scanned microcontroller has three additional inputs and additional output, with the input and output of personal computers are connected respectively with the first output and the input of the serial interface, the second input and the output of which is connected respectively with the first output and the input of the switching unit serial interface, the second input and output to the th respectively connected with the first output and the control input of the microcontroller, the third input and output respectively connected with the first output and the second input of the scanned microcontroller, and a fourth input connected to the first input of the block constants memory access scanned microcontroller and a second output of the control of the microcontroller, a second input connected to the second output of the switching unit, the input processing unit initial installation of the unit address generation ROM, the third input of the scanned microcontroller and the first input of the display unit, the second, third, fourth and fifth inputs of which are connected to respective power bus device, the output processing unit initial installation of the unit address generation ROM connected to the first input of the block address generation ROM check the microcontroller, a second input and multiple outputs which are connected respectively with the second output of the scanned microcontroller and a group of inputs of the block ROM check the microcontroller, the input and the first auxiliary input of which is connected respectively with the third and fourth outputs of the control of the microcontroller, the fifth output of which is connected to the first auxiliary input checked microcontroller, the third output of which is connected to the input of the switching unit, the third and additional outputs which are connected respectively with the second and third additional inputs scanned microcontroller, the first additional output of which is connected with the second auxiliary input block ROM scanned microcontroller, third additional input connected to the fourth auxiliary input checked microcontroller, the first input record block RAM and the sixth output of the control of the microcontroller, the first group of outputs of which are connected with inputs of the block decoding control signals, the group of outputs of which are connected with inputs of the switching unit, the seventh and eighth outputs of the control of the microcontroller are connected respectively to the input of block read data and the second input record block RAM, ninth and tenth terminals are connected respectively with the first and second inputs of the block address generation RAM, eleventh and twelfth outputs connected respectively with the second and third inputs of the block constants memory access check of the microcontroller, the thirteenth output connected to the input of the processing unit addresses scanned microcontroller, a third input coupled to the output processing unit initial setup of the control of the microcontroller, the fourth input is connected to the output of the ROM check microcontroller, and a group of inputs connected to the group of outputs of block read data and outputs of the block RAM read, the first group of inputs which is obedinena with a group of outputs of the block RAM, and the second group of inputs connected with the first group of inputs of the block RAM and the second group of control outputs of the microcontroller, the third group of outputs of which are connected with inputs of the block constants memory access check of the microcontroller, the first group of outputs of which are connected with the first group of inputs of the scanned microcontroller and the first group of outputs of the shaping unit addresses scanned microcontroller, the second group of outputs of which are connected with the second group of inputs of the scanned microcontroller and the second group of outputs of the block constants memory access check of the microcontroller, and a group of inputs connected to the group of inputs of the block address generation RAM, the second group of inputs of the block RAM, the third group of inputs which connected to the group of outputs of the write block RAM, a third input connected to the second additional output scanned microcontroller, third additional output of which is connected to the input of the block RAM and the third input of the block address generation RAM, the fifth auxiliary input and a third group of inputs connected respectively with the additional output and outputs of the block ROM scanned microcontroller, the first group of outputs connected to the group of inputs of the block of data is read and the first group of inputs of the write block RAM, and the second, third, and che the fourth group of terminals are connected respectively with the second, the third and fourth group of inputs of the write block RAM.



 

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13 cl, 6 dwg

FIELD: electricity.

SUBSTANCE: method of testable realisation of logical converters includes initial production of initial mathematical description of operating law of functioning of n-inlet converters in testable logical basis of Zhegalkin, development and realisation of structural circuit of logical converter, detection of quantity and structure of n test signals and structure of reference signal and their generation of external technical facilities, organisation, with the help of additional external control signal, working mode of operation and mode of testing of logical converter, besides, in working mode k-argument functions AND are realised by serial chains from (k-1) two-inlet logical elements AND, every of which in mode of testing is electronically and simultaneously built up to double-digit logical elements of equivalence, which realise k-digit logical functions of equivalence above inlet arguments, such as n test M-sequences of one and the same closed class in testing mode.

EFFECT: improved testability of logical converters in testing of their proper functioning at limit working frequency.

2 dwg

FIELD: information technology.

SUBSTANCE: system has a microcontroller with built-in flash memory and two analogue-to-digital converters (ADC), a USB to UART converter, a 100 MHz generator, a microcontroller temperature sensor, 1.7 V, 2.5 V, 3.3 V and 5.0 V power supplies, a power supply selector unit, a unit for measuring current consumption, a unit for checking contact of leads of the tested RAM microcircuit chips, a converter for converting the voltage level of control input of the tested RAM microcircuit chips, a converter for converting the voltage level of the address bus of the tested RAM microcircuit chips, a personal computer (PC), a power supply, a driver, a comparator, a load for each of the n data bus lines of the tested RAM microcircuit chips, m digital temperature sensors for the RAM microcircuit chips mounted on the housing of the tested RAM microcircuit chips.

EFFECT: full functional testing of high-capacity microcircuits, possibility of inspecting several RAM microcircuit chips simultaneously, shorter testing time, cheap design and low power consumption.

3 dwg

FIELD: information technology.

SUBSTANCE: in the method, electronic models of components representing technical object are obtained, for each component, model of the component state is developed based on electronic model, technical object component state models are saved, electronic model of technical object is created based on the mentioned component state models, component state model parameter associations corresponding to defective functioning states of technical object are identified through simulation in the created electronic model of technical object, list of technical object defective functioning states and their causes is saved as model of technical object defective functioning.

EFFECT: higher quality of monitoring and controllability of complex technical objects.

15 cl, 2 dwg

FIELD: information technology.

SUBSTANCE: invention relates to testing and monitoring elements of a control system, monitoring parameters of devices performing linear conversion of signals, as well as to generation of test input data. In the method of controlling said standard of a memoryless linear system with m inputs and p outputs, n sets of test signals are transmitted in series to the input of the system, said test signals being such that a matrix X=(x1…xn), composed of values of components of said test signals, is the generating matrix for an m-dimensional random Gaussian sequence whose anisotropy does not exceed said value α. The root-mean-square value of the system gain is calculated as the square root of the ratio of the sum of squares of all p components of all output signals, corresponding to all n said input signals, to the sum of squares of all m components of all n said input signals. The obtained root-mean-square value of the system gain on said test signals is taken as the lower-bound estimate for said value of the α-anisotropic standard of the linear system and the permissibility of the value of the α-anisotropic standard of said memoryless linear system is determined based on said estimate value.

EFFECT: high reliability of determining the lower-bound estimate of the value of the α-anisotropic standard of a linear system using a fixed number of input signals.

4 cl

FIELD: information technology.

SUBSTANCE: method for automated serialisation for mass production of radioelectronic devices (RED) involves: testing operation of a RED on a wireless interface on an allocated frequency channel using a process serial number; recording a program in the RED while testing through the wireless interface, through which the programmer checks the memory read protection setting, if the read protection is removed, the process program is restored and the testing process is stopped, and if the read protection is on, the process program is replaced with the working program of the RED on a wire or wireless interface; if testing is successful, the preset value written in the memory of a counter is reduced, the housing of the RED is labelled with a barcode and a unique serial number with continuous numbering, said barcode is scanned and a unique number associated with the barcode is written in the internal memory of the controller of the RED on a wireless interface, and the RED is transferred to the working frequency channel.

EFFECT: providing guaranteed recording of a serial number from a label through a cable and a wire interface into the internal memory of a radioelectronic device controller during testing.

3 cl, 2 dwg

FIELD: aircraft engineering.

SUBSTANCE: proposed system comprises tolerance unit (TU), output completeness unit (OCU) and aircraft hardware control system with data transducer subsystem. Said units and system are connected with network of local computation circuit (LCC) connected via cell systems with network of nuclei 9. Outputs of the latter are connected with input of input unit 12, inputs of training unit 11 and tolerance unit 13. Second input of TU 13 is connected with the input of processor 16. Output of said TU 13 is connected with second input of input unit 12. Input of OCU 21 is connected with output of MLV 20. First output of OCU 21 is connected with first input of decision-making unit 17. Second output is connected with interpretation unit 22 connected in series with communication unit 18 and user's terminal 14.

EFFECT: higher efficiency of diagnostics for logical conclusion making.

1 dwg

FIELD: testing technology.

SUBSTANCE: invention relates to testing technology and can be used to diagnose functioning and determining the reliability margin of the semiconductor memory cards. The system consists of the control automatic unit, the interface controller Ethernet, the random access memory, the interface controller of semiconductor memory card, the unit of control registers, the unit of forming and measuring time parameters of the memory card interface with a resolution of 2.5 ns, the frequency multiplier based on the phase-locked loop, the control unit of input device and the display device, the unit of transceiver of the serial interface, the programmable logic integrated circuit, the microcircuit chip of transceiver of the interface Ethernet, the secondary power supply, the constant reprogrammable memory, the voltage level converter of the memory card interface, the clock signal generator 25 MHz, the input device, the display device, the temperature sensor of the memory card, the controlled power supply with the output voltage from 1 V to 5 V, the current sensor, and the contact device for connecting the semiconductor memory card.

EFFECT: ensuring the possibility of determining the reliability margin of the tested device.

1 dwg

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