Pulse shaping device
FIELD: digital pulse engineering.
SUBSTANCE: proposed device designed for shaping pulses of desired length for each of three events during power turn-on in response to off-operation button signal incorporating provision for chatter elimination in case of skip or stop of changes in input pulses on detection enabling has first and second monostable restart multivibrators 1, 4, off-operation button 2, flip-flop 3, shaper 5 of signal responding to button-provided power turn-on which is built around capacitor 12, resistors 13, 14, diode 15 and two NAND gates 6,7, as well as AND gate 8, controllable pulse generator 9, logical 1 input, pulse signal input 10, and control input 11. Controllable pulse generator 9 is built around AND gate 16, NAND gate 17, resistors 18, 19, and capacitor 20. Device can shape input pulse during power turn-on period and function as hardware watch timer implemented in the course of forward and backward automatic interaction with system microcontroller.
EFFECT: enlarged functional capabilities of device.
1 cl, 1 dwg
The invention relates to pulsed digital technology, is intended for shaping pulses of the desired duration for each of the three events (when the power is turned on, a signal from the trailing buttons with suppression of chattering; if it detects a skip or hang (stop the change of the input pulse signal when the resolution of detection) and can be used, for example, as the device  to detect the skip or hang the input pulses or device for pulse shaping setup watchdog timer for the initial installation of microprocessor systems of information processing and management, designed taking into account the following basic principles : software (firmware) control, trunk information exchange, modular construction, and capacity of computing power.
Typically, such a system contains the kernel module system formed by a quartz oscillator clock, the device for pulse shaping the initial installation, a microcontroller (or microprocessor) and the combined memory (RAM+ROM+CZU), modules functionally oriented controllers and modems for I / o information in the process of interaction of the system with external objects (operator sensor event control object, and the additional devices, adjacent systems and the like), the power supply unit and the system bus to exchange information between modules (functionally complete integral parts of the system) (see, for example,, , ). When power is applied to the pulse shaper initial setup generates a pulse initial setup enable (INOW), the duration of which (on the basis of the data presented, for example, in [5, pp. 27, 28]) can be estimated by the ratio
Top≥90 MS - setup time voltage sources of the secondary power;
Th≥50 MS duration INOW after the voltage levels of the power sources will be established, i.e. Tg determines the minimum value of the real duration of the RESET signal (RESET) when the power is turned on.
During the operation of the microprocessor system at the end of each RESET signal (RESET) components are in working condition (reset, initialized and tested under the control of microcontroller.
Currently Watchdog - the watchdog timer is becoming increasingly popular among manufacturers of microcontrollers. For example, the microcontroller from Atmel AT89S8252 the watchdog timer when the equipment is initiated by entry in the register WMCON code PS[2:0] timer period and WDTRST bit on/reset and is intended for f is Mirovaya reset on hardware level (WDTRST=1), if the application program performs uncontrolled actions, such as “hung” [6, s,108].
It should be noted that the built-in hardware watchdog timer is useful, but in General does not completely eliminate the “hang” of the system, because when you reset the microcontroller WDTRST bit because of the interference of the microcontroller and then interference may be preinitialization and “hang out”. In addition, when installing due to the noise in the PCON register bits PD (or IDL) control mode microparasite (or idling) microcontroller “hangs” at all (or at the time of termination, or until a RESET signal) - see [6, s, 95], and the output from microparasite can only be done by applying to the input of the active signal RESET - reset (initial setup) duration Tg defined by the constraint
Thus, when building a model of a modern microprocessor systems, as accepted with online access to the RESET button, and maintenance-free reset at power-up and access to the RESET button only during the debugging process, an urgent problem is the reliable automatic detection of “freezing” of the application of the kernel, and restart. In this regard, the creation of a simple device for generating RESET pulses from adinam hardware detection “freezing” of the application of the kernel (for example, due to the discovery skip or hang the input pulse signal generated by the microcontroller software with pulse frequency varying within certain limits) and the issuance of the RESET pulses with the required duration (i.e. taking into account the constraints (1) when the system is powered on and the constraints (2) pulse shaping RESET or by a signal from the trailing buttons with suppression of chattering, or when you see the “hang” of the application is an urgent technical problem.
From the point of view of the digital circuitry the proposed device belongs to “support” elements of digital components and devices , [8, pp.24-34], which, in particular, are the revealers of the loss of the input pulses , the controlled pulse generator ([7, RIS a], [8, (figure 1.15)], [9, RES, 114 ], [10, RIS, 4.10], , ), device to suppress the bounce ([7, RIS d], [8, RIS], [9, Rys a, b, C, d; RIC a, b, C; 100 [a, b, C], [10, RIS, 3.36], [13, Fig. 5.11 a, b, C], , , ), the pulse shapers initial installation on power-up ([5, RES], [10, RES]), pulse shapers, eg a series of pulses, ([10, is first two options for running the one-shot AHP with an explanation on Rish], ) and device for separation of single pulses ([18, 14-3], -), designed to convert changes asynchronously what about the input signal in a synchronous output signal, coincident with the corresponding half-cycle (or period) of the input clock signal.
Based on the simplest of the above auxiliary devices can build a device with the features offered. However, such a device will accumulate disadvantages of its component parts, which are narrow specialization or limitations on their functionality and hardware complexity when using them to build devices for pulse shaping the initial installation of modern microprocessor systems.
It is known device , which contains two elements, And the delay element, the element is NOT, the regenerator pulse sequence (formed by series-connected element OR that element of the delay and the driver, perform the function of shortening the input signal in duration), OR a counter, a decoder, the inputs of which are connected to the outputs of the counter, the reset input of which is connected to the output of the first element And the inputs of which are connected to the outputs of the delay elements and element OR the input pulse sequence, which is connected with the first inputs of the regenerator and the OR element and is connected through the element, NOT to the first input of the second element, And a second input connected to the input of the delay element and the output of the regenerator, the first impulse you the od connected to the output of the second element And the second input of the regenerator and counter input counter and the second pulse output which is the output of the decoder, which is connected to the second input of the OR element.
In the initial state, the counter is reset each input pulse with delay and shortening takes place at the exit of the regenerator and through the element does NOT prevent the second element And, in the event of a loss of momentum in the input sequence, the second element And passes the pulse from the output of the regenerator, i.e. generates a first output pulse corresponding to the lost. These pulses are counted by a counter and if the number of skipped pulses reaches a threshold, then the decoder on the second output device generates a pulse through the OR element and the first element And sets the counter to the zero state.
The main drawback of the device  is that it is with considerable hardware complexity has limited capabilities when performing its functions, as it does not detect the loss of pulses at power-up and hangup signal at the input, as in this case, the regenerator does not start.
It is known device , built on the basis of three triggers (one RS trigger and two JK triggers), element And switch closed 2 and feature 3 contacts respectively (Il the device , contains locking button D-flip-flop, three resistors and two capacitor). The main drawback of the device  (or ) is that it is relative hardware complexity performs only the function of forming a single pulse for each trip contact 2 and contact 3 (or the function of the one-bit counter for each button), and each of these devices does not provide the function of forming a single pulse at power-up. This limits the use of such technical solutions even as the simplest devices pulse shaping initial setup when building a modern microprocessor-based systems.
It is known device , containing the inputs and asynchronous clock signals, D-trigger, RS-trigger, two element AND-NOT two NOT gates, T-trigger, RC integrating circuit and the output, and the asynchronous input is connected to the information input of D-flip-flop, the first input of the first element AND-NOT and the input of the RS-flip-flop, the output of which is connected to the second input of the first element AND whose output through the first element is NOT associated with the control input of the T flip-flop, a direct output which is the output device, the input clock signal which is connected to the state clock inputs of D-flip-flop and T flip-flop, the output of D-flip-flop connected to the first input in the showing of element AND-NOT inverted output of the T flip-flop is connected to the second input of the second element AND IS NOT connected through the second element and an integrating RC circuit with a third input of the second element AND IS NOT, the output of which is connected to the reset input of the RS-trigger.
The device  works as follows.
In the initial state at zero value of the input asynchronous signal RS-trigger is selected, the D - and T-triggers reset, the outputs of the first element and the second element AND IS NOT set to zero and singular potentials, respectively. Switching input asynchronous signal from “0” to “1” in the device causes the switching output of the first element does NOT signal “0” to “1”. Next, on the first slice clock input triggers D and T are set to the output device exhibits a signal “1”on the first and third (with a delay less than the repetition period of the clock pulse) inputs of the second element AND NOT see the signal “1”, and the second edge of the clock input of the flip-flop is reset, the second element AND generates the inverse of the pulse duration is determined mainly by the parameters of the integrating RC circuit), leaving RS-flip-flop, the output of which a signal of logical “0” passes through the first elements And NOT and NOT on the control input of the T flip-flop and disables its operation on the input clock signal is Lou. Thus, for each change of the input asynchronous signal from “0” to “1” and while maintaining this state for at least two periods of the repetition frequency of the clock input the device  enables the generation of a single pulse with a duration equal to the repetition period of the clock signal.
The main drawback of the device  is that it is relative hardware complexity (contains three trigger different types) has limited functionality (only performs the function of forming a single pulse for each change of the input asynchronous signal from “0” to “1”), due to a lack of full functionality of its constituent parts.
Known technical solutions closest to the present invention is the device , containing the one-shot (waiting multivibrator formed by the active element, a resistor and a timing RC circuit connected to the two inputs of the active element and to the bus power source connected through a resistor to the input of the start of the active element, which is the negative input of the start of the one-shot, direct and inverted outputs of which are the direct and inverse outputs of the active element), direct and inverted outputs, which is the direct and inverse outputs the one-shot,and a closing button the first contact which is connected to a common bus, and a second contact connected to the negative input of the start of the one-shot.
The device  on the one-shot (restart with or without restarting) with a great time (of the order of a few tenths of a second) reliably suppress spurious pulses due to contact bounce, and forms an ideal pulses on any press button closing.
It is known [8, s]that contact bounce button closing duration 1...10 MS occurs as pressing and releasing. In this regard, the main drawback of the device  is limited its functionality because it does not produce an output signal on power and ambiguous generates an output signal depending on the length of time the button is pressed, as a mobile device when the duration time is pressed, lesser (or greater) time the one-shot produces one pulse (or two pulse, i.e. the first pressing, and the second button is released).
The invention solves the problem of the complex extension of functional capabilities of the device due to the formation of the output pulse at power-up taking into account the constraints (1) and can be run on the device hardware watchdog tie the EPA to permit formation of the output pulse taking into account the constraints (2) when skipping or lag pulses of the input pulse signal, coming to the device, e.g., microcontroller, microprocessor-controlled systems.
To achieve this, the technical result in the apparatus for forming a pulse containing a first one-shot with restart, direct and inverted outputs the generated pulse and a closing button, the first contact which is connected to a shared bus, entered the trigger, the second one-shot with a restart, the driver signal to power on and off button, an input connected to the second contact closing button, and the output is connected to the asynchronous inverted input setup trigger, the first item, the first input connected to the inverse output of the first one-shot, the second AND gate, a first input connected to the information input trigger and inverse outputs of the trigger device, direct the output of which is a direct output of the trigger element And the first input connected to the inverse output of the second one-shot, a controlled pulse generator, a control input connected to the output element, And the pulse output is connected to synchronator trigger and an inverted reset input of the second one-shot, the input pulse signal, which is the direct input of the launch of the first one-shot, and a control input, which is the second input of the first element AND IS NOT, the output of which is on connected to a second input of the second element AND-NOT the output of which is connected with the second input element And, with inverted inputs run both odnovorov connected to a common bus devices, the bus is a Logical 1 which is connected to the inverted reset inputs of the trigger and the first one-shot and the direct input of the start of the second one-shot.
Author unknown solutions containing characteristics equivalent to distinguishing characteristics, the introduction of a trigger, the second one-shot with a restart, the driver signal to power on and off button, two elements, element And controlled pulse generator, the input pulse signal and the control input) of the proposed device, which (compared with the prototype ) comprehensively extend the functionality of the device by generating a pulse at power-up and enable the execution device function hardware watchdog timer to permit formation of the output pulse skipping or lag pulses of the input pulse signal coming to the device, for example, from the microcontroller served or unserved microprocessor systems.
The drawing shows a functional diagram of the device for forming a pulse containing a first one-shot 1 restart, direct and Inverclyde generated pulse, closing the switch 2, the first contact which is connected to a shared bus device, the trigger 3, the second one-shot 4 is restarted, the driver 5 signal power-on and off the button, the input of which is connected with the second contact closing button, and the output is connected to an asynchronous negative input setup trigger 3, the first element 6 AND the first input connected to an inverted output of the one-shot 1, the second element 7 AND IS NOT, the first input connected to the information input of the trigger 3 and inverse outputs of the trigger 3 and the device, direct the output of which is a direct output of the trigger 3, the element 8 And the first input connected to an inverted output of the one-shot 4, the controlled pulse generator 9, a control input connected to the output element 8, And the pulse output is connected to synchronator trigger 3 and the inverted reset input of the one-shot 4, entry 10 pulse signal, which is the direct input of the start of the one-shot 1, and a control input 11, which is the second input element 6 AND IS NOT, the output of which is connected with the second input element 7 AND IS NOT, the output of which is connected with the second input element 8 And inverted inputs of the start of odnovorov 1 and 4 connected to a common bus devices, the bus is a Logical 1 which is connected to the inverted reset inputs of one-shot 1 and the trigger 3 and the direct input zaustaviti 4.
Possible variant of the imaging unit 5 is implemented as a lowpass filter on the basis of technical solutions [13, p.160, Risa] and contains the first capacitor 12, the first 13 and second 14 resistors, diode 15, the input connected to the first terminals of the resistors 13 and 14, and the output connected to the first output capacitor 12, a second output resistor 13 and the anode of the diode 15, the cathode of which is connected with the second output of the resistor 14 and the bus of the power source device, a common bus which is connected to the second lead of the capacitor 12.
The generator 9 is made on the basis of technical solutions [9, pp.62, RIS] and contains the element 16 logical repetition of the signal on the base element And the third element 17 AND the third 18 and fourth resistors 19, the second capacitor 20, a control input, the first input element 17, and a pulse output connected to the first output resistor 18 and the output element 17, a second input connected to the first output capacitor 20 and the output element 16, the inputs of which are connected with the first output resistor 19, the second conclusion which connected with the second terminals of the resistor 18 and capacitor 20.
The trigger 3 and all the logical elements of the device are made in CMOS integrated circuits series 1554 (trigger 3 is 0.5 chips TM2, items 6, 7 and 17 AND NOT take 0,75 chip LA, items 8 and 16, And occupy 0.5 chip is I1), operating supply voltage range from +2 to +6 V and the input current from -1 to +1 µa - see, for example, [25, p.15 and on p.21 table 3.1]. In this regard, the imaging unit 5 introduced the diode 15 to accelerate the discharge of the capacitor 12 when the power is turned off and reduce the discharge current through the protective diode on the input set trigger 3 as part of an integrated CMOS TM, and the generator 9 is entered resistor 19 to recommendations [13, C] to reduce currents flowing when recharging of the capacitor 20 through the protective diode element 16 And the integrated CMOS LI.
Each one-shot 1 (or 4) is implemented on the half integral TTL circuits AHP, for example, a series of 1533 (or 533), the matching resistor and the timing capacitor and the resistor, and the first output breathalyser capacitor connected to one of the inputs “With” chips corresponding to the RC input of which is connected with the second output capacitor and the first output breathalyser resistor, the second terminal of which is connected to the bus voltage and the first output matching resistor, the second terminal of which is connected to an inverted output of the one-shot 1 (or 4), which is the corresponding inverse output circuits corresponding to the inputs are inverted reset input and direct and inverse inputs of the launch of the one-shot 1 (or 4), in which Soglasiye the resistor serves for interfacing TTL output with the first CMOS input element 6 (or 8).
Further description of the operation of the device is through a system of terms and symbols defined in the following paragraphs.
1. Modified the description language of logic functions ABEL, in which the operators “AND”, “OR” and “NOT” are designated as “&”, “#” and “!” (or “N”), respectively.
2. The signals at the inputs 10 and 11 denote by SH and X11, respectively, and direct (or inverse) signal at the output of any element of the device will denote by Yj (or NYj), where j is the element number of the device in the figure. For example, Y3 and NY3 signals generated respectively at the forward and inverse outputs of the trigger 3 (i.e. the outputs of the device). The duration of a single signal NY3=0, NY4=0, NY5=0 and NY9=0 denote by T3, T4, T5 and T9, respectively.
3. Under the front or cut any signal (direct or inverse) is the change of the logical state of the signal from “0” to “1” or from “1” to “0”, respectively.
4. The one-shot 1 is started (or restarted) on the front of the clock signal SH, and the front of the pulse NY9=NY17 generator 9 starts the one-shot 4 and NY5=1 trigger 3 is switched to the opposite state, and when NY5=0 trigger 3 asynchronously set and produces signals Y3=1 and NY3=0.
5. According to [10, pp.118] for the one-shot 1 (or 4), the duration t of the pulse is estimated by the formula
and restart the one-shot 1 is only possible when the period T10 pulse signal SH restriction
The capacitance value breathalyser capacitor;
R is the resistance value breathalyser resistor within from 5.1 kω 51 kω;
• - hereinafter the operator arithmetic operation of multiplication.
The time interval T or T10 is measured in microseconds, if the container is measured in nanofarad, the resistance R in ohms.
6. When building a device that contains an integrating RC circuit and/or shorten CR circuit connected to the input of logic element, there occurs a problem of evaluation time expires Ter. logic element when the signal change at the input RC (or CR)-chain from “0” to “1” or from “1” to “0”. It is easy to see that the time Ter. is determined by the time constant T=C•R circuit and the threshold Uop. actuation logic element, for which a CMOS element is close to half of the voltage u pit. power (see, for example, [9, p.58])
≈ - hereinafter sign of approximate equality.
According to [25, 67, 68], taking into account (5), the time Tavg. can be estimated by the formula
how to shorten the chain, and an integrating circuit, as the active permanent the ability of the output pulse shorten the chain is measured at the level represents half of the amplitude and to the integrating circuit formula (6) defines the time change of the output signal of the circuit from the source level to the level of half of a step change of the input signal.
Taking into account the accepted system of terms and notation we will first describe the operation of the device components or some of the aggregates, and then its functioning as a whole.
The one-shot 1 works as a shaper envelope of the input pulse signal SH (see [10, p.116 is first start the one-shot AHP with an explanation rig on pp.118]) when performing limit
where T and T10 are defined by expressions (3) and (4) respectively. When running the constraints (7) in the one-shot is implemented property is restarted, namely, that with each new front signal SH the one-shot 1 starts counting the new time T regardless of the results of the previous time. In this regard, the one-shot 1 signal SH operates so that provides an output signal NY1=0 at a repetition frequency f=1/T10 signal SH that satisfy the constraint (7), otherwise the signal NY1 appear transitions from “0” to “1” and from “1” to “0”and hangs (constant signal SH=0 or SK=1) one-shot 1 exhibits SIG is al NY1=1.
Shaper 5 at power-up and button 2 works as follows.
When the power is off, the capacitor 12 is discharged and open button 2 and the power supply starts to charge through resistance (R13 + R14) with a constant time T12=C12•(R13+R14) and generate an output signal UC12=U5, as measured by the ratio to the input set trigger 3 as a digital signal NY5, according to expressions
From (1), (6) and (8) it follows that the value of R12, R13 and R14 have to choose from the condition
Tvcl. - the length of time after switching on u n and m., during which the trigger 3, according to (8), perceives from the output of the shaper 5 voltage U5 as a digital signal NY5=0.
After the transition of power to the capacitor C12 is set to the voltage UC12≈u pit.≈+5V, and pressing button 2, the capacitor C12 is discharged through the resistor R13 and the 2 connected to the common bus. In this case, the operation of the imaging unit 5 can be described by the expression
TDR. - the duration of the bounce button 2 has been pressed or released.
From (6), (11) and (12) it follows that to eliminate chattering of the contacts button 2 values of R12 and R13 can be selected on the basis of limitations
When the power is turned off, the capacitor C12 is quickly discharged through the diode 15 and the protective diode trigger 3 input set.
Trigger 3 on signals NY5 and NY9 operates as follows. When NY5=0 trigger 3 is fixed in a single state (produces direct and inverse outputs signals Y3=1 and NY3=0, respectively), while NY5=1 trigger 3 on the front of the signal NY9 switches to the opposite state.
The one-shot 4 runs on each front signal NY9 (see [10, p.116 is - the third option of running the one-shot AHP]) and produces a signal NY4=0 during the time
Items 6, 7 and 8 on signals X11, NY1, NY3 and NY4 produce a signal Y8 control generator 9 according to the expression
so that Y8=1 when NY4=1 and Y3=1 or (X11&NY1)=1, and in all other cases, Y8=0 and X11=0
When Y8=0 at the output of the generator 9 produces a signal NY9=NY17=1, the element 16 produces a signal Y16=1, the capacitor 20 is discharged (i.e. UC20≈0), since U16≈U17≈u pit.≈+5B, where the U16 and U17 - voltages at the outputs of the elements 16 and 17 respectively. Voltage UC20 is measured here and further on the second terminal of the capacitor C20 with respect to its first output connected to the output element 16. With the change of the signal Y8 from “0” to “1” is allowed the use of the generator 9,the elements 17 and 16 respectively produce voltage U17≈ 0 In (i.e. NY17=0) and U16≈+5B (ie Y16=1) and to the input of the element 16 through the resistor 19 signal U16≈+5B decrease with RC-chain (C20 and R18). In this regard, at Y8=1 through time T9 pulse duration NY9=0, evaluate the expression
work items 16 and 17 (produce voltage U16≈, 0V and U17≈+5B), starts the one-shot 4, produces a signal NY4=0 duration T4, which through the element 8 captures the element 17 of the generator 9 in the state NY17=1. Thus, when U17≈+5B, U16≈, 0V and UC20=-U.≈-2,5 begins In the recovery process of the generator 9 in the initial state voltage U17≈+5V, consisting of two stages. At the first stage, the recharging of the capacitor C20 from “Uop.” to “+Uop.” and the actuation element 16, i.e. the setting of its output voltage U16≈+5B, and the second step is the change in the voltage on the capacitor C20 from UC20=+Uop. to UC20≈, 0V and the return of the generator 9 to its original state.
The device can distinguish driven signal Y7 ring oscillator (one-shot 4, item 8, the generator 9), the generation of which at Y7=0 is forbidden, and at Y7=1 is allowed, so that each front signal Y8=NY4=1 starts the generator 9 generates a pulse NY9=0 duration T9, each edge of which runs one-shot 4 and generates a pulse NY4=0 dlitelnost the Yu T4> >T9, see (14) and (17).
Based on the above describe sequentially the operation of the device as a whole upon the occurrence of each of the following three events: a power supply; a circuit button 2; the discovery skip or hang the input pulse signal SH when X11=1, allowing the detection.
Before inclusion u n and m.=UC12=0, NY5=0 and button 2 is open. By turning the power off after a few tens of milliseconds when reaching u pit. value >2V trigger 3 starts to operate steadily and signal NY5=0, duration Tvcl.=(Tip+Th)>140 MS (see (10) and (1)), the trigger 3 is fixed in a single state and produces direct Y3=1 and the inverse NY3=0 output signals of the device. Then through time Tip≥90 MS u pit. almost set (i.e. is determined by the expression u n and m.=+(5±0,5)≈+5 V) and the period Tr1≥50 MS when NY5=0, from which all component parts of the device are stable in the following way.
During Th signals NY3=0 and NY4 elements 7 and 8 form the signal Y8=NY4 permission of operation of the ring oscillator (the one-shot 4, item 8 and the generator 9) with the period
pulse NY9 (or NY4) so that the edge of each signal NY9=0 (or Y8=NY4=0) duration T9 (or T4) starts the one-shot 4 (or generator 9). In some the first time at the end Th trigger 3 perceives from the output of the shaper 5 voltage U5 as a digital signal NY5=1 and edge of the next pulse NY9=0 triggers the one-shot 4 switches from “1” to “0” and put direct and inverse outputs signals Y3=0 and NY3=1, respectively.
The microprocessor interprets the output signal Y3 (and/or NY3) as a direct (and/or inverse) a RESET signal (RESET), after which it can be initialized during the time tin.<T4 (see (14)) so that when X11=1 microcontroller system begins to programmatically generate a pulse signal SH received at the input device 10. When the correct functioning of the system kernel the period T10 of the frequency f of the pulse signal SH must satisfy the constraint (7). When addressing the frequency f of the pulse signal SH the constraint (7) one-shot 1 generates a signal NY1=0, item 6 signal Y6=(!X11#Y1)=1, the element 7 when NY3=1 - signal X7=(!Y6#Y3)=0, which breaks the ring oscillator prohibition passing through the element 8 front signal NY4=0, since this front produced already at Y7=0.
Thus, at the end of the described process of switching the supply voltage u pit. and the correct functioning of the microprocessor system (or if X11=0) the device enters a steady state (CA)
If the device is in a stable state (19), pressing button 2 during the time TNA.>30ms≥3•TDR. after about time TDR.+0,7•C12•R13 driver 5 generates a signal NY5=0, which in use is e time TNA.> 10 MS (see(11), (12), (13)) asynchronously sets the trigger 3. The signal NY3=0 trigger 3 item 7 exhibits a signal Y7=1, authorizing the operation of the ring oscillator (generator 9, item 8, the one-shot 4). Further, the device functions the same as when the power supply voltage, since Tg and maintaining a single state trigger 3 over time
When X11=1, the device being in steady state (19) when not pressed button 2 functions as a hardware watchdog timer, so that when dissatisfaction with the duration of the period T10 of the pulse repetition frequency of the input pulse signal SH the constraint (7) one-shot 1 is switched to the standby mode and signal exhibits NY1=1, which through the elements 6 and 7 enables the ring oscillator (the one-shot 4, item 8, of the generator 9), the wavefronts NY9=0 which trigger 3 is switched so that the first pulse it will be installed on time
develop direct and inverse RESET signal (Y3=1, NY3=0), and the second switch in the zero state and restarts the microprocessor system. Further operation of the device (if u pit.≈+5 V and not the pressed button 2) is completely determined by the behavior of the pulse signal SH as a function of time, the program is about generated by the microcontroller is a microprocessor-based system.
The detection of the one-shot 1 skip or hang pulse signal SH (formation of a one-shot 1 signal NY1=1) if X11=0 device not working. This allows debugging of microprocessor-based system to operate the system from the emulator MCU in step-by-step mode when the signal X11=0, prohibiting the operation of the device as a hardware watchdog timer.
Thus, the proposed device, thanks to its essential features, has broader functionality by generating a pulse when the power is turned on taking into account the constraints (1), implemented in the form of constraints (10)and can be run on the device hardware watchdog timer resolution generate an output pulse when X11=1 with the constraints (2), implemented in the form of constraints (21) when skipping or lag pulses of the input pulse signal SG input to the device, e.g., microcontroller, microprocessor-controlled systems. In this connection, this device can be used directly when building the attended and unattended modern microprocessor-based systems, and, if X11=1, can be used as a device type  for the detection of skip and hang the input pulses.
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Apparatus for forming a pulse containing a first one-shot with restart, direct and inverted outputs the generated pulse and a closing button, the first contact which is connected to common bus, device, characterized in that it further comprises a trigger, a second one-shot with a restart, the driver signal to power on and off button, an input connected to the second contact closing button, and the output is connected to the asynchronous inverted input set trigger, the first item, the first input connected to the inverse output of the first one-shot, the second element AND the first input of which is connected in ormational input trigger and inverse outputs of the trigger device, direct the output of which is connected to the direct output of the trigger element And the first input connected to the inverse output of the second one-shot, a controlled pulse generator, a control input connected to the output element, And the pulse output is connected to synchronator trigger and the reset input of the second one-shot, the input pulse signal, which is the direct input of the launch of the first one-shot, and a control input, which is the second input of the first element AND whose output is connected to a second input of the second element AND IS NOT, the output of which is connected with the second input element And, with inverted inputs run both connected odnovorov with a shared bus devices, the bus Logic of the first device is connected to an inverted reset inputs of the trigger and the first one-shot, and the direct input of the start of the second one-shot.
FIELD: pulse engineering; building various digital devices.
SUBSTANCE: proposed device has two D flip-flops, double-input OR gate, input and output buses, synchronization bus, and zeroing input. Pulses whose length equals repetition period of sync pulses and generation time coincides with time of pulse arrival at input bus are generated across output bus in the course of device operation.
EFFECT: simplified design of device.
1 cl, 2 dwg