Pseudo-associative processor

FIELD: computers.

SUBSTANCE: processor has a pseudo-associative device, consisting of two memory blocks, interconnected through transposing circuit.

EFFECT: higher productiveness, higher efficiency.

2 dwg, 2 tbl

 

The invention relates to the field of computer engineering and can be used in information retrieval systems and database machines.

Known associative processor (AP)containing associative memory (ABC) on the row of the storage matrix and the bit slices, each of which contains the same bits of all rows. In the AP also includes buffer I / o register of the comparand registers storing answers (bullets), the comparison logic bits of the comparand with the bit slices and a control unit (controller), which provides addressing of rows and sections, controls reading and writing ABC and comparison operations. Similar processors, and incoming them in ABC described in the literature[1, 2, 3].

The disadvantage of such processors are the complexity and high cost of associative memory, which does not allow to have ABC high capacity and ultimately reduces the speed of operations.

The proposed solution contains a buffer I / o, the comparand register, the block diagrams compare unit registers markers and the controller. Buffer I / o connected to the external bus of the processor, the first input of the block diagrams of comparison is connected to the output of the comparand register, the output of block diagrams of comparison is connected to the input of the register unit markers, the second output of which is connected to the input of the control of the EPA, the first output of which is connected with the control input of the block diagrams of comparison. The processor is characterized in that it additionally includes two memory block, the first of them is connected to the buffer input / output, the output of the second memory block is connected with the second input of the block diagrams of the comparison, the control inputs of memory blocks connected to the second and third outputs of the controller, the control output register unit markers connected to the input of the recording of the second memory block, the control input circuit terminal connected to the fourth output of the controller.

The first and second memory blocks are interconnected via a scheme of transposition, containing two 64-bit register with shift circuits respectively 8 and 1 bit to the left, multiplexer and demultiplexer, and two inputs of the multiplexer are connected respectively with the byte outputs of the first and second memory blocks, and the two outputs of the demultiplexer are connected respectively to the byte inputs of the first and second memory blocks, the output of the multiplexer is connected to the input lower byte of the first shift register, the output of the first register is connected to the input of the second register, the input bits of the demultiplexer are connected respectively to the outputs of the high-order bits of the eight bytes of the second shift register.

The proposed technical solution, the role of ABC are two of the memory block address is a start, one of which plays the role of memory rows, and the second is the role of memory slices. The memory string is converted in memory of stripes (or Vice versa) by transposition, after which the bit slices become available as a regular expression.

Transposition can be done in code, but this requires a large investment of time. To reduce part of the processor introduces a scheme of transposition of eight bytes, to be included in the circuit of exchange between the memory blocks.

A set of two memory blocks and diagrams transpose forms pseudoisocyanine memory and uses its processor is pseudoisocyanine processor.

Consider the example of the transposition memory matrix containing 16 to 24-bit (3-byte) words. In table. 1 shows the structure of a matrix and its generalized representation, where aijbijcijdijfij, gij- eights bits of the bytes a, b, C, D, F, G, respectively. In table. 2 shows the structure of the transposed matrix, consisting of transposed eights bytes AndTInTWithTDT, FT, GT. The matrix contains 24 16-bit slice.

Scheme of the proposed processor is shown in figure 1, where 1 buffer I / o, 2 - first memory block, 3 - second memory block, 4 - circuit terminal, 5 - comparand register, 6 - block schemes comparison, the 7 - block registration of the s markers, 8 - controller.

Unit 6 compares bits of the comparand with the bit slice by the number of binary bits of the slice.

The first memory block 2 is connected through a buffer 1 to the external processor bus. Byte output unit 2 through the circuit 4 is connected to the byte input block 3, byte output of which is connected through the circuit 4 byte input unit 2. Sredny output unit 3 connected to the first input unit 6, the second input is connected to the output of the register 5, the output unit 6 is connected to the input of block markers 7, the first output of which is connected to the input of the recording sections of the memory unit 3 and the second output unit 7 is connected to the input of the controller 8, the outputs of which are connected to control inputs of blocks 2, 3, 4, 6, respectively.

On the contents of the first memory block are read, write, and modify strings. On the second block of memory search operations are performed with a mark in the row handles, attributes which satisfy the given conditions of the comparison. We can also perform some arithmetic and special operations, such as finding the maximum or minimum.

The execution of these operations is similar to that executed in the usual associative processors and therefore not described in detail.

A more detailed look at the diagram of transposition (figure 2) and the procedure for its work. The schema contains a 64-bit register 10 with the goal of TS the yoke 8 bits to the left 64-bit register 11 to shift 1 bit to the left, the multiplexer 9 and the demultiplexer 12. The inputs of the multiplexer are connected with byte outputs of the first and second memory blocks, respectively, and the outputs of the demultiplexer - byte inputs of these blocks. The output of the multiplexer 9 is connected to the input lower byte of the register 10, the output of which is connected to the input of the register 11. The input of the demultiplexer 12 is connected to the outputs of the bits of the bytes of the register 11 (bits 7, 15, 23, 31, 39, 47).

The operation of the circuit will consider for the case of transmission with transposition of the memory block 2 in the memory unit 3. The bytes of the next eight bytes from the block 2 through the multiplexer 9 are received in the lower byte of the register 11 and through shifts 8 bits fill this register. After that, the contents of register 10 is transferred to the register 11 and register 10 is loaded, the next eight bytes. Bytes generated from the left bits of the bytes of the register 11 through the demultiplexer 12 is transferred to the memory unit 3, and then the shift register 11 by 1 bit to the left. Then output the next byte, and so on, the Combination of input and output allows you to perform a transposition in almost the same time as usual byte-by-byte exchange with delay boot time one of eight bytes.

Transfer with transposition of the memory block 3 block 2 is the same.

Positive E. the effect from the application of the proposed technical solution is the removal of restrictions on capacity pseudoisocyanine memory and improve the performance of the processor, the value of which depends on the number of bits processed simultaneously cut. In addition, it is possible to combine the operations performed in two blocks of memory.

Literature:

1. Computers on VLSI: KN. 2. - Lane. with jap. - M.: Mir, 1988. P. 272.

2. Myers, the Architecture of modern computers: the book. 2. - Lane. from English. - M.: Mir,1985. GL.

3. Ozkarahan E. Machine databases and database management. TRANS. from English. - M.: Mir, 1989, 5.2, 5.3, 6.3 (prototype, s, Fig. 6.19).

Pseudoisocyanine processor containing buffer I / o, the comparand register, the block diagrams compare unit registers markers and the controller buffer I / o connected to the external bus of the processor, the first input of the block diagrams of comparison is connected to the output of the comparand register, the output of block diagrams of comparison is connected to the input of the register unit markers, the second output of which is connected to the input of the controller, the first output of which is connected with the control input of the block diagrams of comparison, characterized in that it additionally introduced two memory block, the first of which is connected to the buffer input / output, the output of the second memory block is connected with the second input of the block diagrams of the comparison, the control inputs of memory blocks connected respectively to the second and third outputs, the first output unit into the ditch markers connected to the input of the recording of the second memory block, and the first and second memory blocks are interconnected via a scheme of transposition, containing two 64-bit register with shift circuits respectively 8 bits and 1 bit to the left, multiplexer and demultiplexer, and two inputs of the multiplexer are connected respectively with the byte outputs of the first and second memory blocks, and the two outputs of the demultiplexer are connected respectively to the byte inputs of the first and second memory blocks, the output of the multiplexer is connected to the input lower byte of the first shift register, the output of the first shift register connected to the input of the second shift register, the input bits of the demultiplexer are connected respectively to the outputs eight bits of the second byte the shift register control input circuit terminal connected to the output of the controller.



 

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