Correlation time delay discriminator

FIELD: specialized information extracting means.

SUBSTANCE: device has displacement registers, comparator block, XOR element, multiplexer, triggers, counter, AND elements.

EFFECT: simplified construction.

1 dwg

 

The invention relates to specialized tools to extract information and can be used to estimate the time relative delay between the two pseudorandom sequences.

The prototype of the invention is the correlation discriminator delay time, containing two shift register block comparison group, XOR-and NOT the element), the EXCLUSIVE OR element, two triggers, two counters, one-shot, the four elements And the element OR, with the information input of the first shift register is the first information input of the discriminator, the second information input of which is the first input of the first element OR a clock input of the discriminator serves as the clock input of the second shift register, the bit outputs of the first and second shift registers connected respectively with the first and second inputs of the block comparison, the output of which is connected with the input of one-shot, the output of which is connected to alnoaimi the inputs of the shift registers, the first counter and the first flip-flop, the second input of the first element And is connected to the direct output of the second trigger and the first input of the second element And a second input connected to a clock input of the second shift register and the output of the second element And is connected to a clock input of the first shift register and the accounts of Photomerge counter, the output of the first element And connected to the first input member OR the output of which is connected to the information input of the second shift register, the second input element OR is connected to the output of the third element And the first input connected to the inverse output of the second trigger, set input connected to boleushim input of the second counter and is a control input of the discriminator, the counting input of a second counter connected to the output of the fourth element And the first input connected to the direct output of the first flip-flop, the second input of the fourth element And is connected to a clock input of the discriminator, the output of the overflow of the first counter is connected to boleushim input of the second trigger and installation input of the first trigger, a second input of the third element And is connected to the output of the EXCLUSIVE OR element, the input of which is connected to respective outputs of the second shift register, the bit outputs of the second counter are exit discriminator [A.S. USSR №1413643. Publ. in BI, 1988, No. 28].

The disadvantage of the prototype is hardware redundancy.

Technical result achieved when using the present invention, apparatus is simplified while maintaining the same accuracy and speed of calculations required parameter.

The technical result is achieved by the fact that the correlation discriminator delay time, contains two shift register block comparison, two trigger, counter, EXCLUSIVE OR element and two elements And information input of the first shift register is the first information input of the discriminator, a clock input which serves as the clock input of the second shift register, the bit outputs of the first and second shift registers connected respectively with the first and second inputs of the block comparison, the inputs of the EXCLUSIVE OR element connected to the outputs of the second shift register according to the rule of formation of the pseudo-random sequence, the clock input of the first shift register connected to the output of the first element And the first input of which is combined with the first input of the second element And connected to clock input of the discriminator, managing input of which is the installation input of the first trigger to the control input of the discriminator is connected Abdoulaye the counter input summing input connected to the output of the second element And a second input connected to the output of the second trigger, bit outputs of the counter are the outputs of the discriminator according to the invention introduced the multiplexer, the output of which is connected to the information input of the second shift register, the first data input of the multiplexer is the second information input of the discriminator, the second information shall include the multiplexer input coupled to the output of the EXCLUSIVE OR element, the address multiplexer input coupled to the output of the second trigger, the D-input connected to the output of the first trigger, Abdoulaye an input connected to the output of the Comparer, the clock input of the second trigger is connected to a clock input of the discriminator, and inverting the output of the second trigger is connected with the second input of the first element I.

The invention is illustrated in the drawing, which shows a functional diagram of the correlation discriminator delay time.

Functional diagram contains the registers 1, 2 shift, block 3 comparison (comparator binary numbers), the EXCLUSIVE OR element 4, a multiplexer 5, triggers, 6, 7, a counter 8, elements 9, 10. Information input D of the register 2 is the first information input x(t) discriminator, the second information input y(t) which is the first information input of the multiplexer 5, the output of which is connected with the information input D of the register 1, the clock input which serves as a clock input CLK of the discriminator, the bit outputs of the registers 1, 2 are connected respectively with the first and second inputs of unit 3 of the comparison, the output of which is connected to boleushim input of the trigger 6, the output of which is connected to the D input of the trigger 7, a clock input which is combined with the first input element And 10 and is connected to a clock the input of the discriminator, the output of the trigger 7 is connected with the joint address input of the multiplexer 5 and the second input element 10, the second information input of the multiplexer 5 is connected to the output of the EXCLUSIVE OR element 4, the inputs of which are connected with the bit outputs of the register 1 according to the rule of formation of the studied pseudo-random sequence, inverting the output of the trigger 7 is connected with one input element And 9, the other input of which is connected to the clock input of the discriminator, and the output connected to a clock input of the register 2, the managing input FROM the discriminator is the installation log trigger 6, combined with boleushim input of the counter 8, summing input connected to the output element And 10, the bit outputs of the counter 8 are output code delay nτ discriminator.

Has a discriminator as follows.

For informational inputs x(f) and y(f) are respectively the forward and trailing pseudo-random sequence with the relative time-shift τ. In the initial state, to feed the input WITH trigger pulse, the registers 1, 2 continuously aktiruyte, and coming to their information inputs symbols of pseudo-random sequences continuously and consistently recorded in the cell. Thus, at any clock time on the bit outputs of the registers 1, 2 will be presented segments of pseudo-random sequences, arriving at the inputs x(t), y(f) discrim is the General.

For a start delay measurementsat the entrance serves a triggering pulse in response to the trigger 6 enters state high logic level at the D input of the trigger 7 is also set to a high logic level and negative edge of the clock pulse from input CLK trigger 7 changes its state. The transition trigger 7 in the condition of high logical level leads, first, to the switching of the multiplexer 5 and, secondly, to supply clock pulses to the clock input of the register 2. The result in the register 2 is stored one of the segments of the advanced pseudo-random sequence, which then will serve as a reference. The switching of the multiplexer 5 leads to switching on the information input register 1 output of the EXCLUSIVE OR element 4, but since clocking of the register 1, in contrast to case 2, is not interrupted, then the case 1 is covered by the feedback, should be considered as a pseudo-random sequence generator. Organized at the time of measurement, the generator starts potato to form the segments of the pseudo-random sequence in accordance with the rule defined for the studied pseudo-random sequences. The original segment is last recorded in the register 1 fragment. After the time τ * on the outputs of the register 1 is formed segment, identical reference stored in the register 2.

The search time τ* counted by the counter 8 by the number of clock pulses required for formation of a segment of the pseudo-random sequence that is identical to the reference. When bit full equality segments are fed to the inputs of unit 3 of the comparison, the output of the specified block is formed, the voltage drop, resulting in the resetting of the trigger 6. Next on the negative edge of the first after the reset of the trigger 6 clock pulse trigger 7 also establishes at its output a logic low and the supply of clock pulses to a summing input of the counter 8 is stopped, and his bit outputs fixed code delay nτ. At a known repetition period of the clock pulses T0CLK calculate time τ*=T0nτ.

With the filing of the next trigger pulse FROM the counter 8 is reset and the measurement cycle is repeated.

Feature discriminator, as well as the prototype, is the need for a priori knowledge of the rules of formation of the studied pseudo-random sequences, asked for a k-bit registers 1, 2 the characteristic polynomial of the k-th degree

F(x)=a0xk+a1xk-1+...+ak-1x+ak,

where a0,..., ak- coefficie what you're polynomial, taking values 0 or 1.

The values of the coefficients of the polynomial determines the connection point of feedback to the bits of the register 1, as well as the required number of inputs of the EXCLUSIVE OR element 4 [Avanesyan BORN, Seleznev A.S. Generator identical sequences, each separated in time. - Instruments and experimental techniques, 1989, No. 1, pp. 104-106]. Therefore, in the General case, the EXCLUSIVE OR element 4 can have two inputs, as shown in the figure, and more depending on the form of the characteristic polynomial (number of inputs equal to the number of coefficients and equal to one).

Correlation discriminator delay time, containing two shift register block comparison, two trigger, counter, EXCLUSIVE OR element and two elements And information input of the first shift register is the first information input of the discriminator, a clock input which serves as the clock input of the second shift register, the bit outputs of the first and second shift registers connected respectively with the first and second inputs of the block comparison, the inputs of the EXCLUSIVE OR element connected to the outputs of the second shift register according to the rule of formation of the pseudo-random sequence, the clock input of the first shift register connected to the output of the first element And the first input of which is combined with the first is the progress the second element And is connected to the clock input of the discriminator, managing input of which is the installation input of the first trigger to the control input of the discriminator is connected Abdoulaye the counter input summing input connected to the output of the second element And a second input connected to the output of the second trigger, bit outputs of the counter are the outputs of the discriminator, characterized in that it introduced the multiplexer, the output of which is connected to the information input of the second shift register, the first data input of the multiplexer is the second information input of the discriminator, the second information input of the multiplexer is connected to the output of the EXCLUSIVE OR element, the address multiplexer input coupled to the output of the second trigger, the D-input connected to the output the first trigger, Abdoulaye an input connected to the output of the Comparer, the clock input of the second trigger is connected to a clock input of the discriminator, and inverting the output of the second trigger is connected with the second input of the first element I.



 

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