System for data transfer for governmental population recording system

FIELD: computers.

SUBSTANCE: system has nine registers, four address selectors, triggers, AND elements, OR elements and delay elements.

EFFECT: higher speed.

8 dwg

 

The invention relates to computer technology, in particular to the transmission system automated information system “State register of population”.

Known systems that could be used to solve the task [1, 2].

The first of the known systems contains blocks receiving and storing data, connected to the control blocks and data blocks search and selection, connected to the blocks of the data storage and display, the clock inputs are connected to outputs of control unit [1].

A significant disadvantage of this device consists in the impossibility of solving the problem of updating data stored in memory in the form of relevant documents simultaneously with the solution of the issue of the content of these documents to users in real time.

Known and other system containing a Central processing unit, memory blocks for storing data structures that are connected to the Central processor unit, the receiving registers and processing units of the data [2].

The last of the above technical solutions closest to being described.

Its disadvantage is the low system performance, due to the fact that the execution of user requests is implemented through procedures of search data to fulfill the request is in on the whole database, and their subsequent processing in the buffer zone of server memory, when large amounts of data, which contains the State register of population, inevitably leads to unnecessarily high time to receive the result.

The purpose of the invention is the improvement of the system performance by updating database reporting and reference data in the receipt transaction in real time.

This objective is achieved in that in the known system, containing the first register, the information input of which is the first information input system clock input is the first synchronizing input of the system, and the outputs of the first register are the first information output system, the first selector address information the input of which is connected to the corresponding outputs of the second register, a clock input connected to the output of the first element OR the output of which is connected to the clock input of the second register, the third register, the information input of which is connected to the information output of the first selector address, which synchronizes the output of which is connected to the clock input of the third register, the first group of elements OR, the inputs of which are connected to respective outputs of the elements And the first and second groups, and the outputs are connected to information inputs of the second register, the second group element is in OR inputs are connected to respective outputs of the elements And the third and fourth groups, and outputs connected to the information input of the fourth register, a clock input connected to the output of the second element OR the first delay element, the input of which is connected to the first clock input of the system, and the output connected with one input of the first element, And the output is connected to one input of the first element OR the first trigger unit whose input is connected to the first clock input system, a direct output connected to another input of the first element And to one input elements And the first and fourth groups, other inputs which are connected to respective outputs of the first register, the inverse output of the first flip-flop is connected to one inputs of elements And the second and third groups, the other inputs of which are the second and third information input system, respectively, the second selector address, data inputs which are connected to the outputs of the fourth register, the information outputs connected to the information input of the fifth register, the clock output is connected to the clock input of the fifth register and to the input of the second delay element, and the output of the fifth register is the third information output system, the second And gate, one input of which one is by the second clock input system, the other input is connected to the inverse output of the first flip-flop and an output connected to another input of the first element OR the output of which is connected with one input of the second item OR the third item, one input of which is connected to the direct output of the first trigger, the other is connected to the output of the second delay element, and the output is the first synchronizing system output, the third delay element, the input of which is connected to the output of the third element, And the output is connected with the installation inputs, the first trigger, the first, third and fifth registers, the fourth element And the input of which is connected to the inverse output of the first trigger and the output of the second delay element, respectively, and the output is connected to one input of the third element OR the fourth delay element, the output of which is connected to the input of the fifth delay element, and the sixth delay element entered the sixth register, the information inputs which are the fourth information input system, and a clock input connected to the output of the third element OR the third selector address information the input of which is connected to respective outputs of the sixth register, and the clock input connected to the output of the third element OR the seventh case, the information input of which is connected to the information output of the third selector the address, the clock input is connected to the synchronizing output of the third selector address setting input connected to the output of the fifth delay element, and outputs are the fourth information output system, the eighth register, information inputs which are the fifth information input system, and the clock input is connected to the synchronizing output of the third selector address output, the fourth selector address information the input of which is connected to respective outputs of the eighth register, the clock input is connected to the synchronizing output of the third selector address, and clock output connected to the input of the fourth delay element whose output is the second synchronizing system output, the ninth case, the information input of which is connected with the information outputs of the fourth selector addresses, the clock input is connected to the synchronizing output of the fourth selector address setting input connected to the output of the fifth delay element, and outputs the fifth information system output, the fifth element And one input which is the third synchronizing input of the system, the other is connected to the inverse output of the first flip-flop, and the output connected to the input of the sixth delay element, the second trigger, a single entrance which the CSO is connected to the output of the fifth element, And installation input is connected to the synchronizing output of the fourth selector address, and the inverted output of the second trigger is connected to the third input of the second element And the sixth element And the input of which is connected to the direct output of the second trigger and the output of the sixth delay element, and an output connected to another input of the second and third elements, the fourth element OR, the inputs of which are connected to the synchronizing output of the first selector address and access the sixth element, And the output is connected to the clock input of the second selector address.

The invention is illustrated by drawings, where figure 1 shows the block diagram of the device in figure 2 - block diagram of the address selector, figure 3 shows the structure of codogram, figure 4-8 shows examples of the display information on the user requests.

The system (figure 1) contains the first 1, second 2, third 3, fourth 4 fifth 5, 6 sixth, seventh, 7, 8 eighth and ninth 9 registers, the first 10, second 11, the third 12 and fourth 13 selectors addresses, the first 14 and second 15 triggers, the first 16 and second 17, 18 third, fourth, 19, 20 fifth and sixth 21 elements And the first 22 and second 23, 24 third, fourth 25 elements OR, the first 26 and second 27, third 28 and fourth group 29 elements And the first 30, 31 second, third, 32, 33 fourth, fifth, 34 and 35 sixth delay elements, the first 36 and second 37 g is uppy items OR.

Figure 1 also shows the first 40, second 41-1, the third 41-2, fourth 41-3 and fifth 41-4 information input system, the first 42 and second 43 clock inputs of the system, the first 45, the second 46-1, third 46-2, fourth 46-3 and fifth 46-4 information system outputs, the first 47 and second 48 synchronizing the outputs of the system.

The selector 10-13 addresses (figure 2) contains the decoder 50, the first 51, second 52, and third 53 elements And block memory 54, made in the form of a persistent storage device, the element 55 OR the first 56 and second 57 delay elements.

Figure 2 also shows information 58 and 59 clock inputs of the selector addresses and information 60 and the clock 61 outputs of the address selector.

All nodes and elements of the system are made on the standard of potentially switching elements. Funds and technical support systems consist of technical equipment server equipment for workstations and LAN.

The software system is implemented in the architecture of client-server. It consists of server software and software workstations.

The server part of the system operates in any of the possible operating systems is installed on the server, the database management system Oracle 9.0.1. Jobs end Users operate Windows 95(98) or Windows NT Worktation 4.0, Windows 2000 Professional.

User installs the client part of Oracle 9.0.1.

The system works as follows.

In the information input system 40 on the transmission path of data sequentially received messages (codogram) from objects-sources of information, which can be the passport and visa service, registry offices and other regional sources of information about the population of the regions of the Russian Federation.

Codogram contain the indicative and the information part (figure 3).

Code codogram input 40 is entered in the register 1 clock pulse input 42, which also receives direct input of the trigger 14 and sets it in one state. High potential with direct access to the trigger 14 is opened by one of the inputs of the elements 26, 29 And the first and fourth groups, connecting the outputs of the first and second indicative parts of the case 1 through the respective elements 36 and 37 OR the first and second groups to the information inputs of the registers 2 and 4, respectively. In addition, a high potential with direct access to the trigger 14 is opened elements 16 and 18 I.

The clock pulse input 42 is delayed by element 30 delay time of the trigger 14, and passes through the elements 16 AND 22, OR to the clock input of the register 2, and advanced through the element 23 OR the synchronization is yuushi the input of the register 4, providing entry into the specified registers codes province and territory, information about the population of which is sent to codogram.

Region code from the output of the register 2 to the input of address selector 10 (figure 2), which is fed to the input of the decoder 50.

The decoder 50 of the selector 10 determines the characteristic region, by issuing on one of its outputs a high potential. For definiteness, suppose that a high potential is received at one input element 51 And. in Parallel, the clock pulse from the output element 22 OR to the input 59 of the selector 10, where the delayed element 56 during operation of the decoder 50, and then queries the state of the elements 51-53 I. Considering the fact that open on one input will be only element 51 And then passing this element And the sync pulse arrives, firstly, to the input of the read fixed memory permanent storage device 54, which stores the starting address of the memory zone server (the drawing is not shown), which is necessary to record information, adopted by the case 1 from the corresponding region.

Secondly, the same impulse to read the output of the element 55 OR delayed by the delay element 57 at the time of reading the contents of a fixed cell ROM and then supplied to the clock input of the register 3, the locking code it addresses areas of memory.

The clock pulse from the output 61 of the selector 11 is delayed element 31 delay recording time code in the register 5 and through the open high potential trigger 14 element 18 And, first, is outputted via the 47 system on the interrupt input of the database server, and, secondly, served on the installation log trigger 14, returning it to its original state.

The outputs 45, 46-1, 46-2 registers 1,3,5 connected to the server information system (not shown), which interrupt signal output 47 queries the contents of specified registers and a program starts updating all reports related to the specified area of the specified region and the Russian Federation as a whole. To do this, read the data used by the server as input to the functional tasks to be solved in the information system client-server.

To perform these functions information-analytical system uses the characteristics of the person recorded in the system registration:

personal code

- name;

- name;

- patronymic;

- gender;

citizenship;

- date of birth;

- place of birth;

- view and details of the identity document;

address of residence (or place of residence);

- family ties (kinship, personal code relative information about my father

- personal ID, surname, name, patronymic, citizenship, information about the mother;

information about the spouse; data on children);

- date of arrival to the place of residence or place of stay;

- the disposal date and the reason for disposal of the composition of the Russian population

Federation;

- date on the latest information.

The indicators of the quantity and composition of the population are indicators of the resident population - the population residing in this territory, population - population in a particular area in a given period of time and temporarily absent and temporarily residing, respectively.

Output information objectives are quantitative data on population size and its placement on a given site in a given period of time.

Natural movement of population is the population change due to processes of birth and death.

Migration is the mechanical movement of the population in the region or between regions of the Russian Federation is tion. Circular migration is a systematic movement from city to city (studies etc).

The result of solving the problem is a summary of the number of inhabitants of the territory, have changed their place of residence within the territory, and retired beyond, as well as a summary of the number of newly arrived residents in this area for permanent residence.

The solution of the problem of analysis of structural shifts in the age and sex composition of the population of subjects of the Russian Federation depending on the given site and a given range of years is based on the use of data on the age level of the inhabitants of the territory.

Output information objectives are based on the numerical distribution of the inhabitants of the territory in different age groups.

The task of projecting the population of subjects of the Russian Federation at a given site in a given range of years based on the use of adaptive models and growth curves of the population.

Output information of the tasks are data characterizing the growth rate (EBITA) of the population in a given area in a given period.

The fundamental matching capabilities of adaptive models and the actual conditions of the Russian demographic reality suggests that adaptation procedure n the can, but must be used in the practice of forecasting future population of the regions of the Russian Federation.

Among the adaptive models include models of brown, Holt and Box-Jenkins. Comparison of adaptive models, such as the average module residues, the relative approximation error criterion darbin-Watson, the coefficient of determination, and others, as well as a content analysis of the logical given their results it can be concluded that the model Box-Jenkins does not look much but it is better than the competing forecast versions.

The solution of the issue of problem-oriented lists of citizens at the specified address, age and other criteria (voter lists, lists of potential retirees in the coming years, the lists of pre-conscripts and the like) is also based on the characteristics of the registration of citizens.

The output of this task are problem-oriented lists of citizens at the specified address, age and other criteria (voter lists, lists of potential retirees in the coming years, the lists of pre-conscripts and so on)

Further operation of the system consider the example of receiving data by users according to the results of the "Assessment of changes in the number and location of population sub is mswb of the Russian Federation (fertility and mortality) in the context of a given site in a given range of years."

To do this, in the workplace of the user generated query on “Dynamics of population”, indicates the amount of help “All regions”, is selected period, the population and press the “Give all regions (figure 4).

After the user presses “to Give all the regions in the input 44 receives a pulse, which passes through the element 20 And open at the second input high potential with inverted output of the trigger 14 to a direct input of the trigger 15 and sets it in one state, when the trigger 15 opens the element 21 And closes the element 17 And blocking the transmission circuit of the clock input 43.

After the element 21 And the clock pulse first passes through the element 23 OR the word clock input of the register 4, recording a code site with information input 41-2 and through the element 25 OR the word clock input of the selector 11, which form the memory address of the server hosting the specific territory and recorded in the register 5 in the manner described above.

Secondly, this same pulse through the element 24 OR supplied to the clock inputs of the register 6, when it selected code rate of a population with information input 41-3, and the address selector 12.

The decoder 50 of the selector 12 decrypts the code rate of the population, is giving one of its outputs a high potential. For definiteness, suppose that a high potential is received at one input element 52 And. in Parallel, the clock pulse from the input 59 of the selector 12 is delayed by element 56 during operation of the decoder 50 and then queries the state of the elements 51-53 I. Considering the fact that open on one input will be only element 52 And, through this element And the sync pulse arrives, firstly, to the input of the read fixed memory permanent storage device 54, which stores the starting address of the selected metric of the population.

Pulse reading on the output element 55 OR selector 12 is delayed by the delay element 57 at the time of reading the contents of a fixed cell ROM and then supplied to the clock input of the register 7, the locking code start address of the memory areas of the selected metric of the population.

The pulse from the output 61 of the selector 12 is fed to the clock inputs of the register 8, recording the code of the selected period, and the clock input of address selector 13.

The decoder 50 of the selector 13 decodes the code of the period for which you want to represent the population of, throwing on one of its outputs a high potential.

For definiteness, suppose that a high potential is received at one input element I. In parallel, the clock pulse from the input 59 of the selector 13 is delayed by element 56 during operation of the decoder 50 and then queries the state of the elements 51-53 I. Considering the fact that open on one input will be only element 53 And then passing this element And the sync pulse arrives, firstly, to the input of the read fixed memory permanent storage device 54, which stores the starting address of the selected index, population, and secondly, the impulse to read the output of the element 55 OR selector 13 is delayed by the delay element 57 at the time of reading the contents of a fixed cell ROM and then is supplied to the clock input of the register 9, the locking code it addresses memory areas selected period.

After that, the sync pulse from the output 61 of the selector 13, delayed by the delay elements on the recording time code in the register 9, issued via exit 48 on the other interrupt input of the database server on which the server polls the register 5 output 46-2, register 7 output 46-3 and the register 9 output 46-4 and displays the workplace the requested data as shown in figure 4.

In addition, the output 61 of the selector 13 clock pulse arrives at the installation log trigger 15, returning it to its original state, and the system is ready for a new cycle of operation.

When the mu is the necessity to obtain data on only one region is pressed another key Issue region. In this case, the trigger 15 will remain in its original state and the clock pulse input 43 will pass through the element 17 And the element 22 OR to the clock input of the register 2, connecting it to work, and eventually to the output 46-1 will be given the address of the memory areas corresponding region in the manner described above.

Thus, the introduction of new units and new constructive relationships significantly improve system performance by eliminating the time spent on the pending tasks after receiving the requests, which helped to organize the presentation of information to users in real time.

Sources of information

1. U.S. patent No. 5136708, M CL G 06 F 15/16, 1992.

2. U.S. patent No. 5129083, M CL G 06 F 12/00, 15/40, 1992 (prototype).

Transmission system automated information system “State register of population”, containing the first register, the information input of which is the first information input system clock input is the first synchronizing input of the system, and the outputs of the first register are the first information output system, the first selector address information the input of which is connected to the corresponding outputs of the second register, the clock input of the first address selector connected to the output of the first element OR the output of which is connected with the clock input is ω second register, the third case, the information input of which is connected to the information output of the first selector address, which synchronizes the output of which is connected to the clock input of the third register, the first group of elements OR whose inputs are connected to respective outputs of the elements And the first and second groups, and outputs connected to information inputs of the second register, the second group of elements OR whose inputs are connected to respective outputs of the elements And the third and fourth groups, and outputs connected to the information input of the fourth register, a clock input connected to the output of the second element OR the first delay element, the input of which is connected to the first clock input system and the output is connected to one input of the first element, And the output is connected to one input of the first element OR the first trigger unit whose input is connected to the first clock input system, a direct output connected to another input of the first element And to one input elements And the first and fourth groups, other inputs are connected to respective outputs of the first register, the inverse output of the first flip-flop is connected to one inputs of elements And the second and third groups, the other inputs of which are the second and third information input system for the NGOs, the second selector address, data inputs which are connected to the outputs of the fourth register, the information outputs of the second address selector connected to the information input of the fifth register, the clock output is connected to the clock input of the fifth register and to the input of the second delay element, and the output of the fifth register is the third information output system, the second And gate, one input of which is the second synchronizing input of the system, the other input is connected to the inverse output of the first flip-flop and an output connected to another input of the first element OR the output of which is connected with one input of the second item OR the third item, one input of which is connected to direct the output of the first trigger, the other is connected to the output of the second delay element, and the output is the first synchronizing system output, the third delay element, the input of which is connected to the output of the third element, And the output is connected with the installation of the inputs of the first trigger, the first, third and fifth registers, the fourth element And the input of which is connected to the inverse output of the first flip-flop and the output of the second delay element, respectively, and the output is connected to one input of the third element OR the fourth delay element, the output of which is connected to the input of the fifth delay element, and the sixth the delay element is provided, characterized in that it contains the sixth register, the information inputs which are the fourth information input system, and a clock input connected to the output of the third element OR the third selector address information the input of which is connected to respective outputs of the sixth register, and the clock input connected to the output of the third element OR the seventh case, the information input of which is connected to the information output of the third selector addresses, the clock input is connected to the synchronizing output of the third selector address setting input connected to the output of the fifth delay element, and outputs are the fourth information output system, the eighth register, information inputs which are the fifth information input system, and the clock input is connected to the synchronizing output of the third selector address, the fourth address selector, the information input of which is connected to respective outputs of the eighth register, the clock input is connected to the synchronizing output of the third selector address, and clock output connected to the input of the fourth delay element whose output is the second synchronizing system output, the ninth case, the information input of which is connected with the information the mi output of the fourth selector address, the clock input is connected to the synchronizing output of the fourth selector address setting input connected to the output of the fifth delay element, and outputs the fifth information system output, the fifth element And one input which is the third synchronizing input of the system, the other is connected to the inverse output of the first flip-flop, and the output connected to the input of the sixth delay element, the second trigger unit whose input is connected to the output of the fifth element And setting input is connected to the synchronizing output of the fourth selector address, and the inverted output of the second trigger is connected to the third input of the second element And the sixth element And the input of which is connected direct the second trigger and the output of the sixth delay element, and an output connected to another input of the second and third elements, the fourth element OR, the inputs of which are connected to the synchronizing output of the first selector address and access the sixth element, And the output is connected to the clock input of the second selector address.



 

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