Energy-independent passive matrix, method for reading from such matrix and device for three-dimensional data storage

FIELD: recording devices.

SUBSTANCE: device has electrically polarized dielectric material, being in layer placed between first and second addressing sets with parallel placement of electrodes within limits of each set, controlling buses and data buses, reading means and means for connecting each data bus to associated reading means. Method describes operation of said device. Device for three-dimensional data storage has multiple stacking layers, each of which has one of said energy-independent recording devices.

EFFECT: possible localization of errors, prevention of interferences in non-addressed cells.

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The technical field to which the invention relates.

The present invention relates to a storage device on the basis of the non-volatile passive matrix, which contains electrically polarizable dielectric material having hysteresis, mainly ferroelectric material. While specified storage material is in a layer, located between the first and second sets of electrodes addressing parallel arrangement of the electrodes within each set. The electrodes of the first set, which form control (numeric) bus storage devices are perpendicular to the electrodes of the second set, which form a data bus (bit bus). As a result, the crossing point (hereinafter called for greater clarity, the point of intersection is formed with the memory cell with a structure type capacitor. Such memory cells form the elements of a passive matrix memory device, which can be made selective addressing of each memory cell for operations read/write, using appropriate control bus and data bus. The write operation in the cell is performed by creating a desired state of polarization in the cell by application thereto of a voltage on the corresponding control bus ishine data determining the cell. The applied voltage or sets the desired state of polarization in the cell, or is able to change its state of polarization. The read operation is performed by application to the memory cell voltage Vsswitch, which exceeds the coercive voltage

Vcand detecting at least one electrical parameter of the output current on the data bus.

The invention relates also to a method of reading from a storage device of the type described.

The level of technology

Ferroelectric integrated circuit has the revolutionary properties in comparison with conventional technology. Their applications include non-volatile storage device, particularly a matrix memory with such advantages as high speed, virtually unlimited service life and high speed recording, i.e. properties, which recently could only dream of.

Ferroelectric matrix devices can be divided into two types, one of which involves the presence of active elements connected to the memory cells, and the other contains no active elements. Next will be described both of these types.

Ferroelectric matrix memory having cells pam is in the form of ferroelectric capacitors without active access elements (such as transistors), contains a ferroelectric thin film with a set of parallel conductive electrodes ("control tyre"), printed on one side and essentially orthogonal set of conductive electrodes ("data bus")engraved on the other side thereof. This configuration will hereinafter be called "passive matrix memory." In a passive matrix memory of the individual ferroelectric memory cells formed at intersections of opposite electrodes forming a matrix of memory containing memory cells, individual accessed electrically by means of selective excitation, with the edges of the matrix, the respective electrodes.

Another approach to the formation of a matrix of memory consists in the modification of each ferroelectric memory cell by including an active element, in the typical case of the access transistor, connected in series with the ferroelectric capacitor. Transistor access controls access to the condenser and blocks unwanted signals-interference, for example, from adjacent memory cells. In a typical case, the memory cell may include a ferroelectric capacitor and an n-channel field-effect transistor metal-oxide-semiconductor (hereinafter abbreviated referred to as a MOS transistor without indications simplify its type (n or p). The gate of the transistor is connected to the control bus. Itokawa/drain region of the MOS transistor is connected to the data bus. One electrode of the ferroelectric capacitor is connected with stokovoj/stock area of the MOS transistor, and its second electrode is connected with the so-called "transmission line". The described scheme is now generally accepted, and the corresponding memory cells are often defined as a memory cell with one transistor and one capacitor (1T, 1C). Well-known and other concepts using two transistors or more. However, all these concepts lead to an increase in the number of transistors as compared with the passive matrix memory that is associated with a number of disadvantages, such as reducing the number of memory cells within a given area, the greater complexity and increased power consumption. Next, the configuration of this type will be referred to as active matrix memory, because here each memory cell includes an active element such as a transistor.

However, the present invention relates exclusively to devices with passive matrix memory that does not contain active elements such as diodes or transistors associated with the memory cell.

Read operations and write in a passive matrix memory can be implemented by so-called "uborochnaya addressing", at which reading or writing is performed only for a portion of the memory cells on the same control bus, in the typical case only for a single cell. To perform this operation random read or write on non-addressable cells in Deaktivierung control buses and data bus serves the bias voltage in accordance with the so-called "Protocol of feed pulses" in order to avoid partial polarization switching in non-addressable cells. The choice of Protocol submission pulses depends on a number of factors, and the literature describes various schemes for applications associated with the ferroelectric memory materials with hysteresis. As an example, you can specify on the application of Norway No. 20003508, filed July 7, 2000 by the applicant of the present invention and the corresponding international application WO 02/052887. This application describes the Protocol for a passive matrix memory.

On the other hand, usually the filing of a shift to non-addressable cells leads to the appearance of interfering voltages. This may cause the loss of content of the memory cell or the appearance of leakage currents and other harmful currents, referred to as "stray currents"that can mask the current addressable memory cells during read operations and thereby mask the content of the data being read. In zavisimost the type under consideration, the storage device can be formulated various criteria regarding the removal or at least, reduce interference to non-addressable memory cells, including methods for eliminating parasitic currents. Another approach is to reduce the sensitivity of each cell in the matrix to weak perturbations. It can be achieved by using cells that have nonlinear current-voltage response, characterized by, for example, the presence of a threshold, straightening and/or various forms of hysteresis.

In order to improve the parameters of both active and passive ferroelectric memory devices, for example, reducing requirements for power consumption, matrix memory can be divided, "segmented" into blocks of smaller size, the so-called "segments". Usually, such segmentation is visible to the user. Another reason for the segmentation problem caused by the so-called "fatigue" ferroelectric capacitors: after the ferroelectric capacitor has been switched a large number of times, corresponding, for example, several million, he is unable to preserve the residual polarization and, therefore, ceases to function. The solution to that particular problem may be the use of smaller segments of the matrix in order to avoid switching the entire row of capacitors. A similar solution is described, for example, in the document US-A 5567636. Other dock the COP, describing the segmented matrix memory, is the work of Gary F. Derbenwick & al., "Non-volatile Ferroelectric Memory for Space Applications", Celis Semiconductor Corporation, Colorado Springs. This document describes a segmented matrix memory capable of reducing power consumption in an active matrix using the architecture of the cell type one transistor - one capacitor (1T, 1C).

Examples of storage devices with passive matrix using ferroelectric memory material can be found in the literature, related to the 40-50 years. In particular, article W.J.Merz and J.R.Anderson, "Ferroelectric storage devices", Bell. Lab. Record. 1, pp. 335-342 (1955) described the memory on the basis of barium titanate. Similar studies were published shortly after the publication of the above article (see, for example, .F.Pulvari, "Ferroelectrics and their memory applications", IRE Transactions CP-3, pp. 3-11 (1956), and D.S.Campbell, "Barium titanate and its use as a memory store", J. Brit. IRE 17 (7), pp. 385-395 (1957)). Another example of a passive matrix memory can be found in the IBM Technical Disclosure Bulletin, Vol. 37, No. 11, November 1994. However, none of these documents describes a solution to the problems associated with the disturbance of non-addressable cells.

Another approach to overcoming these problems would be the modification of the ferroelectric material in such a way as to obtain a hysteresis loop in the shape of a square. However, this approach is not described in the literature in sufficient detail.

The invention

Thus, there is a need for a passive matrix memory, free from the above drawbacks, such as the presence of perturbations on non-addressable cells.

Considering the above mentioned task, which directed the present invention is to provide a storage device with a passive matrix memory, which solved the problem to perturbations of non-addressable memory cells. Another problem solved by the invention is to create a storage device with a passive matrix memory, which minimized the impact of cumulative signals from non-addressable cells in the process of reading the stored data. Finally, another goal of the invention is to develop a method of reading in a storage device of a passive matrix memory, compatible with the above mentioned tasks.

The solution of these tasks, as well as various advantages and new features provided in accordance with the present invention by creating a mass storage device with a passive matrix memory, which is characterized by the fact that the control bus is divided into segments, where each segment contains a number of adjacent data bus matrix and set this set. Also provided means for joining each Chi is s data attributed to the segment to the associated tool reading, which provides simultaneous connection of all memory cells associated with the control bus in this segment, to read on the data bus included in the segment. Each tool reading made with the possibility of detecting the flow of charge in the data bus, connected to the specified tool in order to determine the logical value stored in the memory location specified by the data bus.

In accordance with the first preferred storage device according to the invention the means for simultaneous connection of each data bus assigned to the segment, with an associated tool read while addressing represent multiplexers. In this case, the number of multiplexers corresponds to the highest number of data bus that specifies the segment, and each data bus segment connected to its associated multiplexer. In addition, it is preferable that the output of each multiplexer was connected to the only means of reading, which preferably is a power reading.

In accordance with the second preferred storage device according to the invention the means for simultaneous connection of each data bus assigned to the segment associated with avanim means of reading while addressing constitute valve means. In this case, all data bus of one segment can be connected to their corresponding single valve means. Each of the valve means has a number of outputs corresponding to the number of data bus in the corresponding segment, while each output of each gate means connected to the corresponding line, part of the output data bus. The number of such lines, each of which is connected with the only means of reading corresponds to the highest number of data bus in the same segment.

Valve device in this embodiment preferably contains leaking valves, and a means of reading preferably represents a power reading.

The solution of the above objectives and the achievement of relevant benefits are also provided according to the present invention provide a method for reading non-volatile storage device with a passive matrix memory. The method according to the invention is characterized by the fact that the control bus is divided into a number of segments, each of which contains a number of adjacent data bus matrix and is determined by them, connect each data bus within a segment of the control bus associated with the means of reading, alternately activate, in accordance with the Protocol, what about the one management bus segment, setting the potential of the activated control bus segment is equal to the voltage Vsswitch during at least part of the scan cycle while holding all tires segment at zero potential, and determine the logical values stored in the individual memory cells and perceived means read during the read cycle.

In accordance with the preferred embodiment of this method in those intervals of time when there is read or write any memory location, all control bus and all data bus hold under the original potential, comprising about 1/3 of the voltage Vsswitch, activate, in accordance with the Protocol, one control bus, setting the potential of the activated control bus segment is equal to the voltage Vsswitch during at least part of the scan cycle while holding all buses specified segment at zero potential, and determine the logical values stored in the individual memory cells and perceived means read during the read cycle.

In addition, solving problems and achieving relevant advantages are achieved in accordance with the present invention through the use of non-volatile memory of the mouth of the STS with a passive matrix memory in any of the above options to create three-dimensional device storage with plenty of forming a stack of layers, in which each layer contains one non-volatile storage device with a passive matrix memory.

List of figures

Hereinafter the invention will be described in more detail by discussing its General principles and preferred embodiments, which should be read in conjunction with the attached drawings.

Figure 1 illustrates the principle of the hysteresis loop for a ferroelectric memory material.

Figure 2 is a schematic diagram of part of a passive matrix memory with overlapping electrode lines to which memory cells contain ferroelectric material, localized between the electrodes in the places where they overlap.

Figure 3 on an enlarged scale showing a section along line a-a in figure 2.

Figure 4 is a functional block diagram illustrating the reading of the complete data word in matrix ferroelectric memory.

Figure 5 is a functional block diagram illustrating a passive matrix memory in accordance with a preferred variant of the invention, containing a segmented control bus.

6 is a functional block diagram illustrating a passive matrix memory in accordance with another preferred variant of the invention containing the segment is rowanne control bus.

On figa shows a simple timing diagram read complete data word with the subsequent cycle write/update intended to address control bus segment matrix mode "read full information of the word."

Fig.7b corresponds to variant timing diagram for figa.

On Fig presents a variant of the device shown in figure 5, but with an electric segmentation of governors of the tires.

Figure 9 shows a variant of the device shown in figure 6, but with an electric segmentation of governors of the tires.

Figure 10 schematically illustrates how a matrix memory for 5 or 6 may be embedded in a device of three-dimensional data storage.

Information confirming the possibility of carrying out the invention

In order to achieve a better understanding of how passive matrix memory, and even a separate cell, a detailed description of the preferred embodiments of the invention will be preceded by a discussion of its basic principles. In this regard it will be made reference to figure 1, which presents the so-called "hysteresis loop for ferroelectric material. Figure 1 represents the polarization P of the ferroelectric material as a function of potential difference V. the value of the polarization will be displaced is Atisa in the loop in the indicated direction. Ferroelectric material characterized by a hysteresis loop of the type shown in figure 1, will change the direction of its total polarization ("switch") when a voltage VSthat exceeds the so-called coercive voltage VC.

When the voltage V exceeds the coercive voltage VCthe polarization P varies sharply, taking a large positive value +Pr(it is assumed that at zero electric field polarization was negative). This positive polarization +Prsaved up until a large negative voltage-VSexceeding in absolute value negative coercive voltage VCagain will not change the polarization, giving it a negative value. As a consequence, the storage device provided with capacitors containing ferroelectric material will detect the memory effect in the absence of applied external electric field. This makes it possible for non-volatile data retention by application to the ferroelectric material potential difference, which causes the polarization response. The direction and magnitude of the response can be thus set and saved in the desired state. Similarly can be determined state of polarization application : the tion. Next will be described in more detail the process of storing and determining the content of the data.

The required shift speed and other factors nominal (switching) voltage VSused to control the polarization state of the ferroelectric material, in the typical case is chosen significantly larger than the coercive voltage VC. Figure 1 nominal value in the General form indicated by the dashed line, but his choice is not limited to this value. Can be used and other values.

Figure 2 illustrates the part of the matrix is m× n, part of the storage device 10 with a passive matrix memory, which has two mutually opposite set of parallel electrodes, namely electrodes corresponding to the control tyre (or lines) WL, and electrodes corresponding to the tire (or lines) BL data. Electrodes corresponding to the control tyres WL, and the electrodes corresponding to the tire BL data are mutually perpendicular, and in the area of their overlap, they form the side walls of the individual volume elements of the ferroelectric insulating material (described in detail below), which, in turn, determine the amount kondensatoprovodov memory cells in a matrix memory.

Figure 3 shows brings the e matrix along the line A-a in figure 2. The dielectric in each capacitor is a ferroelectric material 12. The thickness of this material determines the height h of volume elements, which, in turn, determine the cell 13 of the memory. To facilitate understanding of the figure 2, figure 3 shows only three zones of intersection between the control bus and tyres WL BL 10 data.

When creating the cell 13 of the difference Vspotentials between the opposite electrodes, i.e. the control bus WL and bus BL data ferroelectric material in a given cell will be exposed to the action of an electric field E, which will cause the polarization response. This response can be specified and saved in one of two stable States, corresponding positive and negative polarization, as it follows from figure 1. These two States represent the binary state "1" and "0". Similarly, the polarization state of the cell 13 can be changed or read by repeated application of the potential difference between the two opposite electrodes WL and BL and addressing to the cell 13. This will lead to the fact that after removal of the potential difference, the polarization will remain unchanged or will switch to the opposite direction. In the first case, in response to the applied voltage will be low current, whereas in the second case, the change in the polarization is given is to the flow of significant current.

In order to solve it, is "0" or "1", the current is compared with a reference value that can be obtained by different methods (not illustrated). If the read is destructive, the polarization state of some cells will be switched to the opposite. For example, the polarization state of the cell can be switched to "0" regardless of what state ("1" or "0"was read. The initial state can be re-written to a cell included in the memory in order to store the information in memory, i.e. the value which is read. A more detailed description of how the functions of a passive matrix memory, will be given hereinafter, in the description of the preferred variant of the invention.

Further, to facilitate understanding of the present invention will be given with reference to figure 4, illustrating another method for reading a passive matrix memory 11, hereinafter referred to as "read full information of the word." In accordance with this method, the active management bus WL (figure 4 this is the first management bus WL1)associated with the selected cell 13 of the memory is read throughout the length of the string, i.e. in each cell 13 of the memory defined by the bus L1,... BLn. Read full information word itself is well-known concept, described, for example, the document US-A 6157578. However, the solution described in this document, refers to active matrix storage device and serves the purpose of increasing the speed of transferring data stored in a relatively large block matrix memory. The present invention, in contrast, refers only to a passive matrix memory. In connection with this known solution relating to an active matrix, are irrelevant, since the active devices are not problems for non-interference of the cell.

It should be noted that in accordance with the Protocol submission pulses for read full information word in a passive matrix memory unused control bus (in this case the tyres WL2,...m) may be at the same potential or essentially the same potential as the bus BL1,...ndata. The value of the current I depends on the polarization state of each cell 13; it is determined by the means 26 reads, one for each bus BL data, as shown in figure 4. Means for reading, for instance, can serve as amplifiers of the read.

The method of reading the full data word provides several advantages. For example, the voltage reading can be chosen much higher than the coercive voltage, without causing partial switching in adresem cells; however, this method is suitable for a large matrix.

5 to 7 illustrate the preferred variants of the present invention. Figure 7 presents the timing diagram, which correspond to zero perturbations for non-addressable memory cells at a voltage Vsall cells of the active control bus WL1during reading of all cells in the active segment. Preferred timing diagram is given on figa, and an alternative timing diagram - fig.7b.

As can be seen from figure 5, which shows a preferred variant of the passive matrix memory according to the present invention, the corresponding matrix has dimensionality m× n, i.e. formed m the control tyres WL1,...mand n tires BL1,...ndata. The control bus is divided into q segments S, each segment is set to k adjacent tires BL data matrix. Preferred values k are equal for all segments, so that q· k=n. To read the first data bus in each segment S can be connected by means of the first multiplexer 251the first tool 261read. The second data bus in each segment must be respectively connected with the second multiplexer 252; respectively the k-th line in each segment will be associated with the latest multiplexer 25k.

The number is the creation of multiplexers (MUX) 25, therefore, should be equal to the greatest number of tyres in the BL data that specifies the segment. Of course, nothing prevents the number of data bus in each segment S was different; however, if the memory cell on the data bus segment contains a data word of the same length, the value of k is the same for all segments. Each multiplexer 25 is connected to the tool 26 is read to read the data. The amount of funds 26 read, respectively, will be equal to the greatest number k tire BL data that specifies the segment.

Unlike regular options passive matrix memory, which uses a partial read, all the cells 13 in the shared memory segment control bus at the same time attached to the means 26 reads, so all a bit of a point on a segment of the control bus can be read in parallel. The specific option means of reading can serve as amplifiers of the read. To facilitate understanding of the figure 5 shows only the first two segment S1, S2and the last segment Sq; this is also true for the multiplexers 25 and amplifier 26 are read.

Access to data that is stored and/or must be stored in the matrix memory 11 may be performed using the associated row decoder and column decoder that figure 5 does not display the wife. Data that is recorded in the cells 13 of the matrix memory 11 can be read using the Protocol of feed pulses, for example, as was mentioned in connection with figure 5, using the amplifiers 26 are read, which are connected with tires BL data through the multiplexer 25. All tires BL data that specify one segment S, connected with the multiplexers 25, and the selection of these tires are made only when specified by the management bus WL in this segment is active. In accordance with this method, all data bus, the corresponding active control bus WL in the segment S is read in parallel configuration "read full information words, all data bus is shared between amplifiers 26 are read.

In practical applications of passive storage device may represent, for example, the memory 16 Mbit, divided into 8 segments S(q=8), and contain 256000 control tyres WL, each of which corresponds to 64 bits. In this case, each segment S will be 8 tires BL data, i.e. k=8. Possible, of course, other architectures, such as 9, 16, or 32 bits in each segment S.

In another preferred embodiment of the invention, each segment has at least 256 memory cells 13. In the case of multiplexers 25 32:1 the width of the matrix will correspond to 8192 bi the am when duplicating only 32 driver control tyres. Of course, every control bus is segmented in accordance with the number of amplifiers 26 are read.

Figure 6 shows an alternative embodiment of a storage device according to the invention. In this embodiment, the multiplexers replaced valve means 25. Valve means 25 trigger bus BL data in the same way as the multiplexers.

Preferably the valve means 25 in the form of pass gates connected to each bus BL data in the segment S. while the number of multiplexers 25 in the embodiment of figure 5 must be equal to the number of tires BL data in segment S, i.e. k, the number of leaking valves in the embodiment of Fig.6 must match the number q of segments S. the Number of outputs on each transmissive valve corresponds to the number of tires BL data in the corresponding segment S. in order to provide a parallel reading of the memory cells 13 active control bus WL in segment S, for each tire BL in the segment uses a separate amplifier 26 reading. Each amplifier 26 reading is connected with one of the lines 27, forming part of a data bus 28. The first pass gate is connected to the first line 271a data bus; a second output with the second line 272this bus etc. quantity is of lines 27 and amps reading is, obviously, the greatest number of tyres in the BL data that define the segment S.

On figa and 7b shows an alternative timing diagram for the read cycle of the complete data word.

On figa shows the timing diagram cycle read/write ("restore", "re-entry") full data word segment of the control bus. The above timing diagram is based on a four-level Protocol. In accordance with this chart in a period when there is read or write to any memory cell matrix, all control of the bus and all of the data bus are under source voltage corresponding to zero voltage. Each memory cell has an address, which is defined by the intersection of the activated control bus WL and all tires BL data included in the segment to be read.

During a read cycle inactive control tyres WL and all tires BL data follow the same curve of potential. During a read cycle the control bus is in contact with the cells to be read, is under switching voltage VS. In this time interval, the data bus are under zero voltage. With regard to the presented timing chart for the application of the switching voltage VSon the side of the cell, with testwuide control bus, and zero voltage on the other side of the same cell corresponding to the data bus, means that the cell is written to "0". Thus, for both diagrams after completing a read operation, all cells in the active control tyres are in a state corresponding to "0". Therefore, in order to recover the data recorded in the memory, it will be necessary to re-write "1" only on the data bus, which are the cells that must contain "1". This operation on both the above diagrams corresponds to the serving cell, in

which should be written to "1", the voltage of the opposite polarity during a write cycle.

Fig.7b corresponds to an alternate timeline, based on a four-level Protocol. In accordance with this option in a period when there is read or write to any memory cell matrix, all control of the bus and all of the data bus are under source voltage VS/3.

In embodiments of the invention in figure 5 and 6 control bus could be in principle continuous, i.e. they are no gaps through all of the individual segments, which are defined only by the corresponding data bus. In such case, you must use the multiplexing and adapted to this protocols read and Zap the si. However, using too long of governors of the tire does not give any advantage. This problem does not occur in the case of a limited number of segments and the limited number of data bus in each segment, as was the case in the above example, where you used 256000 control tyres and 8 segments with 8 data bus in each segment. The capacity of the memory in this case, as already mentioned, will be 16 MB.

However, continuous control of the bus and have other disadvantages. If the bit pixels corresponding to the memory cells in the segment S is read at a high voltage on the active control bus, the same high voltage is applied to the entire active control bus in all segments. As a result, although will be connected only data bus addressable segments, there may be capacitive coupling and parasitic currents, affecting, for example, the memory cells corresponding to the adjacent inactive control tyres in the same segment. This can cause false signals or noise component. As a consequence, in practical implementations, the storage device according to the invention it was found desirable to have the ability segmentation control tyres electric way so that the control bus is connected to the driver that is are within the addressable segment. At the same time, the corresponding segments of the control bus in the other segments must remain unconnected. This approach is particularly relevant in the case of application of the Protocol on Fig.7; and it can be implemented in a variant of the storage device on Fig, which in General corresponds to the variant in figure 5.

Nesobrannyj driver included in the group of 20 drivers, selected by the selector 22 segment (which, for example, can be made in the form of a selector bus) so that the activation control bus WL in the selected segment S to complete reading or writing. The multiplexers 25, which are controlled by the selector 22 segment can be connected with the selected driver in the group 20 through switches 24; their management from the selector 22 is switchable via the cache memory 21. Specific multiplexer 25 simultaneously addressed for bus connections BL data in the addressed segment with the amplifier 26 is read. For purely practical reasons each control bus WL in the segment can be attached to the logical element "And", such as CMOS-valve leaking or the valve. This segment will be addressed through the control bus or the decoder address. For example, in the segment of S1selected management bus WL1and the tension is this segment will be served only on this control bus. In this case, when a destructive read all of the memory cells and the control bus WL1within segment S1will be under zero voltage, while the multiplexer 25 connects all data bus segment S1to the respective amplifiers 261...26kread. This may be done reading all of the cells along a control bus, i.e. if the control bus segment was set in such a way as to enable the information word, it is possible to read an entire data word.

At that time, as is the detection of the status of all cells on the selected control bus WL1the rest control tyres WL2...WLmand tires BL1-BLkunder source voltage close to the voltage bias on the amplifier 26 is read. In principle, in this case you would not be interfering contribution from other cells in the segment. It would also bias voltage on the cells associated with the data bus, which could lead to interfering signals at the input of the amplifier 26 is read. Data at the output of amplifier 26 is read is transferred on a bilateral information bus 23, while the logical circuit 29 record connected in parallel to the output multiplexers for recording data in the bit point of the cells on the active control of the bus segment. When this control bus is selected accordingly by the selector 22, as in the case of reading.

It is preferable also to provide a buffer blocks 21 memory at switching the outputs of the selector 22. These blocks connect drivers and multiplexers 25 through multiple switches 24 lines managed by the selector 22.

Figure 9 presents the option is functionally equivalent variant on Fig and at the same time having similarities with option 6, namely the use of a valve means instead of the multiplexer 25. Each valve means may include switching transistors 25A, one for each bus, which operate as pass gates. Thus, the valve means 25 will contain k switching transistors 25A. As in the embodiment of Fig, provided by a group of 20 drivers, one for each segment, whereas the selector 22 is replaced by a selector 22A groups of drivers. Addressing a separate control bus WL is output bus 30 addressing control tyres under the control of the selector 22A groups of drivers. When reading bus BL data are connected to lines 27 a data bus 28, and the information output of the read amplifier is connected to duplex the data bus 23. Like the version on Fig, there is a logical circuit 29 of the records in the prison in parallel to the amplifiers 26 are read. When the recording of the corresponding segment of the control bus is selected by the selectors 22A driver groups, addressing via the bus 30 addressing control bus.

Such necessary devices and tools for selection, decoding and addressing, as, for example, a logical synchronization circuit, well known to specialists in this field and are widely used in storage devices with a matrix addressing, where they are active or passive. Therefore, their detailed description is not necessary.

The number of voltage levels and specific values of the levels used in the Protocol submission pulses can be chosen quite freely, provided that you meet the requirements for a reading of the complete data word. When the polarity of the voltages used in the Protocol can be changed to reverse.

In the manufacture of real circuits for the embodiment of the storage device according to the present invention the matrix memory can be performed on the substrate with an integrated driver control bus so as not to increase the overall size of the device.

Segmented control bus can also be applied when using memory in the form of forming a stack of layers. In this case, the bus BL data connecting the raised vertically with the multiplexers 25 or valve means. This is illustrated by figure 10, which represents a schematic, cross section view of embodiment of the invention, in which the storage device 10 of the present invention is assembled in the foot. Thus enabling the device of the three-dimensional data storage, in which each layer (M memory) contains one storage device 10. Due to the fact that storage devices are arranged with a mutual shift, control tyres WL and the data bus BL can be connected through the so-called edge connectors 19 (i.e. alternating horizontal and vertical connections, "Pro edge") with the driver and control circuits in the substrate 16. The substrate 16 (which is applied to the insulating layer 17 may be inorganic, for example, silicon-based, so that these circuits can be implemented using CMOS compatible technology. Figure 10 shows only two layers of M1, M2memory, separated by an intermediate dielectric layer 18 (and only a limited number of data bus), but the actual device is a three-dimensional data storage may contain a very large number of layers of memory 8 and to over 100 and more. The result will be implemented in the memory with a very large capacity and high recording density, since each layer of memory will have a thickness of about 1 μm or even less./p>

The advantages of this passive matrix memory is easy to manufacture and high density cells. Other advantages are as follows.

a) If the control bus electrically segmented, non-addressable memory cells during the read cycle will be at zero potential or a low potential), if the Protocol is used by figa. This will reduce the number of interfering signals, which could lead to loss of memory contents, but also to eliminate all noise during read operations, leading to the emergence of parasitic currents.

b) data-transfer Speed will correspond to the maximum speed determined by the number of data bus segment.

C) Voltage VSreading can be chosen much larger than the coercive voltage, and it will not lead to the partial switching in non-addressable cells. As a result, you can use shift speed approaching the maximum possible speed for the respective polarizable material of cells.

g) the Method of reading is compatible with large matrices.

In addition, the memory device according to the invention can be implemented with a smaller number of read amplifiers. This is a significant advantage in the case of memory, a large shopping Mall is volume, and in relation to the power consumed by the read amplifiers. This power can be quite high, but it can be reduced to some extent through proper management of your contours and contours addressing. Further, reducing the number of amplifiers reading implies that the area allocated to the readout means can be balanced in such a way as to ensure overall optimization space of the storage device. Finally, the segmentation of governors of the tire means that errors in reading or addressing in case of a defect in a single control bus will be localized information in a single word.

1. Non-volatile storage device (10) with a passive matrix memory containing an electrically polarizable dielectric material (12)with hysteresis, mainly ferroelectric material in the layer, located between the first and second sets of addressable parallel arrangement of the electrodes within each set, and the electrodes of the first set form a control bus (WL1,...m) a storage device and are perpendicular to the electrodes of the second set (15), which form a bus (BL1...ndata, and a storage material (12) at the point of intersection of education is described cell (13) memory structure type capacitor, forming elements of passive matrix memory device, which can be made selective addressing of each cell (13) memory for operations read/write, using appropriate control bus (WL) and tires (BL) data, and the write operation in the cell is performed by creating a desired state of polarization in the cell (13) memory by the application to it by determining the cell management bus (WL) and bus (BL) data voltage, which sets the desired state of polarization in the cell (13) memory, or is able to change its state of polarization while the read operation is performed by application to the memory cell voltage, which exceeds the coercive voltage Vcand detecting at least one electrical parameter output current tires (BL) data, wherein the control bus (WL) is divided into segments (S1,...q), each of which contains a number of adjacent tires (L) passive matrix memory (11) and set this set provides the means (25) for connecting each bus (BL) data assigned to the segment (S), to the associated tool (26) reading, which provides simultaneous connection of all cells (13) of memory associated with managing the it bus (WL) in the segment (S), to read on tires (BL) data contained within the segment (S), and each tool (26) reader configured to detect the flow of charge in the tire (BL) data, connected to the specified tool, in order to determine the logical value stored in the cell (13) memory specified specified data bus.

2. Non-volatile storage device (10) according to claim 1, characterized in that the said means (25) for simultaneous connection of each data bus assigned to the segment (S)associated with means (26) reading while addressing represent multiplexers.

3. Non-volatile storage device (10) according to claim 2, characterized in that the number of multiplexers (25) corresponds to the highest number of tires (BL) data specifying the segment (S), and each tire (BL) data are connected with the corresponding multiplexer.

4. Non-volatile storage device (10) according to claim 3, characterized in that the output of each multiplexer is connected to the only means (26) are read.

5. Non-volatile storage device (10) according to claim 4, characterized in that only means (26) reading is a power reading.

6. Non-volatile storage device (10) according to claim 1, characterized in that the said means (25) for simultaneous connection of each of the ins data, attributed to the segment (S)associated with means (26) reading while addressing constitute valve means.

7. Non-volatile storage device (10) according to claim 6, characterized in that all tires (BL1,...ndata segment (S) connected to their corresponding single valve means, each of the valve means has a number of outputs corresponding to the number of tires (BL) data in the appropriate segment (S), and each output of each gate means connected to the corresponding line (27), which is part of the output data bus (28), while the number of these lines (27), each of which is connected with the only means (26) reading corresponds to the highest number of tires (BL) data in the same segment (S).

8. Non-volatile storage device (10) according to claim 6, characterized in that the valve means includes passing the gate.

9. Non-volatile storage device (10) according to claim 6, characterized in that the means (26) reading is a power reading.

10. The device of the three-dimensional data storage containing multiple forming the stop layers (P1P2,... ), characterized in that each layer (B) contains one non-volatile storage device (10) with a passive matrix memory, the implementation of the Noah in accordance with any of claims 1 to 10.

11. The method of reading in non-volatile storage device (10) with a passive matrix memory containing an electrically polarizable dielectric material (12)with hysteresis, mainly ferroelectric material in the layer, located between the first and second sets of addressable parallel arrangement of the electrodes within each set, and the electrodes of the first set form a control bus (WLi,...m) a storage device and are perpendicular to the electrodes of the second set (15), which form a bus (BL1,...ndata storage device and the storage material (12), the intersection points of the cells are formed (13) memory structure type capacitor forming elements of passive matrix memory device, which can be made selective addressing of each cell (13) memory for operations read/write, using appropriate control bus (WL) and tires (BL) data, and the write operation in the cell is performed by creating a desired state of polarization in the cell (13) memory by application to a given cell by determining the cell management bus (WL) and the bus (BL) data voltage, which sets the desired state of polarization in the cell (1) memory, or is able to change its state of polarization, while the read operation is performed by application to the cell (13) memory voltage, which exceeds the coercive voltage Vcand detecting at least one electrical parameter output current tires (BL) data, the method provides for the operation control of the electric potentials on all control tire (WL) and the tires (BL) data coordinated in time in accordance with the Protocol containing the sequence of electrical pulses for control bus and data bus and providing during a scan cycle, is included in the specified Protocol, the detection, by means of the reading of the charges, the current in the data bus, wherein the control bus (WL) is divided into a number of segments (S1,... Sq), each of which contains a number of adjacent tires (BL) data matrix and is determined by them, connect each bus (BL) data within the segment (S) control bus associated with means (26) are read alternately activate, in accordance with the Protocol, one control bus (WL) segment (S)by setting the potential of the activated control bus (WL) segment (S) is equal to the voltage Vsswitch during at least part of collectively while holding all tires (BL) segment (S) at zero potential, determine the logical values stored in the individual cells (13) memory and perceived means (26) is read during the read cycle.

12. The method of reading according to claim 11, characterized in that in those time intervals when there is read or write in any of the cell (13) memory control bus (WL) and all tires (BL) data hold under the original potential, comprising about 1/3 of the voltage Vsswitch, activate, in accordance with the Protocol, one control bus (WL) segment (S)by setting the potential of the activated control bus (WL) segment (S) is equal to the voltage Vsswitch during at least part of the scan cycle while holding all tires (BL) segment (S) at zero potential, and determine the logical values stored in the individual cells (13) memory and perceived means (26) is read during the read cycle.



 

Same patents:

The invention relates to a method of controlling the set of memory cells or display with passive matrix addressing containing electrically polarizable material with hysteresis, mainly ferroelectric material

The invention relates to a method for performing write operations and read into memory with passive matrix addressing, formed by the set of memory cells containing electrically polarizable material having the property of residual polarization, and device for implementing this method

The invention relates to processing devices and/or storage of active or passive electrical addressing

The invention relates to the creation of optical memory and can be used for the optical medium

FIELD: recording devices.

SUBSTANCE: device has electrically polarized dielectric material, being in layer placed between first and second addressing sets with parallel placement of electrodes within limits of each set, controlling buses and data buses, reading means and means for connecting each data bus to associated reading means. Method describes operation of said device. Device for three-dimensional data storage has multiple stacking layers, each of which has one of said energy-independent recording devices.

EFFECT: possible localization of errors, prevention of interferences in non-addressed cells.

3 cl, 11 dwg

FIELD: memory devices.

SUBSTANCE: first device for comparing phases has signal generator for feeding two or more reading signals with given phases to memory cell, phase-sensitive detector, support signal source, discrimination/logic contour. Second device for comparing phases has signal generator for feeding first periodical signal, applied to second periodically reading signal of lesser frequency, phase-sensitive detector/discriminator. Method describes operation of said devices.

EFFECT: higher reliability.

3 cl, 15 dwg

FIELD: electric engineering.

SUBSTANCE: device has ferroelectric memory cell in form of thin ferroelectric polymer film, two electrodes, while at least one of said electrodes has at least one contact layer, which has conductive polymer in contact with memory cell, and if necessary has second layer in from of metallic film in contact with conductive polymer. Method for manufacturing ferroelectric memory contour includes operations for applying on substrate of first contact layer in from of thin film of conductive polymer and applying thin ferroelectric polymer film on first contact layer and second contact layer on thin ferroelectric polymer film.

EFFECT: increased polarization level of ferro-electric memory cell and decreased field strength.

2 cl, 12 dwg, 3 ex

FIELD: ferroelectric or electret memorizing contour (C) .

SUBSTANCE: ferroelectric or electret memorizing contour has memory cell with ferroelectric or electret memorizing material, and two electrodes, while one of electrodes has at least one functional material, capable of physical and/or chemical incorporation of atomic or molecular particles in its volume, aforementioned particles contained in electrode or in memorizing material of memory cell.

EFFECT: increased resistance to wear: minimization of wear processes in memorizing devices, based on organic and, in particular, polymer electrets and ferroelectrics.

2 cl, 11 dwg

FIELD: engineering of devices for storing and/or processing data, based on utilization of thin ferroelectric films, in particular, engineering of ferroelectric or electret three-dimensional memorizing devices.

SUBSTANCE: device has stack of memorizing arrays, formed of two or more ribbon structures, stacked one on another or intertwined with each other, while each ribbon structure has flexible substrate of non electro-conductive material, at least one electrode layer and a layer of memorizing material.

EFFECT: expanded functional capabilities.

12 cl, 9 dwg

FIELD: engineering of devices, containing functional elements forming a planar set.

SUBSTANCE: in electrode matrix, containing first and second thin-film electrode layers L1, L2 with electrodes ε in form of stripe electric conductors in each layer, electrodes ε are separated from each other only by thin film 6 of electrically insulated material, thickness of which is a small portion of electrodes width and which passes along at least side edges of electrodes, forming isolating walls 6a between them. Electrode layers L1, L2 are subjected to planarization to provide for high level of planarity of layers. In dev, containing one or more electrode matrices EM, electrode layers L1, L2 of each matrix are mutually oriented in such a way, that their electrodes 1, 2 intersect or are positioned mutually perpendicularly. Between electrodes 1,2 in form of whole layer functional environment 3 is held, as a result of which device with matrix addressing is formed (preferably passive), which can be utilized, for example, as device for processing or storing data with matrix addressing, containing individually addressed functional elements 5, in form of logical cells or memory cells respectively. Coefficient of filling for separate layer of functional environment 3 by aforementioned cells is close to 1, while maximal number of cells in device approaches A/f2, where A - surface area of functional environment, held between electrode layers L1, L2, and f - minimal size achievable by technological means.

EFFECT: increased efficiency of addressing and increased recording density of stored data.

3 cl, 30 dwg

FIELD: technology for reading information from device with passive matrix addressing, possible use in sensor devices with individually addressed cells on basis of polarized material.

SUBSTANCE: device with passive matrix addressing of individual cells contains electrically polarized material having hysteresis, first and second sets of parallel electrodes, forming controlling buses and data buses, which in overlapping zones within volume of polarized material form cells, containing capacitor-like structures, and also has control means and detection means. Method describes process for reading data from aforementioned device.

EFFECT: prevented obstructing voltages and leak currents during destructive reading of cells, possible parallel reading of several cells.

2 cl, 4 dwg

FIELD: engineering of devices of volumetric data storage.

SUBSTANCE: device has multiple memorizing devices M with matrix addressing, each one of memorizing devices contains two electrode matrices in form of parallel electrode layers, forming controlling buses and data buses, while electrodes of each electrode matrix are made with high position density and isolated from each other by barrier layer with thickness, being a portion of electrodes thickness, while upper surface of one electrode matrix, directed to next electrode matrix, is provided by parallel grooves, directed orthogonally relatively to electrodes and spatially separated from one another by spaces, close to width of electrodes.

EFFECT: high density of data storage.

6 cl, 19 dwg

FIELD: technologies for storing data in energy-independent ferroelectric memory with variable selection.

SUBSTANCE: each method includes recording multiple identical copies of data to multiple memory zones, first controlling line is read, containing at least first copy of multiple identical copies of data, read data are repeatedly recorded into the same controlling line, read data are transferred to logical memory control contour, reading of whole next controlling line is performed, containing, at least, next copy of multiple identical copies of aforementioned data, data are recorded into same controlling line, from where aforementioned data were read, data are transferred to logical memory control contour, and operations are repeated further until all identical copies of data are transferred to logical memory control contour, errors in binary code are detected, in case of detection of errors corrected data are repeatedly recorded to memory zones where errors were detected.

EFFECT: possible maintenance of integrity of stored data.

2 cl, 8 dwg

FIELD: technology for manufacturing ferro-electric memory cells and engineering of ferroelectric memory device.

SUBSTANCE: aforementioned memory device contains ferroelectric memory cells, at least two sets of electrodes, parallel to other electrodes of set, while electrodes of one are set are positioned practically orthogonally to electrodes of closest next set of electrodes. Method for manufacturing aforementioned memory cells in composition of aforementioned memory device includes forming first electrode, containing at least one layer of metal and at least one metal-oxide layer, above first electrode ferroelectric layer is applied, consisting of thin film of ferroelectric polymer, and then onto this ferroelectric layer at least second electrode is applied, contains at least one layer of metal and at least one metal-oxide layer.

EFFECT: high surface density of cells, possible application of upper electrodes without damage to ferro-electric memory material.

2 cl, 7 dwg

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