The receiver clock
The invention relates to radio engineering. The technical result is to reduce the time input in synchronism. The invention consists in that the device comprises a shift register, a detector code combination clock, drive out of synchronism, power generating equipment, channel allocator and the elements of logic (schematic AND NOT), and also contains a set of n processing units, each of which contains m-bit shift register and the switch, while the outputs of the switches connected to the inputs of detector combination clock. 1 Il.
The invention relates to the field of digital technology and can be used in the apparatus of signal processing satellite communication lines with a temporary seal.
In digital communication systems are used for frame synchronization as the concentrated and dispersed code combination signals. The requirements for providing frame synchronization contradictory: input in synchronism must occur as quickly as possible and stay as long as possible.
In the communication lines operating at reglas conditions, when you have to work at low ratios of signal to noise and high probability of distortion of the characters, these requirements can be difficult, especially for signals with distributed code combinations, since each human failure synchronize takes a long time to log in synchronism, since the enumeration of all possible temporal positions of the clock is made using the method of exclusion a single clock cycle of the clock frequency of the monitored signal, which corresponds to the transition to the neighboring bits. The exception stage commands from deciding the schemes in the absence of synchronism for four frames.
So, if the length of podagra M=32 bits, the frame length N=32 podagra and decisions about the timing for K=4 personnel will need to log in synchronism V bits
V=M× N×× M130 kbit
that is a significant loss when transmitting telegraphic information and data transfer, and does not meet the requirements ensure good quality at the receiving side.
Another drawback of this version of the build of the receiver clock is the inability to work on distributed code combinations, if the bits of sinkingracing known to the receiver , containing the detector code combination of HR signals, the output of which is connected to the first inputs of the first and second points of convergence, as well as staffing the counter, the input of which is the input clock frequency of the device, the third element matches the inverter and the drive, the entrance of which is output through the inverter connected to the second input of the second element of coincidence, the output of which is connected to the fault input of the HR counter, the output of which is connected to the second input of the first element matches and the first input of the third element of coincidence, the second input is combined with the input of the counter personnel, thus the outputs of the first and third elements of coincidence connected to the inputs of the cumulative counter.
The disadvantage of this receiver is the inability to work on distributed code combinations of signals as evenly distributed over the length of the frame, and, moreover, are unevenly distributed in different word length and the structure of the signals.
The use of the principle of enumeration of all the temporal position of the synchronization signal allows to solve the problem of work on distributed signals, the time input in synchronism status is howling synchronization also, you cannot work on distributed unevenly on the length of the frame sync signals.
To ensure frame synchronization when concentrated code combinations of known clock receiver clock , taken as a prototype, containing a shift register, a decoder, the scheme NO scheme And the drive input in synchronism, the drive is out of synchronism, the scheme of the recovery clock frequency, generating equipment and channel allocator.
The disadvantage of this receiver is the inability to work on the signals from the distributed signals with different structures and capacity, as well as the increase in the time input in synchronism with small ratios of signal to noise, because the Recognizer clock is used by the decoder for error-free code combination, and not the correlator with settable threshold.
The aim of the invention is to reduce the time input in synchronism (increased robustness) and the provision of work under arbitrary concentrated, uniformly and non-uniformly dispersed signals.
To achieve this goal is proposed receiver clock containing sequentially soy is in synchronism, the drive out of synchronism, a second circuit matches, generating equipment (TH) and channel allocator, while the output of the second schema matching is connected to the second input drive input in synchronism and the second input drive out of synchronism, and the second output generating equipment connected to the second input of the first circuit of coincidence and through the element it is up to the third input of the drive out of synchronism, the output of detector combination clock is also connected to the second input element is NOT present and the second schema matching. According to the invention, it introduced n (bit clock) series-connected units consisting of series-connected m (the number of bits in podagra or the number of bits between adjacent bits dispersed clock)-bit shift registers and switches the outputs are connected to the inputs of detector combination of the synchronization signal, and an information input of the first m-bit shift register is connected with the second input channel of the distributor, with the information input of the receiver clock is the first input of the first m-bit shift register, the clock inputs are objectory input generator equipment, and outputs of the receiver clock are outputs of the channel allocator.
The combination of distinctive features and characteristics of the present invention from the literature are not known, the solution is not obvious, so it meets the criteria of novelty and inventive step.
The drawing shows a diagram of the proposed receiver. The receiver contains a serially connected set of n series-connected m-bit shift registers 11...1nand switches 21...2nconsistently United detector combination 3, the first schema And 4, the drive input in synchronism 5, the drive out of synchronism 6, the second scheme And 7, generating equipment 8, channel distributor 9, and the element NO 10. The inputs of detector combination 3 is connected to the outputs of the switches 21...2nand the output to the first input element NO 10 and the second input circuit And 7, the output of which is connected to the second inputs of the drive input in synchronism 5 and drive out of synchronism 6, the output of generator equipment 8 is connected to the second inputs of the element NO 10 and scheme and 4, the output of element NO 10 is connected to the third input of the drive you the tour), detector combination 3 is made in the form of a correlator with an adjustable threshold.
The device operates in two modes
The 2 switches are installed on the first bits of the shift registers 1, resulting in a n-bit shift register of the first triggers shift registers 11...1nand the receiver is ready for operation focused on code combinations.
Multicast flow, accompanied by a clock frequency supplied to the detector 3 in parallel with switches 2l...2n. Each combination of the synchronization signal causes the detector 3, the formation of a signal at its output. If the receiver is not in synchronism, the first response of the detector 3 through the circuit And 4 will set TH 8 in the initial state. The following response of the detector 3 when the coincidence of his response to the clock signal from TH 8 through the circuit And 4 will be written into the drive input in synchronism 5. Following the coincidence in time of the signal from the detector 3 and 8 will cause the overflow of the block 5 and the installation in the zero state unit 6, that is, the receiver entered into synchronism. When false combinations of the timing response of the detector 3 and 8 do not coincide in time and the receiver is not in synchronism.
When the ADC is Radka, or under the influence of noise, the output signal from the FIRST 8 passes through the element NO 10 and fills the counter drive out of synchronism 6. However, if the block 6 is not full, then the failure of the synchronization does not occur, and at the first signal from block 5 drive 6 is set to zero. If the block 6 full, the receiver out of synchronism and the sign-in process in synchronism repeated.
2. Work on timing evenly or unevenly distributed along the length of the frame.
Let the bit clock 20 bits, the structure of the clock 1011.00001010.1110.1101, length podagra 32 bits, i.e., between adjacent bits synchroprint 31 are information bits.
Perform initial setup of the receiver.
Switches 21...220connect to 32-bits shift registers 11...120in the result, each 32 bits registers 11...120arrives at the detector and the input of the next register. The other 2 switches21...2nleave closed, which is equivalent to masking of the detector 3. Custom detector 3 code combination to trigger by tripping it with2 errors in the code combination of the clock.
Next, the process of logging in synchronism, their retention and exit of synchronism is similar to the previously described processes for concentrated code combinations.
Since the input in synchronism takes 3-4 frame, the time input in synchronism reduced from 130 Kbps up to 4,096 kbps, i.e., provided the gain in time by three orders of magnitude, which increases the noise immunity of the receiver.
When unevenly distributed bits clock on the length of the frame using 2 switches1...2nset codes bit numbers, taken from registers 11...1non the detector, otherwise the operation is the same as described above.
At the moment of submission of application materials in MIERS tested the efficiency of the device and its feasibility, the positive results.
It should be noted that the capabilities of modern programmable logic integrated circuits (FPGAs) allow you to implement a listener on one or two chips.
As a result, the notes as determined, and diffuse signals; reduced time input in synchronism by two-three orders of magnitude for distributed code combinations; increased robustness of the receiver through the use of the detector correlator with adjustable threshold.
1. Application No. 57-5377 (Japan). A collection of "Inventions in the USSR and abroad".
2. L. S. Levin, M. L. Plotkin. Digital transmission systems. - M.: Radio and communication, 1982.
The receiver clock containing a detector connected in series combination clock, the first schema matching, the drive input in synchronism, the drive is out of synchronism, a second circuit matches, generating equipment and channel allocator, while the output of the second schema matching is connected to the second input drive input in synchronism and the second input drive out of synchronism, and the second output generating equipment connected to the second input of the first circuit of coincidence and through the element it is up to the third input of the drive out of synchronism, the detector output code combination clock is also connected to the second inputs of the element is oasa of series-connected m-bit shift registers and switches the outputs are connected to the inputs of detector combination of the synchronization signal, and an information input of the first m-bit shift register is connected with the second input channel of the distributor, with the information input of the receiver clock is the first input of the first m-bit shift register, the clock inputs are combined second input m-bit shift registers, a second input detector combination clock and a second input of the generator equipment, and the outputs of the receiver clock are outputs of the channel allocator.
FIELD: digital communications.
SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.
EFFECT: higher reliability, higher effectiveness, higher interference resistance.
1 cl, 3 dwg
SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.
EFFECT: higher trustworthiness.
FIELD: digital communications;
SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.
EFFECT: enlarged functional capabilities.
1 cl, 2 dwg
FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.
SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.
EFFECT: enhanced noise immunity.
1 cl, 1 dwg
FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.
SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.
EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.
FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.
SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.
EFFECT: increased interference resistance of device for cyclic synchronization.
FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.
SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.
EFFECT: expanded functional capabilities of device for cyclic synchronization.
2 cl, 3 dwg
FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.
SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.
EFFECT: increased interference resistance of cyclic synchronization.
FIELD: data processing in broadband radio communications and radio navigation.
SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.
EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.
2 cl, 9 dwg
FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.
SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.
EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.
1 cl, 9 dwg