The receiver clock

 

The invention relates to radio engineering. The technical result is to reduce the time input in synchronism. The invention consists in that the device comprises a shift register, a detector code combination clock, drive out of synchronism, power generating equipment, channel allocator and the elements of logic (schematic AND NOT), and also contains a set of n processing units, each of which contains m-bit shift register and the switch, while the outputs of the switches connected to the inputs of detector combination clock. 1 Il.

The invention relates to the field of digital technology and can be used in the apparatus of signal processing satellite communication lines with a temporary seal.

In digital communication systems are used for frame synchronization as the concentrated and dispersed code combination signals. The requirements for providing frame synchronization contradictory: input in synchronism must occur as quickly as possible and stay as long as possible.

In the communication lines operating at reglas conditions, when you have to work at low ratios of signal to noise and high probability of distortion of the characters, these requirements can be difficult, especially for signals with distributed code combinations, since each human failure synchronize takes a long time to log in synchronism, since the enumeration of all possible temporal positions of the clock is made using the method of exclusion a single clock cycle of the clock frequency of the monitored signal, which corresponds to the transition to the neighboring bits. The exception stage commands from deciding the schemes in the absence of synchronism for four frames.

So, if the length of podagra M=32 bits, the frame length N=32 podagra and decisions about the timing for K=4 personnel will need to log in synchronism V bits

V=M× N×× M130 kbit

that is a significant loss when transmitting telegraphic information and data transfer, and does not meet the requirements ensure good quality at the receiving side.

Another drawback of this version of the build of the receiver clock is the inability to work on distributed code combinations, if the bits of sinkingracing known to the receiver [1], containing the detector code combination of HR signals, the output of which is connected to the first inputs of the first and second points of convergence, as well as staffing the counter, the input of which is the input clock frequency of the device, the third element matches the inverter and the drive, the entrance of which is output through the inverter connected to the second input of the second element of coincidence, the output of which is connected to the fault input of the HR counter, the output of which is connected to the second input of the first element matches and the first input of the third element of coincidence, the second input is combined with the input of the counter personnel, thus the outputs of the first and third elements of coincidence connected to the inputs of the cumulative counter.

The disadvantage of this receiver is the inability to work on distributed code combinations of signals as evenly distributed over the length of the frame, and, moreover, are unevenly distributed in different word length and the structure of the signals.

The use of the principle of enumeration of all the temporal position of the synchronization signal allows to solve the problem of work on distributed signals, the time input in synchronism status is howling synchronization also, you cannot work on distributed unevenly on the length of the frame sync signals.

To ensure frame synchronization when concentrated code combinations of known clock receiver clock [2], taken as a prototype, containing a shift register, a decoder, the scheme NO scheme And the drive input in synchronism, the drive is out of synchronism, the scheme of the recovery clock frequency, generating equipment and channel allocator.

The disadvantage of this receiver is the inability to work on the signals from the distributed signals with different structures and capacity, as well as the increase in the time input in synchronism with small ratios of signal to noise, because the Recognizer clock is used by the decoder for error-free code combination, and not the correlator with settable threshold.

The aim of the invention is to reduce the time input in synchronism (increased robustness) and the provision of work under arbitrary concentrated, uniformly and non-uniformly dispersed signals.

To achieve this goal is proposed receiver clock containing sequentially soy is in synchronism, the drive out of synchronism, a second circuit matches, generating equipment (TH) and channel allocator, while the output of the second schema matching is connected to the second input drive input in synchronism and the second input drive out of synchronism, and the second output generating equipment connected to the second input of the first circuit of coincidence and through the element it is up to the third input of the drive out of synchronism, the output of detector combination clock is also connected to the second input element is NOT present and the second schema matching. According to the invention, it introduced n (bit clock) series-connected units consisting of series-connected m (the number of bits in podagra or the number of bits between adjacent bits dispersed clock)-bit shift registers and switches the outputs are connected to the inputs of detector combination of the synchronization signal, and an information input of the first m-bit shift register is connected with the second input channel of the distributor, with the information input of the receiver clock is the first input of the first m-bit shift register, the clock inputs are objectory input generator equipment, and outputs of the receiver clock are outputs of the channel allocator.

The combination of distinctive features and characteristics of the present invention from the literature are not known, the solution is not obvious, so it meets the criteria of novelty and inventive step.

The drawing shows a diagram of the proposed receiver. The receiver contains a serially connected set of n series-connected m-bit shift registers 11...1nand switches 21...2nconsistently United detector combination 3, the first schema And 4, the drive input in synchronism 5, the drive out of synchronism 6, the second scheme And 7, generating equipment 8, channel distributor 9, and the element NO 10. The inputs of detector combination 3 is connected to the outputs of the switches 21...2nand the output to the first input element NO 10 and the second input circuit And 7, the output of which is connected to the second inputs of the drive input in synchronism 5 and drive out of synchronism 6, the output of generator equipment 8 is connected to the second inputs of the element NO 10 and scheme and 4, the output of element NO 10 is connected to the third input of the drive you the tour), detector combination 3 is made in the form of a correlator with an adjustable threshold.

The device operates in two modes

The 2 switches are installed on the first bits of the shift registers 1, resulting in a n-bit shift register of the first triggers shift registers 11...1nand the receiver is ready for operation focused on code combinations.

Multicast flow, accompanied by a clock frequency supplied to the detector 3 in parallel with switches 2l...2n. Each combination of the synchronization signal causes the detector 3, the formation of a signal at its output. If the receiver is not in synchronism, the first response of the detector 3 through the circuit And 4 will set TH 8 in the initial state. The following response of the detector 3 when the coincidence of his response to the clock signal from TH 8 through the circuit And 4 will be written into the drive input in synchronism 5. Following the coincidence in time of the signal from the detector 3 and 8 will cause the overflow of the block 5 and the installation in the zero state unit 6, that is, the receiver entered into synchronism. When false combinations of the timing response of the detector 3 and 8 do not coincide in time and the receiver is not in synchronism.

When the ADC is Radka, or under the influence of noise, the output signal from the FIRST 8 passes through the element NO 10 and fills the counter drive out of synchronism 6. However, if the block 6 is not full, then the failure of the synchronization does not occur, and at the first signal from block 5 drive 6 is set to zero. If the block 6 full, the receiver out of synchronism and the sign-in process in synchronism repeated.

2. Work on timing evenly or unevenly distributed along the length of the frame.

Let the bit clock 20 bits, the structure of the clock 1011.00001010.1110.1101, length podagra 32 bits, i.e., between adjacent bits synchroprint 31 are information bits.

Perform initial setup of the receiver.

Switches 21...220connect to 32-bits shift registers 11...120in the result, each 32 bits registers 11...120arrives at the detector and the input of the next register. The other 2 switches21...2nleave closed, which is equivalent to masking of the detector 3. Custom detector 3 code combination to trigger by tripping it with2 errors in the code combination of the clock.

2. Thus, the detector 3 receives data from twenty switches 21...220with the delay on each of 32 bits. The other switches are closed.

Next, the process of logging in synchronism, their retention and exit of synchronism is similar to the previously described processes for concentrated code combinations.

Since the input in synchronism takes 3-4 frame, the time input in synchronism reduced from 130 Kbps up to 4,096 kbps, i.e., provided the gain in time by three orders of magnitude, which increases the noise immunity of the receiver.

When unevenly distributed bits clock on the length of the frame using 2 switches1...2nset codes bit numbers, taken from registers 11...1non the detector, otherwise the operation is the same as described above.

At the moment of submission of application materials in MIERS tested the efficiency of the device and its feasibility, the positive results.

It should be noted that the capabilities of modern programmable logic integrated circuits (FPGAs) allow you to implement a listener on one or two chips.

As a result, the notes as determined, and diffuse signals; reduced time input in synchronism by two-three orders of magnitude for distributed code combinations; increased robustness of the receiver through the use of the detector correlator with adjustable threshold.

Literature.

1. Application No. 57-5377 (Japan). A collection of "Inventions in the USSR and abroad".

2. L. S. Levin, M. L. Plotkin. Digital transmission systems. - M.: Radio and communication, 1982.

Claims

The receiver clock containing a detector connected in series combination clock, the first schema matching, the drive input in synchronism, the drive is out of synchronism, a second circuit matches, generating equipment and channel allocator, while the output of the second schema matching is connected to the second input drive input in synchronism and the second input drive out of synchronism, and the second output generating equipment connected to the second input of the first circuit of coincidence and through the element it is up to the third input of the drive out of synchronism, the detector output code combination clock is also connected to the second inputs of the element is oasa of series-connected m-bit shift registers and switches the outputs are connected to the inputs of detector combination of the synchronization signal, and an information input of the first m-bit shift register is connected with the second input channel of the distributor, with the information input of the receiver clock is the first input of the first m-bit shift register, the clock inputs are combined second input m-bit shift registers, a second input detector combination clock and a second input of the generator equipment, and the outputs of the receiver clock are outputs of the channel allocator.



 

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