A method and apparatus for automatic gain control and exception offset constant component in the receiver with quadrature demodulation

 

The invention relates to receivers. The technical result is the removal of the bias DC component. The AGC device includes an amplifier (At) with adjustable gain (KU). Step-down Converter (PP) with a quadrature demodulator, connected to, serves to convert the frequency of the output signal (S) modulating frequency. Two active low pass filter (LPF) with high QU provide suppression mnediateka With in the frequency band of the modulating C. the suppressor passing the DC component (PS) suppresses the substation issued by the PM and LPF. The AGC device also generates power taken on the basis of the power output C. Saturating integrator compares the received power With a reference and generates adjustment KU by integrating or abstention from it on the basis of the reference values, the received power With and gain control. 4 N. and 7 C.p. f-crystals, 13 ill.

The technical field

The present invention relates mainly to HF receiver with quadrature demodulation. In particular, the present invention relates to a new method and apparatus for automatic the digital receiver.

Prior art

In analog receivers, such as those used in FM systems, cellular radio, use FM-modulator to highlight the information encoded in the phase of the incident signal. Existing FM modulators often include analog frequency discriminator, which is faced analog limiter to maintain the input signal power at a constant level. In this case, the input of frequency discriminator supported maximum signal-to-noise ratio in the whole dynamic range of the input FM signal. However, this method of processing analog signals, as a rule, determines the filtering advanced signals and is often implemented using a large number of elements. In addition, it is shown that it is possible to achieve high operational performance through the use of linear digital demodulation signals, not analog demodulation. Unfortunately, conventional methods of demodulation is often inapplicable to digital receivers, since the restriction of a received signal can cause distortion obtained on the basis of his information.

Digital receiver for receiving subjected to digital modulation information signals the population. The process gain of a received signal using a control signal referred to as automatic gain control (AGC). Usually in digital receivers AGC process causes the measurement of the output power amplifier with variable gain. The measured value is compared with a value representing the desired power signal, and generates a control signal for the amplifier with adjustable gain. Then the magnitude of the error is used to adjust the gain of the amplifier so that the signal level consistent with the desired signal power. To perform digital demodulation with optimal signal-to-noise ratio, use automatic gain control to maintain the amplitude of the modulating signal, close to the entire width of the dynamic range of the frequency band of the modulating signals, analog-to-digital converters. However, this requires, as a rule, to provide automatic gain control in the whole dynamic range of the power of the received signal.

Under conditions of cellular systems digital receiver can receive the signal, whose power of preterea the new phone mobile object with negotitations access, code-division multiplexing (MDCRC) and negotitations access with time division multiplexing (MDRC), it is necessary to adjust the power of the demodulated signal for proper signal processing. However, as in MDCRC or MTURK compatible receivers and conventional WC-compatible receivers, i.e., dual-mode digital/FM receivers, it is necessary to provide a power control as broadband MDCRC signals (or MTURK signals), and narrowband FM signals. The adjustment process is complicated by the presence of different dynamic ranges associated with the received power FM and MDCRC signals. That is, the amplitude of the received FM signals may change in dynamic range over 100 dB, while MDCRC systems usually leads to a more limited dynamic range, for example approximately 80 dB. The presence of the AGC circuits for each mode increases the complexity of the hardware and the cost of such receivers. It is therefore desirable to develop an AGC circuit capable of operating with both narrowband FM signals with a wide dynamic range and broadband MDCRC signals over a limited dynamic range.

It is also desirable to develop a digital AGC in low-cost receivers that use analog-to-digital converters (ADC) with restricted is above 100 dB, and relatively inexpensive eight-bit ADC will have a dynamic range limited to 48 dB, the introduction of cost ARU would provide the possibility of adjusting the gain of the receiver preceding the ADC to adjust the dynamic range of the signal in the ADC. The alternative is to use expensive ADC with greater dynamic range, increase the value of the receiver or with the increase of the AGC range of the analog part of the receiver, which is very difficult and expensive.

Therefore, it is necessary to develop new and improved AGC circuit, which has advantages compared to known arrangements and methods ARU.

In the standard FM cell-phone AGC function performs a scheme called limiter. When using the limiter, suppression mnediateka signal can only be performed using filters, intermediate frequency (H). Although the required capacity of the suppression of signals can be achieved by using ceramic filters if they, as a rule, are relatively large in size and expensive. Smaller and less expensive filters FC, as a rule, you cannot perform so that they possess the desired characteristics suppression with the technology of integrated circuits (ICS) made it possible to design active filters bandwidth of the modulating signals, which are very small and inexpensive compared to the filters of the inverter. Hence, it would be desirable to use active filters bandwidth of the modulating signal on the basis of IP to exercise significant suppression unidiomatic signals, receiving for this opportunity to use smaller and less expensive filters FC to mitigate any additional desired signal. In the active filter, the higher the gain, the better the suppression can be obtained. But the higher the gain, the more susceptible the system is undesirable displacements of the permanent component. The suppression of such displacement is permanent component is desirable in order to maximize the dynamic range of the available signal, to minimize the distortion of the demodulated baseband signal caused by the DC offset, and to minimize errors in the estimates of the level of the modulating signal, caused by the DC offset.

In standard digital systems, such as systems with four-phase shift keying (Cpfm) used in the standard MDCRC-communication systems (and some MDRC systems, or systems with a two-position phase maniutenam frequency to frequency, located in the frequency band of the modulating signal having an average value level of the permanent component. In this case, the bias DC component easily excluded, because the carrier, as a rule, still oppressed by the transmitter. Therefore, in the frequency band of the modulating signals, you can use the constant component failure.

However, for modulation with a constant amplitude, such as FM and coherent phase manipulation (FMN) (which is used in FM systems, cell phones, such as automatic message processing (automatic message processing system - AMP)) (SAOS) and Gaussian minimum shift keying (Gmmn) (used in some MDRC systems), the carrier should be retained for demodulation of a received signal.

The use of active filters bandwidth of the modulating signal on the basis of IP makes it necessary to provide some mechanism to suppress unwanted displacements of the permanent component. The circuit of the signal processing FC standard digital receivers, cell phones, typically includes a local oscillator (lo (G) having a frequency selected so that the carrier frequency is reduced to the level of the DC component. For example iltr-tube) constant component. If the world Cup, FMN or Gmmn signal is processed using a processing circuit frequencies, the suppression of the bias DC component eliminating not only undesirable movement of the permanent component, but also an important amplitude and phase information on the frequency of the carrier. That is, in FM systems cell phones is important amplitude and phase information on the frequency of the carrier, and if that information to destroy, you will be provided with a negative impact on the performance of the system.

However, there are two narrow bands of frequencies between the carrier frequency Fcand Fc+F1and between Fcand Fc-F1(where F1expected lowest frequency in the spectrum of the demodulated signals; usually F1=300 Hz for cell FM systems), which can be suppressed without adversely affecting the demodulated signal. Although intermodulation components and contains minimal verbal information at frequencies close to the carrier frequency, these compounds are rare and have a relatively short duration. Therefore, the suppression of only the low-frequency intermodulation components after conversion with decreasing frequency bandwidth of the modulating signal usually does not lead to the loss of PAA at frequencies below Fl= (baud rate symbol)/100, so the band between Fcand Fc+F1you can suppress without destruction of digital information.

A brief statement of the substance of the invention

The present invention is the task of developing a new and improved AGC circuit, which has advantages compared to known arrangements and methods ARU.

Another technical task of the present invention is to design a receiver with quadrature demodulation, in which you can use active filters bandwidth of the modulating signals with high gain and high selectivity without loss of information on the carrier frequency.

The problem is solved by creating an automatic gain control to compensate for changes in the power of a received signal containing an amplifier with adjustable gain, having an input for receiving the received signal, an output for generating an output signal having a certain frequency, and a control input for receiving signal gain control, which according to the invention contains:

step-down Converter connected to the output polos frequencies of the modulating signals, moreover, the step-down Converter converts the carrier frequency of the output signal in a certain frequency band of the modulating signals, shifted by the specified amount of the fixed payment

a filter connected to the step-down Converter, for removing DC bias offset, and a signal modulating signal to generate a filtered signal,

a power detector connected to the filter for generating a signal power level in response to the power of the filtered signal,

an integrator having a first input coupled to the power detector and a second input for receiving the reference frequency signal, and is designed to generate a signal gain control for selective integration of a difference between the reference signal and the signal power level,

a control logic device for selective formation of integrable difference when the signal gain is less than the first threshold value and greater than the second threshold value.

Preferably the step-down Converter includes:

the intermediate frequency filter connected to the output of the amplifier with adjustable the output from the generator and filter intermediate frequency, to generate at least one component of a frequency band of the modulating signals in response to the reference frequency signal and an output signal

at least one low pass filter connected to the mixer, for generating at least one transfer function for low frequencies of the at least one component of a frequency band of the modulating signals.

It is advisable that the device was designed for operation in mode multiple access code division multiplexing (MDCRC) or in the mode of frequency modulation, and at least one low pass filter contained the first filter mode MDCRC and the second filter mode frequency modulation.

Beneficial to the integrator contains a switch controlled logical control device, when this switch is in the closed position connects the signal power level to the input of the integrator, and in the open position, the capacitor maintains the input to the integrator, at any level, from among a certain set of specified voltage levels.

According to the second aspect of the automatic gain control to compensate for changes in power prinimaemogo signal, output for generating an output signal having a certain frequency, and a control input for receiving an analog signal gain control, according to the invention the device includes

step-down Converter connected to the output, for down-converting the frequency of the output signal and receiving a modulating signal having a certain frequency band of the modulating signals, and the step-down Converter converts the carrier frequency of the output signal in a certain frequency band of the modulating signals, shifted by the specified amount of the fixed payment

at least one analog-to-digital Converter, which transmits the signal bandwidth of the modulating signals at least one signal of a frequency band of the modulating signals, each analog-to-digital Converter generates a digital representation of a signal frequency band of the modulating signals,

a filter, coupled to at least one analog-to-digital Converter, for generating at least one filtered signal,

a power detector connected to the filter, for generating a signal power level in response at modesti signal with a preset reference signal and generating the error signal, moreover, the integrator generates the digital signal gain control through selective integration of the error signal in response to values of the error signal and the digital signal gain control, and

digital to analog Converter connected between the integrator and amplifier with adjustable gain and designed to generate an analog signal gain control of the digital signal gain control.

Preferably, the integrator contains:

the schema subtraction, connected to the power detector, for generating the error signal in response to the difference between the power level signal and a given reference signal,

scale factor, coupled with the schema subtraction, to generate scaled the error signal by multiplying the error signal by a first constant when the value of the signal power is reduced, and multiplied by a second constant, when the value of signal power increases, and

drive, coupled with large-scale multiplier, for generating the digital signal gain control by accumulating the scaled signal massagesalon Orehova value, when the accumulated scaled the error signal is reduced to a minimum predetermined threshold value, and supports the digital signal gain control at maximum set threshold value when the accumulated scaled the error signal increases to a maximum predetermined threshold value.

It is advisable that the device contains a low pass filter connecting the d / a Converter with amplifier with adjustable gain.

The problem is solved also by creating a way to offset changes in power of the received signal in the automatic gain control having an amplifier with an adjustable gain, which has an input for receiving the received signal, an output for generating an output signal having a certain frequency, and a control input for receiving signal gain, which is that:

convert the lower frequency output signal to obtain a signal of a frequency band of the modulating signals having a certain frequency band of the modulating signals,

generate a filtered signal by removal the level of the power signal in response to the power of the filtered signal, and

generate a signal gain control through selective integration of a difference between the signal power level and a reference signal.

It is advisable that when generating the adjustment signal amplification was performed by integrating the difference only in the case when the value of signal gain exceeds the minimum threshold value and is smaller than the maximum threshold value.

According to another aspect of the invention, the method of compensation of changes in the power of a received signal in the automatic gain control having an amplifier with an adjustable gain, which has an input for receiving the received signal, an output for generating an output signal having a certain frequency, and a control input for receiving an analog signal gain control, is that:

convert the lower frequency output signal to obtain at least one modulating signal having a certain frequency band of the modulating signals,

generate a digital representation of each of the respective baseband signal,

generate at least one filtered si signal power level in response to at least one filtered signal,

compare the signal power level with a reference signal to generate the error signal,

generate the digital signal gain control through selective integration of the error signal in response to values of the error signal and the digital signal gain control, and

convert the digital signal gain control in the analog signal gain control.

It is useful to have when generating the digital signal gain control was carried out by the operation of integration of the error signal only when the value of the digital signal gain control exceeds the minimum threshold value and is smaller than the maximum threshold value.

The present invention is a new method of automatic gain control and adjusting device power received RF signal in a wide dynamic range. In a preferred embodiment, the automatic gain control can be configured to provide the specified control response to different fading characteristics of the received RF signal. In applications where the signal of interest is presented in which the coherent phase modulation with constant envelope, such as Hmmn, FMN or FM (used in mobile phase systems with SAOS), the proposed device is able to provide the necessary gain control, suppression unidiomatic signals and converting with decreasing frequency until the frequency of the modulating signal without bias DC component.

In accordance with the present invention, an apparatus for automatic gain control (AGC) for dual mode receiver to compensate for changes in power of the received signal. The AGC device includes an amplifier with an adjustable gain, having an input for receiving the received signal, a control input for receiving signal gain and output for delivery of the output signal. Connected to the output of the step-down Converter serves to convert the frequency of the output signal at the frequency of the modulating signal, thus generating a modulating signal. In a preferred embodiment, the step-down Converter is used to convert a frequency of the modulating signal to the output signal at the modulating frequency is shifted by the specified amount of DC component. Contour suppression of signals passing constant sostavlyajushie is issued step-down Converter, providing, thus, the presence of compensated baseband signal.

The AGC device further comprises a means of generating power of a received signal based on the output power. Saturating the generator compares the power of a received signal with a reference signal and generates a signal gain control by integrating or refraining from integration on the basis of the values of the reference signal power of a received signal and a signal gain control.

Brief description of drawings

Distinguishing features and advantages of the present invention are explained below with reference to the accompanying drawings, in which:

Fig.1 depicts a block diagram of a variant of the device using the proposed automatic gain control (AGC) according to the invention;

Fig.2 depicts a graph of the gain of the AGC amplifier depending on the voltage gain, according to the invention;

Fig.3 depicts a block diagram of a variant of the proposed device, automatic gain control, which includes control loop in analog form, according to the invention;

Fig.4A and 4B depict PE is of the limiter signal, included in the proposed device gain control, according to the invention;

Fig.5 depicts a variant embodiment of the logic used to control the operation of the control switch integrator according to the invention;

Fig.6A-6C are timing diagrams illustrating operation of the proposed AGC device according to the invention;

Fig.7 depicts the preferred embodiment of the proposed device ARU, including digital implementation of the control loop, according to the invention;

Fig.8 depicts a variant embodiment of the digital saturating accumulating register included in the integrator shown in Fig.7, according to the invention;

Fig.9 depicts another preferred variant implementation of the proposed AGC circuit, which includes the contour suppression of signals passing constant component, according to the invention;

Fig.10 depicts a block diagram of the analog circuit suppression of signals passing constant component, according to the invention.

Detailed description of preferred embodiments of the invention

In a digital receiver, such as used in digital cellular communication device with mgtadalafil at a constant level. Under conditions of cellular systems, the receiver can receive the signal, the power of which is changing rapidly in a wide range of values. In order to properly process the digital information contained in a received signal, it is necessary to adjust the signal power in the receiver. In dual-mode digital receiver, i.e., in a digital receiver capable of processing and MDCRC signals (or MTURK signals), and the standard FM signals, the dynamic range of the received signal may vary depending on the selected operating mode. It is therefore proposed that the automatic gain control for a digital receiver, which is able in each of the operating modes to compensate for the deviation of the power of a received signal in any of the two systems of signals.

The automatic gain control built into the transceiver of the portable cellular MDCRC phone 10 (Fig.1). The phone 10 may be dual mode, i.e. MDCRC-compatible (or MDRC-compatible) and conventional FM compatible. We offer the automatic gain control is able to provide power regulation and broadband MDCRC signals (or MTURK signals), and narrowband FM signals. The opportunity this is and capacity when creating a listener.

The phone 10 includes an antenna 12 for receiving RF signals, including MDCRC signals or FM signals transmitted from the base station. Antenna 12 provides a flow of the signals received on the antenna switch 14, which generates received signals in the receiving part of the phone 10. The antenna switch also accepts MDCRC - or H-communication signals from the transmitter of the phone 10 to issue them to the antenna 12 and the transmission to the base station.

Received signals are issued from the antenna switch 14 on the step-down Converter 16, where RF signals are converted into signals of a range of lower frequencies, and issued forth as the corresponding signals to intermediate frequency (if). The frequencies from the down-Converter 16 serves on the RF amplifier 18 with automatically adjustable gain. The frequencies are amplified with a gain level determined by the AGC signal (VARU), who also served on the amplifier 18. The amplifier 18 is able to provide a linear gain control over a wide dynamic range, such as in excess of 80 dB, on the basis of VARU. Amplifier 18 may have the construction disclosed, for example, in U.S. patent No. 5099204 “Linear amplifier with adjustable gain”.

In vysheupomjanutoe regulation. In specific embodiments, implementation of such regulation may be provided by the circuit gain in the absence of a compensation scheme. Among such embodiments include, for example, those in which several stages of amplification are combined in a cascade. Similarly, it is possible due to the presence of the high voltage source of the power to exclude the compensation scheme.

The frequencies of the adjustable gain of the amplifier 18 receives the second step-down Converter 20, where the frequencies are converted into signals of a range of lower frequencies, and issued forth as the corresponding in-phase and quadrature baseband signals ICCand Qbb. In the variant shown in Fig.1, the modulating signals in the operating mode MDCRC represent the I - and Q-samples encoded digital output data for further phase demodulation and correlation. In dual mode receiver step-down Converter 20 also lowers the frequency of the FM signals with the formation of modulating the FM phase and quadrature signals, which are then subjected to the phase/frequency demodulation with the formation of the audio output.

The detector 25 measures the level of the signals issued by the step-down Converter 20, and the generating system is PN (ARUP), issued by the controller (Fig.1 not shown), serves on the schema 22 saturating integrator. The signal AROOP corresponds to the desired signal to baseband signals. The controller also generates the reference signals of the extremely low level AGC (ARUNIS) and an extremely high level AGC (AROWS) at saturating integrator 22. Signals ARUNIS and AROWS correspond to the limits of variation of signal amplitude gain control (VARU) supplied to the control input of the amplifier 18 saturating integrator 22.

In Fig.2 shows that there is clearly a nonlinear characteristic of the gain of amplifier 18 at a relatively constant voltage regulation, exceeding the level AROWS and smaller than the level ARUNIS. Generally, it is desirable to limit the magnitude of VARUthe linear range between the levels AROWS and ARUNIS, corresponding to the time constant of the control loop remains in an acceptable range. Deviation time constant of this circuit is within the acceptable range could lead to significant errors in the control loop.

As indicated below, saturating integrator 22 is designed to integrate the difference between the signals Pupil should cause an increase of the VARUto levels above the level AGC HIGH, or fall to a value less than the level ARUNIS, the integrator 22 stops the integration, and the signal gain of VAruis kept constant, either at the level AROWYN, or at the level ARUNIS, which, as described above, improves the response of the control loop.

Saturating integrator 22 (Fig.1) receives the signal of the PUPS from the detector 25 together with the signal AROOP from the controller. To ensure accurate gain control, as a rule, it is necessary to minimize the difference between the signal PUPS and signal AROOP. Saturating integrator 22 is used to perform this function in the AGC circuit by reducing this difference to zero. For example, if the gain is too large, the signal PUPS will also be a high signal compared to the signal AROOP. While these signals will not be signals of equal amplitude, the output signal VARUthe integrator will continue to reduce the gain of the amplifier 18.

It should be understood that measuring the PUPS can be performed at various points during the processing of the received signal. Although in Fig.1 shows that such a measurement is carried out after lowering the frequency step-down Converter 20, it can be about Aut after filtering of the signal, thus minimizing power structurepoint interference in the measurements. When using analog methods of capacity control as in the case of broadband, and narrowband signals, you can use the same schema adjust the power for both modes of operation.

With regard to the transmitting part 30 of the portable telephone shown, and it is regulated by the power of multiple transmitted signals. For ongoing transmitted power control mode MDCRC also uses the signal VARU. The signal VARUissued in the transmitting part 30 together with various other control signals from a controller (not shown).

In Fig.3 depicts an exemplary variant of the proposed device, automatic gain control, which includes a partially analog implementation saturating integrator 22. Saturating the integrator includes an integrator 40 with an operational amplifier with capacitive feedback circuit. In particular, the integrator 40 receives the signal AROOP through a resistor 42 to its reinvestiruet the entrance to which is also connected to the capacitor 43. When the switch 44 is closed in response to control information provided is m 40 through resistor 50. When the switch 44 is held in the open position in response to the control information with decision logic circuit 46 integrator capacitor 52 serves to maintain the output signal (VARU) integrator 40 constant level AROWYN, or at the level ARUNIS. This prevents saturation of the amplifier 18 when the amplitude of the input if signal is outside the specified dynamic range.

RF switches 49 and 55 connect the bandpass filter 51 MDCRC-frequencies to the amplifier 18 and the inverter mode MDCRC, which corresponds to the setting of the switches shown in Fig.3. In FM mode the position of the RF switch 49 and 55 is changed to connect the bandpass filter 53 FM frequencies and the limiter 54 to the amplifier 18 of the inverter. Band-pass filter 53 FM frequencies to suppress unediapeedani interference determines the bandwidth of the FM signal applied through the limiter 54 to the amplifier 18 of the inverter. For example, when operating in the FM mode filter 53 FM frequencies must have a passband width of approximately one cell channel (e.g., 30 kHz) and lane keeping, the boundaries of which are considerably removed (for example, the value of ±60 kHz) from the average frequency range of the inverter. During operation, MDCRC RK signals, supplied to the amplifier 18. For example, in MDCRC band-pass filter 51 MDCRC signals of the inverter can provide a bandwidth corresponding to the repetition rate of the elementary assumptions of the modulating signals of the receiver (for example, of 1.26 MHz), and provides the specified bandwidth suppression (for example, n of 1.8 MHz). In another embodiment, the limiter 54 can stand in the overall chain before the power amplifier 18 FC.

The limiter 54 attenuates RF signals of high power, which are mainly taken during operation in the FM mode. FM signals can have more power than the power of the signals that have to deal with when working in the mode MDCRC. In a preferred embodiment of the invention, the limiter 54 limits the input power of the signal applied to the amplifier 18, a dynamic range of, for example, 80 dB typical for mode MDCRC. The limiter 54 allows to obtain the desired control range of the circuit of the automatic gain control (AGC) on the basis of the expected dynamic range MDCRC, thereby eliminating the need for a separate calibrated AGC control loops to work in FM and MDCRC.

In Fig.4A and 4B are displayed, for which nicities 54. It should be noted that the limiter 54 does not weaken the signal having the voltage amplitude is less than the specified maximum voltage Vm. The saturation power can be set as pSAT=Vm2/2PLwhere pldenotes the impedance of the input load of the amplifier 18. If the input power exceeds psthe power of the output signal produced by limiter 54, is maintained constant at about the level of psatby limiting the peak voltage of the signal voltage Vm. A value of PSATyou should choose based on the maximum expected level of the input power mode MDCRC. Therefore, a sinusoidal input signal of the inverter high power (PIN>PSAT) cause the output signal produced by limiter 54, is cut to a fixed amplitude, but has the same basic frequency, and phase information is not lost. Harmonic distortion introduced by the limiter, exclude, filter 56 of the lower frequencies.

The filter 56 of the lower frequencies included in the step-down Converter 20 must have a cutoff frequency greater than the frequency of the if signal at the output of the amplifier 18 in the mode MDCRC or FM. As noted above, filter, what eigenem frequency and formation of in-phase (I) and quadrature (shifted in phase by 90° Q) components. The limited availability of limiter 54 signals high power causes the creation of unwanted harmonics. The filter 56 of the lower frequency range of the inverter eliminates unwanted harmonics, so they are not converted in the frequency band of the modulating signals along with the desired information contained in the frequencies. In the described embodiment, the type, order, and limit the bandwidth of the filter 56 is chosen so as to make the attenuation distortion components in the frequency band of the modulating signals arising from harmonics of the inverter contained in amplifying the if signal produced by the amplifier 18.

The filtered if signal is fed to the first input of the mixer 60, while the other input to the mixer 60 receives the reference signal generated by the local oscillator generator 64. The mixer 60 mixes the filtered if signal with a reference signal to obtain the I - and Q-(quadrature) components of the baseband signals on the output lines 70 and 12, respectively. The mixer 60 is designed to convert a frequency which is offset from the intermediate frequency range of the inverter at a specified distance, for example, from 3 to 300 Hz, the frequency of the constant component of the modulating signal. This offset field of the permanent sostarivanie FM signal (i.e., undamped harmonic signal NG signal) from error due to bias DC component at the input. In particular, the mixer 60 is preferably will generate the output frequency of approximately 100 Hz in response to the input NG-signal at the assigned frequency range of the inverter. Thus, errors due to bias DC component at the input, causing distortion of the results of determining the signal strength of the PUPS are excluded notch filter 66 DC component without loss of information enclosed in NG signal.

The output line 70 (Fig.3) and 72 are connected respectively with circuits 76 and 78 low-pass filters the I - and Q-channel baseband signals. Each of the circuits 76 and 78 filters preferable to provide when operating in modes FM and MDCRC transfer function in the range of lower frequencies, the cutoff frequency of 13 kHz and 630 kHz, respectively. In the specified embodiment of the invention, each filter 76 and 78 includes a pair of filters, one of which is used when operating in mode MDCRC, and the other when in FM mode. The individual filters included in the schema filters 76 and 78, switch to the I - and Q-channel baseband signals, respectively, depending on R. the treatment filters included in the schema filters, in accordance with the selected mode of operation.

In addition to the performance of its functions and the functions of protection against aliasing ADC 86 and 88 filters 76 and 78 of the lower frequencies also provide suppression unidiomatic signals. In a preferred embodiment, the filters 76 and 78 have high gain and provide suppression in a wide swath of retaining. As a result of this bandpass filters 51 and 53 of the inverter can have more than a narrow strip of delaying and therefore be less expensive.

After filtration through circuits 76, 78 filters baseband signals and narrow-band notch filter 66 DC component of the received baseband signals I - and Q-channels are fed to the detector 48 signals the PUPS. The detector 48 signals the TOY produces an output signal of the TOY, showing the measured signal power (in dB). The difference between the signal PUPS, issued by the detector 48 signals the PUPS and signal AROOP, integrated in the saturating integrator 22 to obtain voltage regulation VAru.

I - and Q-outputs of the circuits 76 and 78 filters baseband signals are also connected to the I - and Q-channels analog-to-digital converters ADC 86 and 88, respectively, ADC 86 and 88 provide kVA is egime MDCRC, or FM mode. In a preferred embodiment, the dynamic range of the ADC 86 and 88 is chosen such that it was sufficient for approval by the signals, which are expected to deal in the range of control provided by the device AGC amplifier 18 of the inverter. As noted above, the logic circuit 46 in saturating integrator 22 limits the voltage regulation VARUrange ARUNIS<VARU<AROWS. This protects the amplifier 18 from saturation and working in a non-linear operating characteristics.

Therefore, the ADC 86 and 88 are arranged so as to quantize the input signals without significant distortion regardless, saturated integrator 40, or not. In the preferred embodiment, each of the ADC 86 and 88 provides 6-8 bits of dynamic range. This dynamic range is sufficient to prevent the lowering of the signal-to-noise ratio of the input to the ADC 86 and 88 in comparison with the signal-to-noise ratio of the quantized digital output of the ADC 86 and 88 for any input level RF signals. For example, when VARUreaches the level ARUNIS, the limiter 54 limits the amplitude of the RF signal. Thus, the signal level at ADC input 86 and 88 may exceed the ur is to be accurately quantize the modulating signals at a higher level.

Similarly, the dynamic range of the ADC 86 and 88 is sufficient to prevent the lowering of the signal-to-noise ratio at low levels of input modulating RF signals. For example, when VARUreaches AROWS and the switch 44 is opened, if the input RF signal continues to decrease, the level of the modulating signal at the ADC input 86 and 88 falls below the level specified value AROOP. Reduced level signal to the ADC 86 and 88, leads to the use of the device is not full, i.e., some bits of the ADC output 86 and 88 are not used. At high input RF signals in the conversion process uses the entire dynamic range of the ADC 86 and 88. Therefore, the proposed device AGC enables you to use the control circuit AGC when demodulation of signals occupying a much greater range than the control range of the amplifier 18 of the inverter. A variant embodiment of the logic circuit 46, which is designed to control the position of switch 44 shown in Fig.5. Signals AROWS and VARUserved on a logical comparator 104. When VARUexceeds the level AROWYN, the output of comparator 104 appears logical unit “1”. The output signal of the comparator 104 about the mini-unit “1” because of the closed position of the switch 44. The output signal of the trigger 110 is delayed by the delay element 114 to prevent excessive caused structurepoint a hindrance, actuation of switch 44. The logical element “And” 108 and delay element 114 are intended to prevent opening of the switch 44 until then, until some specified period of time after its closure. The level of the output signal of the logical element “And” 108 changes from low to high, thus causing the transfer of the output signal of the trigger 110 to a logic level zero “0”, a logical zero “0” at the output of the logical element “And 130 and the opening of switch 44. When the switch 44 is opened, the signal PUPS and signal AROOP no longer supported equal through the circuit. When the level AROWYN exceeded and the circuit is open, the signal PUPS indicates a signal level smaller than the AGC OP, and the output logic of the comparator 102 there is a logical zero “0”. When the signal AROOP exceeds the level AROOP, the level of the output signal of the comparator 102 becomes high, and the level of the output signal of the logical element “And” 108 becomes too high, thus causing the transfer of the output ical element And 106 are similar to delay element 114 and the logical element “And” 108 and prevent the closure of the switch 44 until until a specified period of time after opening.

Analog the sequence of logical operations performed when the level of the input RF signal exceeds the range of AGC. When VARUdrops below ARUNIS, the output of comparator 118 appears logical unit “1”. The output signal of the comparator 118 is passed through the logical element “And” together with the output trigger signal 124, which is a logical unit of “1” when the switch 44 is closed. After that there is the transfer of the output signal of the logic element 122 from low to high, thus causing the transfer of the output trigger signal 124 to logic level zero “0”. This causes a logical zero “0” at the output of the logical element And 130, which leads to opening of the switch 44. When the switch 44 is open, the circuit no longer supports the signal PUPS equal to the signal AROOP. When the circuit is open, the signal PUPS will be more AROOP, and the output logic of the comparator 116 is a logical zero “0”. When the signal becomes smaller PUPS AROOP, there is a transfer of the output signals of the comparator 116 and a logic element 120 at a high level. This transfer mustache and logical elements “And” 120 and 122 are similar to delay element 114 and the logical element “And” 108 and serve to prevent very rapid actuation of the switch 44 from the open position to the closed and Vice versa.

Signal logic output logic element And 130 can be viewed as a signal of preparation for integration, shown by a bus 124 control switch connected to the switch 44. In a preferred embodiment, the switch 44 is closed in response to the issuance of a logical unit of “1” through the control bus 124 and opens in response to the issuance of a logical zero “0” through this bus. Logic circuit 46 integrator manages, when the integrator 40 with an operational amplifier integrates the difference signal of the PUPS and AROOP. Thus, the logic circuit 46 of the integrator and the integrator 40 interact, forming a voltage VARU. The AGC device (Fig.3) can be described more with reference to the timing diagram (Fig.6A-6C), showing the change with time of the power approximate RF signal and the corresponding position (closed or open) switch 44 in the saturating integrator 22. In Fig.6C shows the corresponding voltage gain VARUgenerated by the integrator 40 with an operational amplifier in response to the input RF signal (Fig.6A).

On the first integration interval (to<1<t1) power is<VARU<AROWS (Fig.6C). At time t=t1logic circuit 46 of the integrator determines that the voltage VARUreached level ARUNIS, and then opens the switch 44. The switch 44 remains open for a time interval t1<t<t2during which the integrator 40 is not integrates the difference between the PUPS and AROOP. During this time, the output signal of the ADC 86 and 88 is limited by limiter 54. At time t=t2the power of the input RF signal again becomes less than the value defined by the upper limit of the range control circuit that causes the logic circuit 46 integrator closes the switch 44, and VARUexceeds the level ARUNIS. After that, the switch 44 remains closed on the second integration interval (t2<t<t3) up until the voltage regulation VARUreaches a level AROWYN, and at this point, the logic circuitry 46 of the integrator again opens the switch 44. In this period of time the output signal of the ADC 86 and 88 is changed in response to changes in the level of the input RF signal. Similarly, logic circuit 46 integrator closes the switch 44 at the moments t4, t6and t8to start the third, the fourth realizatio saturating integrator 22, using the digital filter 150 of the upper frequencies, but not the notch filter 66 DC component, to eliminate bias DC component in the samples of the baseband I - and Q-channels generated by FTP 86 and 88. The cutoff frequency of the filter 150 is chosen much smaller than the frequency offset introduced in the mixer 60. In an alternative embodiment, it is possible to achieve exception offset DC component by:

separate determination of the average values of samples of the baseband I - and Q-channels, and

subtracting the resulting DC component from each component of the I - and Q-signals for further processing.

Digital detector 154, the PUPS should, as a rule, to include a mapping table containing the values of the logarithm of the power in function of the amplitudes of the samples of the baseband I - and Q-channels. Digital integrator 154 approximates the logarithm of the power, i.e. 10LOG (I2+Q2by measuring the value of LOG (MAX {ABS(I), ABS(Q)}) and the value component of the amendment. Operation MAX {ABS(I), ABS(Q)} gives the output value equal to the amplitude of the largest component of this pair of samples (I/Q-signals. In a specific embodiment, this output value is the pointer to access neobrazovana, then add to the magnitude of the component of the amendments is approximately equal to the difference between the LOG (I2+Q2) and LOG (MAX {ABS(I), ABS(Q)}).

Assess the power of the received signal, i.e. the signal of the PUPS produced by the detector 154 baby-doll, served on digital subtraction unit 158 together with the signal AROOP. The resulting error signal is then scaled scaling multiplier 162 in accordance with the desired time constant tthe contour. The time constant tcontour is chosen in accordance with the characteristics of the fading of the input RF signal. As a rule, you should choose a relatively small time constants (faster firing circuit) to provide tracking signals with steep fading characteristics, not slowing down the trigger circuit to a level that does not cause excessive delay or “ringing”, which is determined by the delay introduced into the loop filters and other elements.

In a preferred embodiment, the scaling multiplier 162 can be programmed to multiply the error signal from myCitadel 158 on the first time constant circuit in response to the descending signals the PUPS and multiplication on the second posti in the tuning response of the AGC circuit based on the characteristics of fading, inherent in the working equipment, and minimizes the delay of the path.

The scaled error signal generated scaling multiplier 162 (Fig.7), served on saturating the memory 166. Register 166 accumulates the scaled values of error signals with the formation of the integrated error signal as long as the signal accumulated error reaches a level AROWS or level ARUNIS. Then the signal value of the accumulated error support or level AROWYN, or at the level ARUNIS until then, until it is adopted, the scaled error signal, which when combined with the existing signal accumulated error signals accumulated errors in the range bounded by the levels AROWS and ARUNIS.

Option saturating drive 166 with discretizations in time shown in Fig.8. The scaled error signal is fed to the first input of the digital adder 170. The scaled error signal is summed in a digital adder 170 with integrated error signal resulting from the previous time interval saturating storing register 166, and the integrated error signal is memorized in the register 174. Values AROWS and ARUNIS supplied by a system controller (not shown), the th register 178, limit value of the digital signal outputted to the first register 174, range, limited levels AROWS and ARUNIS.

Digital filter implementation 150 of the upper frequency detector 154 PUPS and saturating oscillator 22 lets get serious advantages compared to analog implementations. For example, used digital items are not subject to variance parameters under the influence of temperature and allow you to adjust the time constant in accordance with the expected terms, to make signals using the circuit. In addition, the filter and the integrator implemented in digital form, occupy a much smaller volume than the corresponding design of discrete resistive and capacitive elements.

It is assumed that the digital detector PUPS and digital saturating integrator will lead to improved accuracy. In particular, during the period when the value of VARUyou want to maintain any level AROWYN, or at the level ARUNIS, capacitive discharge associated with analog elements will, as a rule, lead to “sagging” (relative decrease) value of VARUfrom the desired level via a hinge downturn), characteristic for the analog devices.

The control signal stored in the register 174 saturating drive 166, is fed to digital to analog Converter (DAC) 190. In a preferred embodiment, the resolution of the DAC 190 will be sufficient to ensure that the size of the output analog step AGC less than 1 dB. In another embodiment, the generated sequence is subjected to density-modulation (PIM) or pulse-width modulation (PWM) output pulses of levels of logic zero “0” and a logical unit is “1” in response to the control signal. The average value of the voltage sequence output pulses corresponds to the desired analog voltage output signal.

The analog output signal produced DAC 190, passes through the filter 194 lower frequencies before applying to the control input of the gain amplifier 18 of the inverter. The filter 194 lower frequencies designed to mitigate any output noise generated by the DAC 190.

Referring now to Fig.9, note that there is depicted another preferred variant of the proposed AGC circuit, which is designed to suppress unwanted signal components bias DC component without odstepny similar to the AGC circuit, is depicted in Fig.7. As noted above, in the receiver with digital modulation, such as Cfmn or Dpfm, the General rule is that such a choice lo frequency (G) in the processing chain of frequencies that the carrier frequency of the received signal is reduced (i.e., convert) to a DC component. However, here the subsequent baseband processing, designed to suppress unwanted signals passing constant component, noise mixer 60, also tends to the destruction of the information signal, centered around the accepted carrier, which is manifested in such modulation, as the world Cup and coherent phase shift keying.

In accordance with one aspect of the invention the frequency of the local oscillator generator 64 FC are chosen so that the carrier frequency of the received signal converted into a baseband frequency that is offset from the DC component by a specified amount. The circuit 200 suppression of signals passing constant component allows to exclude the passage of unwanted DC component while maintaining at the same time, the information signal on the adopted carrier frequency. In a preferred embodiment, the frequency of the local oscillator is chosen offset by a lowly is extra with decreasing frequency until the frequency band of the modulating signals. It follows that the energy of the signals I - and Q-channels generated by the mixer 60, at a given frequency offset (e.g., 100 Hz) corresponds to the information recorded in the carrier frequency of received signals. Range of low frequencies, including information contained in the carrier, is skipped in the ADC 86, 88, whereas the unwanted signal passing the DC component from the mixer 60 is suppressed. Although this process leads to a decrease in energy at a frequency that is offset from the assumed carrier frequency by a specified amount, in many cases (for example, when transmitting voice data) energy suppressed low frequency shall be a minimum of useful information signal. Therefore, the circuit 200 suppress the DC component mainly eliminates alien signal passing the DC component without destroying the information present on the carrier frequency of received signals.

The circuit 200 (Fig.9) suppression of signals passing constant component includes a digital integrator 204 and 206 I - and Q-channels with inputs that are functionally connected to the outputs of the filters 76 and 78 of the lower frequencies through ADC 86 and 886, respectively. In the described embodiment, the integrators 204 and 206 are designed for integrirovanie the digital-to-analogue converters (DAC) 208 and 210 of the I - and Q-channels, located between the integrators 204 and 208 and analog blocks subtraction 212 and 214. The constant gain of the integrators 204 and 206 can be chosen so that the integrators 204 and 206 will not respond to the signal power at frequencies of 100 Hz and above. The received signals exceptions DC component generated by the integrators 204 and 206, nominally equal to the offset errors unwanted DC component introduced with the passage of signals by the mixer 60, the filters 76 and 78 of the lower frequencies and ADC 86 and 88. Thus, it is guaranteed that the power level applied to the ADC 86 and 88, and hence to the circuit 154 baby-doll is indicative of the power level of the signals actually received by the circuit 22 ARU. Therefore, the circuit 200 suppression of signals passing constant component operates to maintain the integrity of the power level of a received signal even during eliminate unwanted signals passing the DC component.

Analog implementation of the circuit 230 suppression of signals passing constant component that can be installed in the circuit in Fig.9 instead of the circuit 200 shown in Fig.10. The circuit 230 is designed to eliminate unwanted signals passing constant sotirova generator 64 FC (Fig.9) are chosen so that to convert the carrier frequency in the frequency of the modulating signal, offset from the DC component by a specified amount. The circuit 230 provides suppression of signals passing through a permanent part of the way, essentially the same as that which was described with reference to suppression circuit 200, i.e., with the exception of unwanted signals passing the DC component while preserving the information signal on the adopted carrier frequency. In particular, through appropriate selection of the gain of the integrators 234 and 238, the information contained in the carrier frequency subjected to the conversion down to frequency offset is passed to the ADC 86 and 88. As discussed above, then the unwanted signal passing the DC component from the mixer 60 is suppressed by blocks 212 and 214 of the subtraction.

The circuit 230 suppression of signals passing the DC component also ensures that the power of the modulating signal applied to the ADC 86 and 88, and hence the detector 154 baby-doll, is a measure of the power of the signal received on fact, and not destroyed alien signals constant component.

In the specified embodiment of the invention may photoby adapted to receive the received FM signals, the corresponding “multi-tone” analog signals. In particular, adopted the FM signal can be represented in the form of “multi-tone” signal consisting of a group of stationary, i.e., having a fixed frequency components of the FM signal, in which each stationary component corresponds to the amplitude or step specific analog tone. This may require conversion of low-frequency intermodulation components. Therefore, if the local oscillator generator 64 makes a static frequency offset, it is possible to convert specific intermodulation components in the mixer 60 in modulating the DC component, i.e., the conversion to the same modulating frequency, which may be a signal passing a DC component. In this case, it may be difficult to identify the differences between the undesirable passage of the constant component of the information enclosed in the useful signal converted by the mixer 60 in modulating the DC component. Because the circuits 200 and 230 suppression of signals passing the DC component, as a rule, intended to exclude essentially all the signal energy is constant component, lname penetrating signal DC component.

In accordance with another aspect of the invention this difficulty is overcome by using a modulator 260 offset of the local oscillator, designed to make the time-varying variations in the DC offset applied at the nominal frequency of the local oscillator. The term “nominal” frequency lo refers to the frequency at which adopted the average carrier frequency is converted to a frequency modulating DC component using a mixer 60. Because in this case, the frequency offset DC component applied to the mixer 60, not static, but varies within a given range, accept stationary components will not be continuously transformed in modulating the DC component, but instead will be converted to baseband frequency based on the deviation of the offset of the local oscillator. Therefore, the useful low-frequency intermodulation components can be distinguished from unwanted passage of a constant component, as the penetrating signal DC component remains at the level of the modulating DC component, regardless of the deviation of the frequency offset applied to the lo signal. So modelmania constant component, while retaining certain information stationary signal.

The offset frequency modulated made to the nominal frequency of the local oscillator, can be characterized in terms of: average frequency offset, the minimum and maximum frequency offset and modulation frequency offset, i.e., the speed at which varies the offset between the minimum and maximum frequency offset. For example, in a particular embodiment, the average frequency offset is chosen equal to 100 Hz, the minimum and maximum offset is chosen equal to 50 Hz and 150 Hz, and the modulation frequency offset is set to 10 Hz.

If you use the option to build Cmcm or Gmmn receiver, the ADC output 86 and 88 connected to the FM demodulator (not shown). Modulating the signal introduced by the demodulator 260 offset of the local oscillator (in the preferred embodiment, 10 Hz) can be easily deleted after FM demodulation using a digital high-pass filter with cutoff frequency, which is somewhat higher than the maximum frequency shift modulator 260 offset lo, without negative impact on sound quality.

Claims

1. The automatic gain control to compensate from the entrance to reception of the received signal, output for generating an output signal having a certain frequency, and a control input for receiving signal gain control, characterized in that it contains step-down Converter connected to the output for down-converting the frequency of the output signal and receiving a modulating signal having a certain frequency band of the modulating signals, and the step-down Converter converts the carrier frequency of the output signal in a certain frequency band of the modulating signals, shifted by a specified amount from the constant component, a filter connected to the step-down Converter, for removing DC bias offset, and a signal modulating signal to generate a filtered signal, a power detector, connected to the filter for generating a signal power level in response to the power of the filtered signal, the integrator having a first input coupled to the power detector and a second input for receiving the reference frequency signal, and is designed to generate a signal gain control for selective integration of a difference between the reference signal and the signal power level, the control logic condition is I less than the first threshold value and greater than the second threshold value.

2. The device under item 1, characterized in that the step-down Converter includes an intermediate frequency filter connected to the output of the amplifier with adjustable gain, a generator for generating the reference frequency signal, a mixer connected to a generator and a filter intermediate frequency to generate at least one component of a frequency band of the modulating signals in response to the reference frequency signal and the output signal, at least one low pass filter connected to the mixer, for generating at least one transfer function for low frequencies of the at least one component of a frequency band of the modulating signals.

3. The device according to p. 2, characterized in that it is designed to work in the mode of multiple access code division multiplexing (MDCRC) or frequency modulation, in this case, at least one low pass filter includes a first filter mode MDCRC and the second filter mode frequency modulation.

4. The device under item 1, characterized in that the integrator contains a switch that controlled the power to the input of the integrator in the open position, the capacitor maintains the input to the integrator, at any level, from among a certain set of specified voltage levels.

5. The automatic gain control to compensate for changes in the power of a received signal containing an amplifier with adjustable gain, having an input for receiving the received signal, an output for generating an output signal having a certain frequency, and a control input for receiving an analog signal gain control, characterized in that it contains step-down Converter connected to the output, for down-converting the frequency of the output signal and receiving a modulating signal having a certain frequency band of the modulating signals, and the step-down Converter converts the carrier frequency of the output signal in a certain frequency band of the modulating signals, shifted by the specified amount of DC component, at least one analog-to-digital Converter, which transmits the signal bandwidth of the modulating signals at least one signal of a frequency band of the modulating signals, each analog-to-digital Converter generates a digital representation of a signal frequency band of the modulating signal, a filter connected to at least one analog-to-digital prinny filter, to generate the signal power level in response at least one filtered signal, an integrator coupled to the power detector, for comparing the power level of the signal with the predetermined reference signal and generating the error signal, and the integrator generates the digital signal gain control through selective integration of the error signal in response to values of the error signal and the digital signal gain control, and a digital to analog Converter connected between the integrator and amplifier with adjustable gain and designed to generate an analog signal gain control of the digital signal gain control.

6. The device under item 5, wherein the integrator includes a subtractor, connected to the power detector, for generating the error signal in response to the difference between the power level signal and a given reference signal, scale factor, coupled with the schema subtraction, to generate scaled the error signal by multiplying the error signal by a first constant, when the value of signal power poligeenan with a scale factor, to generate the digital signal gain control by accumulating the scaled signal mismatch, and the specified tape drive supports the digital signal gain control at minimum specified threshold value when the accumulated scaled the error signal is reduced to a minimum predetermined threshold value, and supports the digital signal gain control at maximum set threshold value when the accumulated scaled the error signal increases to a maximum predetermined threshold value.

7. The device under item 5, characterized in that it contains a low pass filter connecting the d / a Converter with amplifier with adjustable gain.

8. The method of compensation of any change in power of the received signal in the automatic gain control having an amplifier with an adjustable gain, which has an input for receiving the received signal, an output for generating an output signal having a certain frequency, and a control input for receiving signal gain control, namely, that transform with penitentary bandwidth of the modulating signals, generate a filtered signal by removing the error signal offset DC component in the frequency band of the modulating signals, generating a power level signal in response to the power of the filtered signal and generate a signal gain control through selective integration of a difference between the signal power level and a reference signal.

9. The method according to p. 8, characterized in that for generating a signal gain control exercised by integrating the difference only in the case when the value of signal gain exceeds the minimum threshold value and is smaller than the maximum threshold value.

10. Way limit the changes in power of the received signal in the automatic gain control having an amplifier with an adjustable gain, which has an input for receiving the received signal, an output for generating an output signal having a certain frequency, and a control input for receiving an analog signal gain control, namely, that convert the lower frequency output signal to obtain at least one baseband signal, and the existing baseband signal, generate at least one filtered signal by filtering the digital representations of the at least one baseband signal, generate a signal power level in response to at least one filtered signal, comparing the signal power level with a reference signal to generate the error signal, generate a digital signal gain control through selective integration of the error signal in response to values of the error signal and the digital signal gain control and convert the digital signal gain control in the analog signal gain control.

11. The method according to p. 10, wherein when generating the digital signal gain control perform the operation of integration of the error signal only when the value of the digital signal gain control exceeds the minimum threshold value and is smaller than the maximum threshold value.



 

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SUBSTANCE: proposed controllable optical amplifier designed to transfer wavelength-multiplexing signals has, respectively, first gain control device (OE1, OE2, R1) and second dominating control device (OE2, R2, R1) having much slower output power control characteristic (Pout)in compliance with basic sold power (Psold). Transmission lines equipped with such amplifiers are characterized in that both fast changes in level and slow changes in attenuation can be compensated for in them.

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8 cl, 3 dwg

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