Device to control the retrieval of text documents in the information database

 

The invention relates to computing. Its use allows to obtain a technical result in improved performance of the device by introducing a hierarchy of document types and their classification by subject area and time. The device contains five registers two address selector, element, And three delay elements, groups of elements OR three elements And. the Technical result is achieved that the device introduced three cases and two address selector, two reversible counter, the block select the search direction, two element And three element OR. Code and the number of the desired document are received at the inputs of respectively the first and third registers. 3 Il.

The invention relates to computing, and in particular to devices for controlling retrieval of text and graphic documents in the information database.

Feature solved the technical problem is that the users of an information database could obtain documents not only for some of the predefined identification signs, but also to carry out tiny device, which could be used to solve the task [1, 2].

The first known device contains blocks receiving and storing data, connected to the control blocks and data blocks search and selection, connected to the blocks of the data storage and display, the clock inputs are connected to outputs of control unit [1].

A significant disadvantage of this device consists in the impossibility of nding documents in the information database in the absence of a complete set of identification features of the required document.

Known and other device containing first and second memory blocks, registers the first and second groups, registers, triggers the one-shot, elements OR groups of elements AND, OR, elements of the delay and pulse shapers [2].

The last of the above technical solutions closest to being described.

Its disadvantage lies in the fact that the search of the required documents is tightly tied to the need to specify the full set of identification features, which is the section address of memory block, which is the required document.

The purpose of the invention is to improve performance usta.

This objective is achieved in that in the known device, containing the first register, the information inputs which are the first information input of the clock input is the clock input of the device, and the outputs are connected to information inputs of the first selector addresses, the clock input of which is the clock input devices, and information outputs connected to information inputs of the second register, a clock input connected to the clock output of the first selector address, and the outputs of the second register are the first information output device, the third register, the information inputs which are second information input device, the clock input is connected to the output of the first element And and outputs connected to information inputs of the second selector addresses, the clock input of which is connected to the output of the first element And the fourth register, the information input of which is connected to the information output of the second selector addresses, the clock input is connected to the synchronizing output of the second selector address, and outputs connected to the first input match is on connected to the synchronizing output of the second selector address, the fifth register, the information input of which is connected to the inputs of the respective elements OR groups, the clock input coupled to the output element OR the input of which is connected to the outputs of the first, second and third delay elements, and the output element OR is the clock output devices, elements, And the second and third groups whose outputs are connected to inputs of the respective elements OR groups, the second and third elements, And entered the block select the search direction, the first, second, third and fourth control inputs of which are the first, second, third and fourth control inputs of the device, respectively, a first control unit output is connected to one input elements And the first group and with the same inputs of the first and third elements And other inputs which are connected to the synchronizing output of the first selector address, the second control unit output is connected to the third input of the first element And to one input of the second element And the other input of which is connected to the synchronizing output of the first selector address, the third control output unit connected to the third input of the second element And with the same inputs of elements And the second group, the other input of the m input of the third element And one input elements And the third group, other inputs are connected to the output of the third delay element.

The device has also entered the sixth register, the information input which is the third information input device, and a clock input connected to the output of the second element And the first reversible counter, totalizer and subtractive inputs of which are connected with the fifth and sixth control outputs block selection of the search direction, and outputs connected to other inputs of elements And the second group, the third selector address, data inputs which are connected to the outputs of the sixth register, the clock input connected to the output of the second element And information outputs the third address selector connected to information inputs of the first reversible counter, and the clock output is connected to the clock input of the first reversible counter, the seventh case, the information input which is the fourth information input device, and a clock input connected to the output of the third element And the second reversible counter, totalizer and subtractive inputs of which are connected with the seventh and eighth control outputs block selection of the search direction, and outputs connected to other WMO and the seventh register, clock input connected to the output of the third element And information outputs of the fourth selector addresses connected to information inputs of the second reversible counter, and a clock output connected to the clock input of the second reversible counter, the second element OR the input of which is connected to the fifth and sixth control outputs block selection of the search direction and the clock output of the third selector address, and the output connected to the input of the second delay element and the third element, OR, the inputs of which are connected with the seventh and eighth control outputs block selection of the search direction and the clock output of the fourth selector address, and the output connected to the input of the third delay element.

The invention is illustrated by drawings, where Fig.1 shows a block diagram of the device of Fig.2 is a block diagram of the address selector 11 to 14, and Fig.3 shows an example of a specific structural embodiment of the block select the direction of the search.

The device (Fig.1) contains the first 1, second 2, third 3, fourth 4 fifth 5 sixth 6 and 7 seventh registers, the first 8 and second 9 reversible counters, block 10 select the search direction, the first 11, second 12, third 13 and fourth is retu 21 group elements And, a group of 22 elements OR the first 23 and second 24 25 and the third delay elements, the second 26 and third 27 OR elements.

In Fig.1 also shows a synchronizing input device 30, the first 31, second 32 and third 33, 34 fourth information input device, the first 35 and second 36, third 37 and 38 fourth control inputs of the device, the first 39 and second 40 installation unit 10.

In addition, in Fig.1 shows the first 41 and second 42 information output device, which synchronizes the output device 43, and the first 44 and second 45, 46 third, fourth, 47, 48 fifth, sixth, 49, 50 seventh and eighth 51 control outputs block selection of the search direction.

The selector address 11-14 (Fig.2) contains a decoder 55, the first 56 and second 57, 58 third elements And groups, block 59 memory, made in the form of a persistent storage device, the element 60 OR the first 61 and second 62 elements of the delay. The drawing also shows an information input of the selector 63, the clock input of the selector 64, and an information output 65 and the clock output 66.

The block select the search direction 10 (Fig.3) contains the first 67 and second 68 triggers the first 69, 70 second, third 71 and 72 fourth elements, and the elements 73, 74 OR. The drawing also shows the first 35, the WTO is a and device and control outputs 44-51.

All nodes and elements of the device are made on the standard of potentially switching elements.

The device operates as follows.

For clarity of illustration of the operation of the device will divide all text documents in the information database, the type of their use into three categories:

- patents

- application of FIPS

- cases involving proceedings for the proposals to pass.

Before you begin the unit, all of its units and the units are installed in their original state by pressing the Reset button, which is pressed whenever the user navigates to a new cycle of work (to simplify the drawing, the Reset key and installation chain assemblies and units in the original position not shown)

If necessary, search for any of these types of documents the user on the remote control (not shown), first, must specify the document type, coded information of the input 31 is supplied to the information input of the register 1, and its number, code information input 32 is supplied to the information inputs of the register 3. Then, the user presses “Search” and the clock input of the mouth of Oset a code document type, and secondly, is fed to the clock input 64 of the selector address 11 (Fig.2).

The decoder 55 address selector 11 decrypts the code document type and a high potential on one of its outputs opens one of the items 56-58 And (assume that this will be the element 56). Simultaneously, the clock pulse from the output element 61 delays the detainee at the time of entering code in the register and its decoding by the decoder 55, passes through the outdoor element 56 And, firstly, to the input of the read fixed cell constant memory (ROM) that stores the address area of memory that stores the selected document type, such as patents. Address code memory areas are read from the ROM 59 and through the outlet 65 is supplied to the information inputs of the register 2.

Secondly, the pulse from the output element 56 And through the element 60 and passes to the input of the delay element 62, where it is delayed by a time code read from the ROM 59 to the information inputs of the register 2, and then enters the clock input of the register 2, bringing in a code address memory areas of the documents of the selected type.

In parallel with the described process ID number of the document type selected is supplied to the information inputs of the register 3 and is filled in ' 67 and 68 of the block 10. In other words, triggers, 67 and 68 must be in its original condition. This state corresponds to the situation when the user has already been known patent number, case number or the application number, the contents of which he needs to work.

In this situation, the clock pulse from the output 66 of the selector address 11 passes through the element 16 And the clock input of the register 3 and enters a code number of the selected document type.

The decoder 55 address selector 12 decodes the code of the document type, and a high potential on one of its outputs opens one of the elements And (assume that this will be an item 57). Simultaneously, the clock pulse from the output element 61 delays the detainee at the time of entering the code in the register 3 and the decryption decoder 55, passes through the outdoor element 57 And, firstly, to the input of the read fixed cell constant memory (ROM) that stores the address of the document with the given number. Address code of the document with the given ID is read from the ROM 59 and through the outlet 65 is supplied to the information inputs of the register 4.

Secondly, the pulse from the output of the element 57 And through the element 60 and passes to the input of the delay element 62, where serouse the input of the register 4, bringing in his address code of the document with the given ID.

Address code of the document with the given ID from the output of the register 4 through the elements 19 And the first group and the elements OR group 22 is supplied to the information inputs of the register 5. The elements 19 And the second input open high potential with inverted output trigger 67, coming from the output 44 of the block 10. In parallel, the clock pulse from the output 66 of the selector 12, delayed by the delay element 23 on the time code reading and recording in the register 4, is held on the third input elements 19 And rewrites the code of the address number of the document to the information inputs of the register 5. This same pulse through the element 15 OR arrives at the clock input of the register 5, providing a code entry in the register 5, and simultaneously outputted through the output 43 to the interrupt input of the processor (not shown), which on this signal reads the address of the document of the selected type with the specified number of outputs 41 and 42 of the second and fifth registers, respectively, and samples of this document from the information database and issuing it to the user's workplace.

If the user has no exact number of the patent, which he needs, the latter can change the nab, the national classification of inventions. For this user on the remote control (not shown) is gaining class code of the patent according to the international classification of inventions, which input 33 is supplied to the information inputs of the register 6, and presses the “set class of the invention, the output of which is fed to the input 35 of the device and further to a single input trigger 67 unit 10, which, moving in one state, removes the enabling potential from the output 44 of the block 10, thereby blocking the passage of the clock pulse through the element 16 And the elements 19 And the first group. In addition, this same pulse through the element 74 OR arrives at the installation log trigger 68 unit 10, confirming its original state.

High potential with a single trigger output 67 from the output 46 of the unit 10 opens one input element 17 And the elements 20 And the second group. Given that the second input element 17 And is supplied with a high potential with inverted output 45 of the trigger 68 unit 10, then pressing “Search” clock pulse input 30 is held at the output 66 of the address selector 11 in the manner described above and then through the element 17 And is supplied to the clock input of the register 6 and enters a code classification of the invention.

Deshadow opens one of the elements And (for example, it will be the element 58). Simultaneously, the clock pulse from the output element 61 delays the detainee at the time of entering code in the register 6 and the decryption decoder 55, passes through the outdoor element 58 And, firstly, to the input of the read fixed cell constant memory (ROM), which stores the starting address of the descriptions of the inventions of this class. Code start address of the inventions of this class is read from the ROM 59 and through the outlet 65 is supplied to the information inputs of the reversible counter 8.

Secondly, the pulse from the output of the element 58 And through the element 60 and passes to the input of the delay element 62, where it is delayed by a time code read from the ROM 59 to the information inputs of the reversible counter 8, and then supplied to the clock input of the reversible counter 8, putting him in the class code of the invention.

Class code of the invention with the output of the reversible counter 8 through the elements 20 And the elements OR group 22 is supplied to the information inputs of the register 5. The elements 20 And the second input open high potential with direct access trigger 67, coming from the output 46 of the block 10. In parallel, the clock pulse from the output 66 of the selector 13, the detainee elem on the third input element 20 And rewrites the code class of the invention for informational inputs of the register 5. This same pulse through the element 15 OR arrives at the clock input of the register 5, providing a code entry in the register 5, and simultaneously outputted through the output 43 to the interrupt input of the processor (not shown), which on this signal reads the codes from the outputs 41 and 42 of the second and fifth registers, respectively, and performs the selection of the first description of this class of information database and issuing it to the user's workplace.

To view the descriptions of the inventions of this class, the user performs by pressing “>” (not shown), the output of which is fed to the input 37 of the block 10, and then passes through the open high potential with direct access to the trigger element 67 69 at exit 48 of the block 10, where applied to a summing input of reversible counter 8, which is formed by the address of the next invention of this class.

In parallel, the same pulse, after passing through the element 26 OR delayed by the delay element 24 during actuation of the reversible counter 8 passes to the third input element 20 And rewrites the code class of the invention for informational inputs of the register 5. This same pulse through the element 15 OR goes to sync the interrupt processor (not shown), who on this signal reads the codes from the outputs 41 and 42 of the second and fifth registers, respectively, and samples next to the description of this class of information database and issuing it to the user's workplace.

If necessary, reverse the descriptions of the inventions of this class the user presses "<", the output of which is fed to the input 38 of the block 10, and then passes through the open high potential trigger 67 element 71 And the output 49 of the block 10, where applied to the subtractive input of the reversible counter 8, reducing his testimony on the unit and setting the new value of the address. In addition, this same pulse through the element 26 OR delayed by the delay element 24 during actuation of the reversible counter 8 passes to the third input element 20 And rewrites the code class of the invention for informational inputs of the register 5. This same pulse through the element 15 OR arrives at the clock input of the register 5, providing a code entry in the register 5, and simultaneously outputted through the output 43 to the interrupt input of the processor (not shown), which on this signal reads the codes from the outputs 41 and 42 of the second and fifth registers, respectively, and assests the forth place of the user.

If the user selects this type of document, as a matter of maintaining records on the application, there is additionally the direction of the search by the date the case.

For this user on the remote control (not shown) dials a date code, which is input 34 is supplied for informational inputs register 7, and presses the “date”, the output of which is fed to the input 36 of the device and further to a single input trigger 68 unit 10, which, moving in one state, removes the enabling potential from the output 45 of the block 10, thereby blocking the passage of the clock pulse through the elements 16 and 17 I. in Addition, this same pulse through the element 73 OR passes on the installation log trigger 67 and establishes or confirms its original state.

High potential with a single trigger output 68 from the output 47 of the unit 10 opens one input element 18 And the elements 21 And the second group. Given that the second input element 18 And fed a high potential with inverted output 44 of the trigger 67 unit 10, then pressing “Search” clock pulse input 30 is held at the output 66 of the address selector 11 in the manner described above and then through the element 18 And arrives at the synchronization is d date and high potential on one of its outputs opens one of the elements And (for example, it will be the element 56). Simultaneously, the clock pulse from the output element 61 delays the detainee at the time of entering code in the register 7 and the decryption decoder 55, passes through the outdoor element 56 And, firstly, to the input of the read fixed cell constant memory (ROM), which stores the starting address of Affairs on the selected date. Code start address cases this date is read from the ROM 59 and through the outlet 65 is supplied to the information inputs of the reversible counter 9.

Secondly, the pulse from the output element 56 And through the element 60 and passes to the input of the delay element 62, where it is delayed by a time code read from the ROM 59 to the information inputs of the reversible counter 9, and then supplied to the clock input of the reversible counter 9, bringing in his address code.

Address code from the output of the reversible counter 9 through the elements 21 And the elements OR group 22 is supplied to the information inputs of the register 5. The elements 21 And the second input open high potential with direct access trigger 68 coming from the output 47 of the block 10. In parallel, the clock pulse from the output 66 of the selector 14, delayed by the delay element 25, the read time code and senesence for informational inputs of the register 5.

This same pulse through the element 15 OR arrives at the clock input of the register 5, providing a code entry in the register 5, and simultaneously outputted through the output 43 to the interrupt input of the processor (not shown), which on this signal reads the codes from the outputs 41 and 42 of the second and fifth registers, respectively, and performs sampling of the first case from the information database and issuing it to the user's workplace.

Sequential scan of cases with a given date, the user performs by pressing “>” (not shown), the output of which is fed to the input 37 of the block 10, and then passes through the open high potential with direct access to the trigger element 68 70 at exit 50 of the block 10, where applied to a summing input of reversible counter 9, forming the address of the next case.

In parallel, the same pulse, after passing through element 27 OR delayed by the delay element 25 at the time of actuation of the reversible counter 9, is held on the third input elements 21 And overwrites the address code to the information inputs of the register 5. This same pulse through the element 15 OR arrives at the clock input of the register 5, providing a code entry in the register 5, and at the same time vicodi with outputs 41 and 42 of the second and fifth registers, respectively, and samples another case from the information database and issuing it to the user's workplace.

If necessary, reverse the descriptions of the inventions of this class the user presses "<", the output of which is fed to the input 38 of the block 10, and then passes through the open high potential trigger element 68 and 72 And to the output 51 of the block 10, where applied to the subtractive input of the reversible counter 9, reducing his testimony on the unit and setting the new value of the address. In addition, this same pulse through the element 27 OR delayed by the delay element 25 at the time of actuation of the reversible counter 9, is held on the third input elements 21 And overwrites the address code to the information inputs of the register 5. This same pulse through the element 15 OR arrives at the clock input of the register 5, providing a code entry in the register 5, and simultaneously outputted through the output 43 to the interrupt input of the processor (not shown), which on this signal reads the codes from the outputs 41 and 42 of the second and fifth registers, respectively, and samples another case from the information database and issuing it to the user's workplace.

Thus, the introduction of new units and new constructive relationships will significantly improve the performance of the device, excluding the belt.

Sources of information

1. The EPO patent (EP) No. 0505651, M CL G 06 F 13/40, 13/38, 1992.

2. U.S. patent No. 5161214, CL G 06 F 3/14, 1992 (prototype).

Claims

Device to control the retrieval of text documents containing the first register, the information inputs which are the first information input of the clock input is the clock input of the device, and the outputs are connected to information inputs of the first selector addresses, the clock input of which is the clock input devices, and information outputs connected to information inputs of the second register, a clock input connected to the clock output of the first selector address, and the outputs of the second register are the first information output device, the third register, the information inputs which are second information input device, the clock input is connected to the output of the first element And and outputs connected to information inputs of the second selector addresses, the clock input of which is connected to the output of the first element And the fourth register, the information input of which is connected to data outputs the resa, and outputs connected to the first input of the respective elements And the first group, the second input of which is connected to the output of the first delay element, the input of which is connected to the synchronizing output of the second selector address, the fifth register, the information input of which is connected to the inputs of the respective elements OR groups, the clock input coupled to the output element OR the input of which is connected to the outputs of the first, second and third delay elements, and the output element OR is the clock output devices, elements, And the second and third groups whose outputs are connected to inputs of the respective elements OR groups, the second and third elements, And characterized in that it contains the block select the search direction, the first, second, third and fourth control inputs of which are the first, second, third and fourth control inputs of the device respectively, the first control unit output is connected to one input elements And the first group and with the same inputs of the first and third elements And other inputs which are connected to the synchronizing output of the first selector address, the second control unit output is connected to the third input of the first element And to the od of the dres, the third control output unit connected to the third input of the second element And with the same inputs of elements And the second group, the other inputs of which are connected to the output of the second delay element, the fourth control output unit connected to the third input of the third element And one input elements And the third group, the other input of which is connected to the output of the third delay element, the sixth register, the information input which is the third information input device, and a clock input connected to the output of the second element And the first reversible counter, summarizing and subtractive inputs of which are connected with the fifth and sixth control outputs block selection of the search direction, and outputs connected to other inputs of elements And the second group, the third selector address, data inputs which are connected to the outputs of the sixth register, the clock input connected to the output of the second element And information outputs the third address selector connected to information inputs of the first reversible counter, and a clock output connected to the clock input of the first reversible counter, the seventh case, the information input which is the fourth Arseny counter, summarizing and subtractive inputs of which are connected with the seventh and eighth control outputs block selection of the search direction, and outputs connected to other inputs of elements And the third group, the fourth selector address, data inputs which are connected to the outputs of the seventh register, a clock input connected to the output of the third element And information outputs of the fourth selector addresses connected to information inputs of the second reversible counter, and a clock output connected to the clock input of the second reversible counter, the second element OR the input of which is connected to the fifth and sixth control outputs block selection of the search direction and the clock output of the third selector address, and the output is connected to the input of the second delay element and the third element, OR, the inputs of which are connected with the seventh and eighth control outputs block selection of the search direction and the clock output of the fourth selector address, and the output connected to the input of the third delay element.



 

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