Device for synchronization cycles

 

The invention relates to telecommunication and can be used in the receiving device sync cycles of transmission of discrete messages. The device includes a detector clock, the main output of which is connected to the first input of the adder, an output connected to the signal input of the shift registers, the main output of which is connected to the second input of the adder, and an additional output to the signal input of the decision making node , the output of which is connected to the reset inputs of the unit shift registers of the imaging unit cyclic pulses, the clock input of the detector clock United clock inputs of the decision making node, block shift registers, counter distorted singlesymbol, shaper cyclic pulses, the counter element And the control input of the decision making node coupled to the output of the block selection threshold, the output of the counter is connected to the reset input of trigger , the input set which is connected to the output of the shaper cyclic pulses, the output of which is connected to the control input of the counter distorted singlesymbol, the trigger output is connected to the reset input of the counter and the second input element And the output of which is connected to the clock input of the counter, the output of the larger connecting apertures the dew counter distorted singlesymbol, the data input of which is connected to the secondary output of the Recognizer clock, the output of the counter distorted singlesymbol connected to the address inputs of the block selection threshold and the block selection maximum weight response, the output of which is connected to the control input of the detector clock. When this signal input to the detector of the clock, the clock input of the shaper cyclic pulses and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output devices, entered the counter distorted singlesymbol, counters, item, trigger and block selection maximum weight response, and the detector clock is made in the form of a shift register, detector errors synchrogram and shaper weight response to the synchronization signal, the output of which is formed the weights depending on the number of errors in the received synchrogram. The technical result achieved by the invention is to increase the noise immunity and performance. 4 Il.

The invention relates to telecommunication and can be used in receivers for the cycles on and.with. The USSR 436393 class G 11 19/00, publ. 15.07.74, bull. No. 46, containing, as the proposed device, the detector of the clock, the unit shift registers, an adder, a crucial node, and the main output of the detector clock connected to the first input of the adder, the output of which is connected to the signal input of the shift registers, the main output of which is connected to the second input of the adder. In addition, in the known device, the main output of the unit shift registers is connected to a second input of the adder and the signal input recause site. This adder is made in the form of n-bit reversible counter which performs a counting function response of the detector clock on each of the pulse positions of cycles of the observation interval, and n shift registers of unit shift registers perform the saving of the results account for the duration of the cycle. In clock intervals defined by clock pulses from a clock pulse is cheating values of bits of the n-bit counter in the first cell of the corresponding shift registers and write to the same counter values of the last cells of the shift registers. If the heartbeat interval is the response of the detector clock the Lu response, accumulated previously in this position the loop is incremented. If the position loop is no response of the detector, the number recorded in parallel binary code into an n-bit counter with the last cell of register is decreased by one. After a cycle in cells of registers in a parallel binary code are recorded the results of the response of the detector for all N pulse positions. Based on the analysis of these results, a crucial node determines the position number, which corresponds to the largest binary number of responses of the detector clock, and thus decides the position of synchronism. The output of the decision making node is an output device.

A disadvantage of the known device is the low immunity, defined high probability of false positives (false detection of synchronism). When the distortion of at least one sync pulse at the output of the Recognizer clock, there is no response. The value of the binary number corresponding to the number of responses accumulated previously in the position loop is decreased by one, i.e., there is loss of the accumulated synchroinformation. At other positions of the cycle may be the possible false synchronism. In addition, when the correction of the detector clock distorted singlesymbol dramatically increases the probability of detection by the detector of false singlegroup (see Koltunov M. N., Konovalov, C., leaf monkeys H. I. Synchronization cycles in digital communication systems. - M.: Communication, 1980. - S. 134), which also increases the detection probability of false matching.

A device for the synchronization cycle.with. The USSR 1596475 class H 04 L 7/08, publ. 30.09.90, bull. No. 36, containing, as the proposed device, the shift register, the detector errors synchrogram and shaper of such pulses, and the input detector error synchrogram connected to the output of the shift register and the clock input of the shift register is connected to the clock input of the shaper cyclic pulses, the data input, the clock input of the shift register and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output devices. In addition, the known device also contains K-1 detectors errors in singlegroup (where K is the number of controlled cyclic intervals), the adder and the comparator. Moreover, the inputs To the detectors errors in synchrogram connected to tify the detectors errors in synchrogram made in the form shapers signal weighting coefficients, determining the amount of distortion singlegroup. The signals from the outputs of the detectors errors in synchrogram go through the adder in a comparator that compares the value of the output signal of the adder with the value of the threshold code. When exceeding the value of the comparator generates a signal that carries out phase shaper cycle pulses.

However, a disadvantage of the known device is the low immunity caused by fixed interval of observation, that with a high probability of erroneous reception of the pulses reduces the probability of detecting a true matching.

Closest to the present invention is a device for synchronizing the cycles of as.with. The USSR 1172052 class H 04 L 7/08, publ. 07.08.85, bull. No. 29, prototype, containing, as the proposed device, the detector of the synchronization signal, the adder, the unit shift registers, a crucial node, the driver of such pulses and the block selection threshold. Moreover, the main output of the detector clock connected to the first input of the adder, the output of which is connected to the signal input of the shift registers. The main output of the unit shift registers connected to the second input of the adder, and on the comparison, memory block, block subtraction, the second unit of comparison and counter comparison. Thus the output of the first unit of comparison is connected to the control input of the memory block, the output of which is connected to the second input of the first unit of comparison and the first input of the subtraction unit. The second input of the subtraction unit is combined with data input of the memory block, the first input of the first unit of comparison is the signal input of the decision making node. The output of the subtraction unit is connected to the second input of the second unit of comparison. The output of the second unit of comparison is connected to the reset input of the counter comparison. The output of the counter comparison is connected to the reset input of the memory block. While managing and clock inputs of the decision making node are, respectively, the first input of the second block comparison and the clock input of the counter comparison. The output of the decision making node is the output of the meter comparison, which is connected to the reset inputs of the former (cyclic pulses and block shift registers. The clock input of the unit shift registers combined with a clock input of the Recognizer clock, a casting site and shaper of such pulses, and the control input of the decision making node coupled to the output of the block selection threshold. When this signal input, a clock input OPOS, the Assembly input and output devices. In addition, the known device also contains an element of the ban, the counter distorted signals and the loop counter. The second input element of the ban is connected to the output of the detector clock. The output of shaper cyclic pulses connected to the first input element of the ban and the entrance to the loop counter. The output of the loop counter is connected to the control input of the block selection threshold and the control input of the counter distorted signals. The output element of the ban is connected to the counting input of the counter distorted signals, the output of which is connected to the address input of the block selection threshold.

The disadvantage of the prototype is a low noise immunity and performance, due to the fact that in the search mode of synchronism signal, adopted by the error, not allocated by the Recognizer clock that prevents the accumulation of signals in the shift registers. In addition, when performing correction on the output of the detector clock regardless of the number of correctly received pulses generated response in the form of a single pulse. This increases the number of false singlegroup recognized by the Recognizer clock as distorted synchro distorted the true singlegroup or false, recognized by the Recognizer as misrepresented the true singlegroup. This leads not only to increased recovery time simultaneity, i.e., to increase the time on the accumulation of synchroinformation, but also to increase the detection probability of false matching.

Transmission feature of deterministic sequential clock is the frequency of its repetition on the same positions of the transmission cycle of the group signal. This Recognizer clock can recognize in the received multicast signal is not only true singlegroup, but false, randomly generated information on the positions of the cycle. When forming the output of the Recognizer trigger responses in the form of units (recognized singlegroup) and zeros (the unrecognized singlegroup) the required accuracy of decision-making decisive node is achieved through the accumulation of responses in the unit shift registers. This leads to low noise immunity of the device to synchronize the cycles, because when taking singlegroup with errors at the output of the detector clock is formed by a "zero" response, and the accumulation of synchroinformation in cells of the unit shift registers are not implemented. Recognition of opoznavatelnie shift registers, the corresponding false synchrogram, increasing the likelihood of false detection of synchronism. The formation of the output of the Recognizer trigger responses in the form of weights leads at a fixed observation interval and a high probability of erroneous reception of the clock to reduce the probability of true detection of synchronism. In addition, the formation of the threshold numbers for the block selection threshold based on the measured probability of erroneous reception of singlegroup provides low accuracy of the choice of threshold numbers, since the evaluation of the quality of a received digital signal based on the probability of erroneous reception of singlegroup gives a rough estimate of the degree of distortion of the received signal. With a high probability of detection false synchronism possible false alarm device to synchronize the cycles, which, in turn, leads to the need for further search of synchronism, i.e., to increase the time of a cyclical recovery of synchronism. These factors make high demands on performance and noise immunity of the device to synchronize the cycles.

Device for synchronizing the cycles contains Recognizer clock, osnovnoi the output of the detector clock connected to the first input of the adder, the output of which is connected to the signal input of the shift registers. The main output of the unit shift registers connected to the second input of the adder, and an additional output unit shift registers to the signal input of the decision making node. At this crucial node consists of the first block compare block of memory, the subtraction unit, the second unit of comparison and counter comparison. The output of the first unit of comparison is connected to the control input of the memory block, the output of which is connected to the second input of the first unit of comparison and the first input of the subtraction unit. The second input of the subtraction unit is combined with data input of the memory block, the first input of the first unit of comparison is the signal input of the decision making node. The output of the subtraction unit is connected to the second input of the second unit of comparison. The output of the second unit of comparison is connected to the reset input of the counter comparison. The output of the counter comparison is connected to the reset input of the memory block. While managing and clock inputs of the decision making node are, respectively, the first input of the second block comparison and the clock input of the counter comparison. The output of the decision making node is the output of the meter comparison, which is connected to the reset inputs of the former (cyclic pulses and the block region is sausage site and shaper cyclic pulses, and control input recause node coupled to the output of the block selection threshold. When this signal input, a clock input of the detector clock and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output devices.

The technical result in the implementation of the invention is the increased robustness and performance of the device to synchronize the cycles is achieved by the introduction of counter distorted singlesymbol, block selection maximum weight response, the first and second counter, the trigger element I. in Addition, the detector clock contains a shift register, the detector errors synchrogram and shaper weight response to the synchronization signal. Thus the output of the shift register is connected to the input of detector errors synchrogram. The first output of detector errors synchrogram connected to the first input of the shaper weight response to the synchronization signal, the second output is connected to the third input of the shaper weight response to the synchronization signal and the data input of the counter distorted singlesymbol. Thus the output of the shaper weight response to the synchronization signal connected to the first input of the adder and is the primary output of the Recognizer synchrogram. The signal and control inputs of the detector clock are respectively the serial data input of the shift register and the second input of the shaper weight response to the synchronization signal. A clock input of the detector clock is the clock inputs of the shift register and driver weight response to the synchronization signal, which is also combined with the first input element And a clock input of the first counter and the counter distorted singlesymbol. The output of the first counter is connected to the reset input of trigger. The input set trigger in the "single" status is connected to the output of the shaper cyclic pulses, which are output to synchronize the cycles. In addition, the output of the shaper cyclic pulses connected to the control input of the counter distorted singlesymbol. The trigger output is connected to the reset input of the first counter and the second input element And an output connected to a clock input of the second counter. The output of the second counter connected to the control inputs of the block selection threshold and the block selection maximum weight of response, and also to the reset input of the counter distorted singlesymbol. The output of the counter distorted singlesymbol connected to the address inputs of the block selection is El clock.

With the introduction in the detector of the sync detector errors synchrogram and shaper weight response to the synchronization signal at the output of the detector clock generated weighting coefficients whose values are determined depending on the number of errors in the received synchrogram. When overweight response to the synchronization signal value u is generated weighting factor greater than zero. This synchroinformation accumulates in the appropriate cells of the unit shift registers, increasing the value generated at the output of the detector clock weighting factor. This reduces the risk of false positives compared to the prototype that generates a response in the form of a binary signal regardless of the number of detected erroneously accepted singlesymbol. In addition, improving the noise immunity of the device to synchronize the cycles is achieved by the introduction of counter distorted singlesymbol, the first and second counter element And trigger and block selection maximum weight response. Counter distorted singlesymbol, item, trigger, the first and the second counter are used to measure the probability (relative) erroneous admission snih of singlesymbol provides a count of the number of distorted singlesymbol, as an element And trigger the first and second counter - the number of transmitted singlesymbol. This is compared with the prototype provides a more accurate estimate of the degree of distortion of the received signal. In addition, the achieved reduction in the average recovery time simultaneity in comparison with the prototype, because the time interval of observation of the response of the detector clock at the end of which the decision on the phase of the clock cycle, adaptive changes, approaching the minimum possible, which will ensure the required immunity.

Conducted by the applicant's analysis of the prior art, including searching by the patent and scientific and technical information sources, and identify sources that contain information about the equivalents of the claimed invention, has allowed to establish that the applicant had not discovered similar, characterized by signs, identical with all the essential features of the claimed invention. Select from a list of identified unique prototype, as the most similar in essential features analogue, has identified a set of essential towards perceived by the applicant to the technical result of the distinctive features in the Declaration is riteria "novelty".

To check the compliance of the claimed invention, the criterion of "inventive step", the applicant conducted an additional search of the known solutions to identify signs that match the distinctive features of the prototype of the characteristics of the claimed device. The search results showed that the claimed invention not apparent to the expert in the obvious way from the prior art, as defined by the applicant. Not identified the impact of changes under the essential features of the claimed invention, to achieve a technical result. In particular, the claimed invention does not provide the following transformations: addition of known means of any known part attached to it according to certain rules, to achieve a technical result, in respect of which it is the effect of such additions; the replacement of any part of the other known means known part to achieve a technical result, in respect of which it is the effect of such a change; the exclusion of any part of the funds while the exclusion of its functions and the achievement of a result of such exclusion; uwano of such elements; the execution of a known drug or part of a known material to achieve a technical result due to the known properties of the material; the creation of tools, consisting of well-known parts, the choice of which and the relationship between them is carried out on the basis of known rules, recommendations, and achievable technical result is due only to the known properties of the parts of this object and the relationships between them; change quantitative attributes or relations of signs, if known fact of the influence of each on the technical result and the new values of the signs or their relationship could be obtained from the known dependencies. Therefore, the claimed invention meets the criterion of "inventive step".

The invention is illustrated graphics, which depict: Fig.1 is a structural diagram of a device for synchronizing the cycles of Fig.2 is a block diagram of the error detector in synchrogram, Fig.3 is a functional diagram of the shaper weight response to the synchronization signal of Fig.4 is a functional diagram of the counter distorted singlesymbol.

Information confirming the possibility of carrying out the invention with getting vishey the inhabitants Recognizer 1 clock the adder 2, block 3 shift registers, a crucial node 4, the counter distorted singlesymbol 5, block 6 select the maximum weight response, block 7 of the choice of the threshold, the imaging unit 8 cyclic pulses, the trigger 9, the counter 10, item 11, a counter 12, the input signal 13, the input 14 of the clock, the output device 15. This Recognizer 1 clock register contains 16 shift detector 17 errors in synchrogram and shaper 18 weight response to the synchronization signal. A crucial node 4 contains a block 19 of the comparison, the memory block 20, block 21 subtraction unit 22 comparison, the counter 23 comparison. When this input signal 13 is connected to the signal input of the detector 1 clock. The signal input of the detector 1 clock information is the input of the register 16 of the shift, the output of which is connected to the input of the detector 17 errors in synchrogram. The clock input of the detector 1 clock connected to clock inputs of the register 16 of the shift and shaper 18 weight response to the synchronization signal. The first output of the detector 17 errors in synchrogram connected to the first input of the shaper 18 weight response to the synchronization signal. The second output of detector 17 errors in synchrogram connected to the data input of the counter 5 distorted singlesymbol and to the third input f is a high weight response. The output of the shaper 18 weight response to the synchronization signal connected to the first input of the adder 2, the output of which is connected to the signal input unit 3 shift registers. The main output unit 3 shift registers connected to the second input of the adder 2, and the additional output to the signal input of the decision making unit 4. When the output unit 19 comparison is connected to the control input of the memory block 20, the output of which is connected to the second input unit 19 comparison and the first input unit 21 subtraction. The second input unit 21 subtraction combined with the data input of the memory block 20, the first input unit 19 comparison and is the signal input of the decision making unit 4. The output of the subtraction unit 21 is connected to the second input unit 22 of the comparison, the output of which is connected to the reset input of the counter 23 comparison. The output of the counter 23 comparison is connected to the reset input of the memory block 20. While managing and clock inputs of the decision making node 4 are, respectively, the first input unit 22 comparison and the clock input of the counter 23 comparison. The output of the decision making node 4 is the output of the counter 23 of the comparison, which is connected to the reset inputs of the former (8 cyclic pulses and block 3 shift registers. The clock input of the shaper 8 cyclic pulses combined with the first one is, counter 5 distorted singlesymbol and counter 10, and the control input of the decision making node 4 is connected to the output unit 7 of the choice of the threshold. The output of the counter 5 distorted singlesymbol connected to the address inputs of the block 6 select the maximum weight response and block 7 of the choice of the threshold. The output of shaper 8 cyclic pulses connected to the control input of the counter 5 distorted singlesymbol and the input set trigger 9, and the reset input of the trigger 9 is connected to the output of the first counter 10. The trigger output 9 is connected to the reset input of the counter 10 and the second input element 11 And whose output is connected to a clock input of the counter 12. The output of the counter 12 is connected to the reset input of the counter 5 distorted singlesymbol and the inputs of the control unit 6 selection of the maximum weight response and block 7 of the choice of the threshold. When this signal input of the detector 1 clock, the clock input of the shaper 8 cyclic pulses and the output of the shaper 8 cyclic pulses are respectively the signal input 13, a clock input 14 and the output 15 of the device.

Device sync cycles is as follows. At the signal input of the detector 1 clock group enters the digital signal containing deterministic mi group is the first group of information symbols, identical to singlegroup, are formed randomly. During each clock interval in the register 16 of the shift is written to one symbol of the received signal, and with the arrival of the next character previous moves to the next cell in the shift register. Thus, for m clock intervals (where m is the number of characters in singlegroup) in the register is written m character code combination. During each clock interval compares patterns of each of the received sequence of m symbols with the "copy" singlegroup recorded in the detector 17 errors in synchrogram, and the result of the comparison is converted into an s-bit binary number mOsh(where mOsh- the number of errors in singlegroup, s=[log2m]+1, where [] is the integer part of the number) input to the shaper 18 weight response to the synchronization signal.

In Fig.2 for example shows a functional diagram of the error detection in singlegroup having the structure 1101. The detector errors synchrogram consists of a decoder singlegroup (element DD1.1), encoder (elements DD2-DD5) and subtractive devices (elements DD6 and DD1.2-DD1.4). To the input of the decoder from the output of the register 16 of the shift to parallel code group served the signal. While the act left. The decoder is configured to detect singlegroup ID 1101. The encoder is designed to generate binary numbers accurately detected singlesymbol in singlegroup. Subtractive device performs the operation of subtracting from the number of characters in singlegroup m (in our case m=4). the number accurately detected singlesymbol in singlegroup. At the output of subtractive device, which is the output of the detector 17 errors in synchrogram, is formed by a binary number of erroneously received singlesymbol in singlegroup. The detector 17 errors in synchrogram can be implemented, for example, on the chip: DD1 - CLN: DD2 - CID: DD3 - CLA; DD4 - CLA; DD5 - CLE; DD6 - KIM.

Functional diagram of the shaper 18 weight response to the synchronization signal shown in Fig.3. Shaper 18 weight response to the synchronization signal consists of delay lines (elements DD1.1-DD1.2), storage devices (DD2) and comparing the device (DD3). In the shaper 18 weight response to the synchronization signal produced by the comparison operation maximum weight of response to the synchronization signal u with the detected number of errors in singlegroup mOsh. The value of u varies from 1 to m. Input voicee number accurately detected singlesymbol in singlegroup. Code corresponding to the value of u, is fed from the output of block 6 select the maximum weight of response depending on the magnitude of the probability of erroneous reception of characters singlegroup to the first input of the compare unit (DD3). Code corresponding to the value of mOshserved with the second output of the detector 17 errors in synchrogram on the second input of the comparing device. When the input detector 1 clock combination code singlegroup at the output of the shaper 18 weight response to the synchronization signal generated response w in the form of binary numbers. Thus the value of the response w changes depending on the number of errors in singlegroup mOsh:

where w is the weight of the response to the synchronization signal; and u is the maximum weight of a response to the synchronization signal: mOsh- the number of errors in singlegroup; mSS- the number of allowable errors in singlegroup. If u>mOshthen the output comparing device (pin 7 item DD3) is zero, the signal received at the reset input and the write-enable mass storage devices (DD2). With the advent of the positive front of the clock pulse, delayed by the delay line to the desired value, the number w of zapisyvaetsja (DD3) is formed of a single signal, installing a storage device in the zero state. The delay line (elements DD1.1, DD1.2) is used to correct account numbers w in the storage device. The delay line can be constructed, for example, the elements are NOT. When this delay time is calculated as the total time delay of signal propagation in the elements of the register 16 of the shift detector 17 errors in synchrogram and shaper 18 weight response to the synchronization signal and is determined by the number of items included (see, for example, Veniaminov C. N., Lebedev, O. N., Miroshnichenko, A. I. Chips and their application: Ref. the allowance. - M.: Radio and communication, 1989. - S. 207)

tLPA=qtZV.R. cf,

where q is an even number of elements NOT involved in the delay of the signal, tZV.R. cfthe time delay distribution in the element is NOT equal to half the sum of the delay time distribution of the signal when switching on and off of the integrated circuit (for example, for a chip CLN tZV.R. cf=20 NS) (see, for example, Avanesyan, R., Levshin VP of Integrated circuits TTL, TTLS: a Handbook. - M.: Mashinostroenie, 1993. - S. 76). Shaper 18 weight response to the synchronization signal may be implemented, for example, on the chip: DD1 - CLN; DD2 - CIR; DD3 - CSP. In ecstasy a parallel combinational adder, which s-bit input of the first term (low-order bits of the n bit input and n-bit inputs of the second term are respectively the first and the second input of the adder, while the other (n-s) bit inputs of the first summand is connected to the source of the "zero" level.

Unit 3 shift registers includes n-bit (n=[log2N· u]+1, N is the number of positions in one cycle) shift registers. United clock inputs and the United inputs reset shift registers are respectively a clock input and a reset input block 3 shift registers, and the signal inputs, the outputs of the last bits and outputs the first digits of all shift registers are respectively the signal input, main output and an additional output side 3 shift registers. Thus, the response of the detector 1 clock in the i-th clock interval, formed in the adder 2 with the previous account of the responses to the i-th position of the loop coming from the main output unit 3 shift registers. A new result of counting responses, more on w still written in the form n-bit binary number in the corresponding first cell (bits) shift registers unit 3 shift registers. When the, stored in subsequent similar cells, in parallel shifted by one digit, and the output unit 3 shift registers to the second input of the adder 2 is supplied the result of counting responses (i+1)-th clock interval. If the response of the detector clock (i+1)-th clock interval is not present, then the previous result account of the responses to (i+1)-th position of the cycle corresponds to the first cell block 3 shift registers, and other numbers that are stored in the same cell block 3 shift registers are shifted by one digit, and so on, Unit 3 shift registers provides storage of account results of the responses to each position of the loop within the loop duration. The value of n determines the memory capacity of account results. At the same time the account of the responses to each of the positions of the cycle with an additional output unit 3 shift registers sequentially arrive at the signal input of the decision making unit 4. In the final node 4, for example in the i-th clock interval, the input binary number in parallel code representing the current account responses to the i-th position of the cycle, is simultaneously supplied to the first input unit 19 comparison, the data input of the memory block 20 and the second input unit 21 subtraction. In block 19 comparison of the input then the output unit 19 comparison pulse is formed, which, by acting on the control input of the memory block 20 provides the Erasure of the old and the new record (input) number. After that, the input unit 19 comparison are equal to a binary number. If the input number is equal to or less than the number stored in the memory block 20, the content of the latter is not changed. Thus, in block 20 of the memory is overwritten by the most current the account of the responses to any of the position loop, which is then compared to the results of the account at the subsequent positions of the cycle. The resulting difference between the number of the memory block 20 and the input number) at the output of block 21 subtraction in the form of binary numbers in parallel code is compared in block 22 comparison with a threshold number d received at its first input (which is the controlling input of the decision making node 4) from the output of block 7 of the choice of the threshold. If the number from the output of block 21 of the subtraction is less than the threshold number d, the output of the second unit 22 comparison to the reset input of the counter 23 comparison is "single" (prohibiting) the potential that sets and keeps it in the "zero" state. When the i-th clock interval number from the output of block 21 of the subtraction is equal to or greater than the number d, the output of the second unit 22 comparison comes "Nona its clock input, which is the clock input of the decision making unit 4. If the largest binary number recorded in the memory block 20, will exceed each of the N-1 subsequent numbers coming one after another with an additional output unit 3 shift registers, an amount equal to or greater than the threshold number d, the counter 23 comparison will produce the following N consecutive clock pulses. Then it outputs a pulse signal, which is output by the synchronization signal of the decision making unit 4. The synchronization signal is supplied to the reset inputs of the memory block 20, block 3 shift registers of the imaging unit 8 cyclic pulses. As a result, the memory block 20 and block 3 shift registers is reset to "zero", then the output of block 22 comparison begins to act prohibiting "single" potential, and the counter 23 comparison is also reset to "zero". The output signal synchronized final node 4 is the phase shaper 8 cyclic pulses so that the output device 15 start coming regularly following cycle pulses, a time coinciding with the response of the detector 1 clock on the true singlegroup. The process of finding a temporary position of a cyclical clock in dogdom to confirm the initial setup phase shaper 8 cyclic pulses, if the temporary position of a cyclical clock does not change. Blocks 19 and 22 comparison can be performed, for example, in the form of n-bit binary Comparators forming the sign "more", "less" with the appropriate sign of the difference values of the input operands, and a sign of their equality supplied to first and second inputs of the blocks. Thus the outputs of the first and second block are output P>Q comparator (Fig.3, the element DD3). The memory block 20 may be made in the form of n-bit register with parallel input. When this data inputs, a control input, a reset input and an output of the memory block 20 are respectively a data input, a clock input, a reset input and output data n-bit register. The block 21 subtraction can be performed in a full n-bit parallel adder. The bit width of the adder is provided a serial output connection of the transfer of the adder least significant bits with a carry-in input of adder senior ranks. To perform a full adder operation of subtracting a number from the memory block 20, arriving at the first input of the subtraction unit, subject inversion, and the number coming from the additional output unit 3 shift registers to the second input of the subtraction unit, inv is t to be made in the form of serially connected binary-synchronous decimal counter and decoder. When the reset inputs of the counter 23 comparison and shaper 8 cyclic pulses are input reset BCD counter. Accordingly, the clock inputs of the counter 23 comparison and shaper 8 cyclic pulses are clock inputs of the BCD counter. The outputs of the counter 23 comparison and shaper 8 cyclic pulse is the output of the decoder, determining a condition of BCD counters. During this phase shaper 8 cyclic pulses can be performed by setting in "bullets" counter.

The process of forming the threshold numbers d for the final node 4 and a maximum weight of response to the synchronization signal and detector clock 1 as follows. The s-bit data input of the counter 5 distorted singlesymbol receives a binary number mOshequal to the number of errors in singlegroup. Counter 5 distorted singlesymbol calculates the total number of errors in synchrogram R, and the counter 12, the total number of singlesymbol transmitted for a certain period of time Q. the frame synchronization Signal from the output of the shaper 8 cyclic pulse sets the trigger 9 in the "single" status, and "single" signal (signal razresheniya mode "accounts", and permitted the passage of clock pulses from the output element 11 And the clock input of the counter 12. The counter 10 provides a passage through the element 11 And one cycle of a certain number of clock pulses equal to the number of pulses in singlegroup m, then resets the trigger 9 to "zero". The counter 10 by a signal of logical "zero" output of the trigger 9 is reset to "zero" and is translated in the mode "stop". Counting the number of R distorted singlesymbol during the time the account is quite a large number of such singlesymbol Q, it is possible periodically to determine the probability (castest) erroneous admission of singlesymbol by the formula pOsh=R/Q, i.e., to produce a current assessment of the degree of distortion of the received digital signal. The counters 10 and 12 can be performed as a shaper 8 cyclic pulses, in the form of serially connected binary-synchronous decimal counter and decoder. Reset both counters - synchronous. Thus the decoder counter 10 is configured to identify the state of the binary-decimal counter equal to the number of pulses in singlegroup m, and the decoder counter 12 is configured to identify the state of the binary-decimal counter equal to the number of Kirovets 8 cyclic pulses, and the input R to the output of the counter 10. The capacity of the counter 12 is equal to the value of Q, so after counting each Q clock pulses at its outputs a single pulse, which in block 7 of the choice of the threshold in block 6 of selecting the maximum weight of the response, instead kept them in binary numbers, rewritten content of the counter 5 distorted singlesymbol. After that, the counter 5 distorted singlesymbol is reset to "zero", and the process of analyzing the quality of the received signal during the subsequent follow Q clock repeats.

In Fig.4, for example, presents a functional diagram of the counter 5 distorted singlesymbol intended to count wrongly accepted singlesymbol when m=4. Counter 5 distorted singlesymbol consists of adding devices (elements DD1 and DD3) and storage devices (DD2) and delay lines. When the input data counter 5 distorted singlesymbol served number of erroneously received singlesymbol mOshfrom the second output of the detector 17 errors in synchrogram. This number is summed with the number of bugs in synchrogram accumulated during the previous period. To the control input of the counter 5 distorted singlesymbol will SHS to the inputs of the control mode of the storage device (DD2). providing a saving of the results of the summation of the errors in synchrogram. Therefore, the counter 5 distorted singlesymbol provides counting only mistakenly accepted singlesymbol. the corresponding true synchrogram, in the moments of arrival of the positive front of the clock pulse through the first delay line to the clock input of the storage device (DD2). The reset signal is supplied from the output of the counter 12 to the clock input of the counter 5 distorted singlesymbol through a third delay line to the reset input of the storage device (DD2). Delay lines are: first line delay for the correct recording of the summation in the storage device; a second delay line for recording in the storage device only mistakenly accepted singlesymbol corresponding true synchrogram; a third delay line for the timely discharge of the storage device. The delay time of the first and second delay lines is defined as the total time delay of signal propagation in the elements of the register 16 of the shift detector 17 errors in synchrogram and counter 5 distorted singlesymbol (items adder). The delay time of the third delay line is defined as the 7 choice of threshold). Counter 5 distorted singlesymbol can be implemented, for example, on the chip: DD1, DD3 - KIM; DD2 - CIR. Delay lines can be implemented, for example, as the delay line driver 18 weight response to the synchronization signal on items NOT chip KLN.

Unit 6 selection of the maximum weight response and block 7 of the choice of the threshold depending on the values written to them in the binary number R make the selection, respectively, a certain number of maximum weight response to the synchronization signal u, and the threshold number d. The selected number of u and d outputs of blocks 6 and 7 in parallel code served, respectively, to the second input of the shaper 18 weight response to the synchronization signal and the control input of the decision making unit 4. Unit 6 selection of the maximum weight response and block 7 of the choice of the threshold can be made in the form of permanent storage devices (for example, on the chip CRF), memory elements which are recorded the results of calculations of the numbers of valid error values in synchrogram and threshold numbers depending on the probability of erroneous reception of a single character of the input group of the digital signal (see Kalinnikov centuries, tashlinskii A., methods of finding internal system parameters cyclic singl. SNR, ser. B, vol.61, 2002). The value of the measured probability of erroneous reception of a single character from the output of the counter 5 distorted singlesymbol served on a storage device that can be made in the form of register with parallel input and a parallel output connected to the address inputs of persistent storage devices. Maximum weight of response to the synchronization signal and / or a threshold number d is carried out when entering the control inputs reading of permanent storage devicesthe output signal of the counter 12 is finished measuring the probability of erroneous reception of singlesymbol POsh. Thus, during the time of account Q at a crucial node 4 is fed a certain threshold d, and the shaper 18 weight response to the synchronization signal is the maximum weight of a response to the synchronization signal u, which can take in each case one of the h discrete values (gradation) depending on signal quality. The required number of gradations h threshold number d and a maximum weight of response to the synchronization signal u is determined on the basis of maintaining the probability of false detection of the synchronization signal within the required limits when the difference is ub> unit 7 the choice of the threshold and the maximum weight of response urunit 6 selection of the maximum weight of the response can be written in the form

dr=F1(ArPOsh<Br),

ur=F2(ArPOsh<Br),

where F1and F2- pre-selected rules, respectively, for unit 7 of the choice of the threshold and the block 6 select the maximum weight of response, for which the value of POsh=R/Q, takes the value within the r-th interval (g varies from 1 to h) dimensions, given in compliance with the threshold values of the number d, and the maximum weight of response to the synchronization signal ur;rand Brrespectively the lower and upper bound values of ROshfor the r-th interval. The required noise immunity of the device, which is determined by the probability of false detection of the synchronization signal, is ensured by the choice of the laws of formation threshold numbers drfor block 7 of the choice of the threshold and numbers maximum weight of response to the synchronization signal urfor unit 6 selection of the maximum weight of a response corresponding to the measured values of ROshwithin any r-g the th threshold number of drand the maximum weight of a response to the synchronization signal ur. At the same time achieved by reducing recovery time simultaneity, since the time interval of observation of the response of the detector 1 clock, at the end of which the decision on the phase of the clock cycle, adaptive changes depending on the magnitude of ROshand in each specific case (at a certain value of POshis approaching the minimum required, which will ensure the required immunity. The Q-value, which determines the ratio of the account of the counter 12 should be chosen, on the one hand, large enough to provide the desired precision of the estimate of the error probability POsha single character, on the other hand is sufficiently low to ensure that the measurement of POshbetween two failures of synchronism in cycles and tracking of changes to the conditions of communication. If we assume that failures of synchronism in cycles occur relatively infrequently, i.e., intervals that are much longer than the time of the Q cycle of the clock, in practice, the value of Q may be chosen as

where1- upper limit amount is>and u1; [] means rounding to the nearest integer.

For determining the quality characteristics of the device to synchronize the cycles were built his analytical (Kalinnikov centuries, tashlinskii A., an Analytical model of the system frame synchronization in parallel and recircularii search clock. - Ulyanovsk: UFWOC, 2002. 28 S. - Dept. in ZUNI the defense Ministry 02.10.02. No. b, publ. SNR, ser.B, vol.61, 2002) and simulations (Kalinnikov centuries, tashlinskii A., a Simulation model of the system frame synchronization in parallel and recircularii search clock. - Ulyanovsk: UFWOC, 2002. 32 S. - Dept. in ZUNI the defense Ministry 02.10.02. No. b, publ. SNR, ser.B, vol.61, 2002), on the basis of which the technique of finding the threshold numbers and the maximum weight of response to the synchronization signal depending on the probability of erroneous reception of characters singlegroup (see Kalinnikov centuries, tashlinskii A., methods of finding the internal parameters of the system frame synchronization in parallel and recircularii search. - Ulyanovsk: UFWOC, 2002. 35 S. - Dept. in ZUNI the defense Ministry 23.09.02. No. b, publ. SNR, ser.B, vol.61, 2002).

The simulation was performed with the following initial data:

- the length of the transmission cycle N=1200;

- length singlegroup m=9 (000111011);

- speed is the probability of erroneous reception of a single character POsh=5· 10-2(for the "worst case").

The result of simulation of the device showed the following characteristics (in parentheses are the characteristics of the prototype):

- average time to restore synchronism 5 MS (25 MS):

- the probability of false detection of synchronism 10-3(6· 10-3).

The simulation confirmed the achievement of the technical result is to increase speed and noise immunity - during implementation of the invention.

The above data confirm that the implementation of the use of the claimed device the following cumulative conditions:

the tool embodying the claimed device in its implementation, is intended for use in the receiving device sync cycles of transmission of discrete messages;

for the claimed device, as it is characterized in the claims, confirmed the possibility of its implementation using the steps described in the application or known before the priority date tools and methods;

the tool embodying the claimed invention in its implementation, is able to achieve perceived by the applicant of the technical result.

Thus, the claimed izobreteny trojstvo sync cycles, containing Recognizer clock, the main output of which is connected to the first input of the adder, the output of which is connected to the signal input of the shift registers, the main output of which is connected with the second input of the adder, and an additional output unit shift registers connected to the signal input of the decision making node, the output of which is connected to the input of the shaper cyclic pulses and block shift registers, a clock input which is combined with the clock inputs of the detector clock, a casting site and shaper of such pulses, and the control input of the decision making node is combined with the output of the block selection threshold and the counter distorted singlesymbol, the output of which is connected to the address input of the block selection threshold, and a count of the total number of clock pulses, the output of which is connected to the reset input of the counter distorted singlesymbol and with the control input of the block selection threshold, and the signal input of the Recognizer clock, clock input and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output device, characterized in that it introduced the block selection maximum weight response, the counter clock pulses trigger the detector errors synchrogram, the first output of which is connected to the first input of the shaper weight response to the synchronization signal, the output of which is the primary output of the Recognizer clock, an additional output which is the second output of detector errors synchrogram, which is also connected to the third input of the shaper weight response to the synchronization signal, and the signal and control inputs of the detector clock are respectively the information input of the shift register and the second input of the shaper weight response to the synchronization signal, and a clock input of the detector clock is the clock input of the shift register, which is also combined with a clock input of the shaper weight response to the synchronization signal, the counter distorted singlesymbol, counter clock pulses and the first input element And the output of the counter clock pulses is connected to the reset input of trigger, the input set which is connected to the output of the shaper cyclic pulses to the control input of the counter distorted singlesymbol, and the trigger output is connected to the reset input of counter clock pulses and the second input element And the output of which is connected to a clock input of a counter of the total number of clock pulses, the output of which is increasinglv connected to the secondary output of the detector clock and the output of the counter distorted singlesymbol to the address input of the block selecting the maximum weight response, the output of which is connected with the control input of the detector clock.



 

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Device sync cycles // 2192711
The invention relates to communication technology and can be used for receiving data from a downhole telemetry system using looped packets of digital data

FIELD: digital communications.

SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.

EFFECT: higher reliability, higher effectiveness, higher interference resistance.

1 cl, 3 dwg

FIELD: communications.

SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.

EFFECT: higher trustworthiness.

1 dwg

FIELD: digital communications;

SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.

EFFECT: enlarged functional capabilities.

1 cl, 2 dwg

FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.

SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.

EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.

1 dwg

FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.

EFFECT: increased interference resistance of device for cyclic synchronization.

4 dwg

FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.

SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.

EFFECT: expanded functional capabilities of device for cyclic synchronization.

2 cl, 3 dwg

FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.

SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.

EFFECT: increased interference resistance of cyclic synchronization.

2 cl

FIELD: data processing in broadband radio communications and radio navigation.

SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.

EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.

2 cl, 9 dwg

FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.

SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.

EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.

1 cl, 9 dwg

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