Trehkostochny modulator

 

The invention relates to techniques for radio communication and can be used in mobile systems terrestrial and satellite communications. The technical result consists in reducing the actual width of the spectrum of the modulated signal while maintaining the index frequency-shift keying m=0,5. The device includes an analyzer status futuremusic voltage 1, the power sequencing signals given shape and sequence of clock pulses 2, logical block generating control voltages for the unit key 3, key 4, the code Converter 5, two amplitude-phase modulator 6, 7, the phase shifter 8, the carrier generator 9, an adder 10. In the invention the problem is solved using three frequency manipulation to create a frequency-shift keyed signal without breaking phase. 18 Il., 3 table.

The invention relates to the field of radio communications and can be used in digital systems, in particular in satellite and terrestrial mobile radio to generate oscillations with angular modulation with compact spectrum.

Analogues of the claimed devices are frequency modulators using quadrature CX is>/img>/4-DQPSK and CQPSK (Ovchinnikov, M. A., Vorobyov, S. P., Sergeev S. I. Open standards digital trunking radio. Series “Communication in business”. M: ICSTI, LLC “Mobile communications”, 2000, 166 S. Cm. S. 73 158). These modulators are made by the same structural diagrams (Fig. 9.1 and 8.10). They differ only filters and speed of information transmission (S. 160). These modulators include unit conversion, two lowpass filter (filters Nyquist), two of the amplitude modulator and the adder, and two output devices transcoding are connected respectively to the inputs of low-pass filters, the outputs of the low-pass filter connected to the input of the amplitude modulator, the outputs of these modulators are connected to the inputs of an adder whose output is the output of the frequency modulator. The disadvantage of these frequency modulators is the presence of accompanying amplitude modulation of the output signal. With this signal, the power amplifier of the transmitter must operate in a linear mode, which eliminates the possibility of using high-efficiency modes of operation transmitter with high efficiency (80 C.). The cause of concomitant AM is used in the method of forming the modulating voltage for modulator s excitation).

The closest in technical essence is a modulator performing frequency modulation without breaking phase Minimum Shift Keying (MSK) or, equivalently, the minimum modulation frequency shift (MMS) (see the book: the Banquet In L. Dorofeev, C. M. Digital techniques in satellite communications. - M.: Radio and communication. 1988. - 240 S., ill., S. 39-40, Fig. 2.1 b 2.2).

This modulator includes a switch parcel into two channels (even - in one channel, odd in the other), the generator smoothing voltages, two multiplier, a carrier generator, a phase shifter, two amplitude-phase modulator and an adder. Alternate switching parcels input baseband signal into two channels provides a two-fold increase in the duration of parcels in each channel. Smoothing the rectangular parcels of duration 2T0according to the laws of

in each channel, respectively, provides the shape of the envelope of the RF voltages at the outputs of the amplitude and phase modulators in accordance with the voltages u1and u2consequence of which is a smooth change in phase of the RF oscillations at the output of the adder for time T0+/2 or -/2 depending on the RS of the output signal m=0,5. The selected form of the voltages u1and u2at the inputs of the quadrature amplitude and phase modulators provides no concomitant AM output signal, i.e., in this modulator is missing the main disadvantage of modulators and CQPSK/4-DQPSK. In addition, the modulator due to linear phase change over the time of shipment, the absence of phase jumps at the boundaries of the parcels, generates a modulated output frequency voltage with compact spectrum. The real spectrum width modulated so signal is 1.18 V, where V is the transmission rate, bit/s used in the modulator MMS Gauss filter gives additional possibilities for reducing the occupied bandwidth (modulation GMSK, see, for example, the book: Ratynski M. C. Fundamentals of cellular communication/ Ed. by D. B. Zimin. - M.: Radio and communication, 1998. - 248 S., ill., S. 121-126). In addition, this modulator has no direct impact on the generator carrier, thus ensuring high stability of the carrier oscillation, and the possibility of rapid change of the carrier frequency, which is important for systems with abrupt frequency change.

However, the requirements for reducing the actual width of the spectrum is increasing and the possibility of modulating meremove signal is a lack of modulator MMS. The reason for this is the use of dual frequency modulator modulation, and accordingly, a binary digital signal having information redundancy, which is not used to reduce the actual width of the spectrum.

The claimed invention is directed to solving the problem of three frequency manipulation to create a frequency-shift keyed signal without breaking phase. This allows the use of information redundancy binary digital signal. as well as the reduction of the frequency deviation and the redistribution of energy in the spectrum of the signal to obtain the main technical result is the reduction of the real width of the spectrum while maintaining the index of the frequency modulation m=0,5.

The solution to this problem is achieved by the frequency modulator, comprising a generator carrier, Phaser, two amplitude-phase modulator and the adder, and the output of the carrier generator connected to the first input of the first amplitude-phase modulator and to the input of the phase shifter, the output of the phase shifter connected to the first input of the second amplitude-phase-modulator outputs the amplitude and phase modulators are connected, respectively, with first and second inputs of the adder, sobrasada stress the power sequencing signals given shape and sequence of clock pulses, the logic unit generating control voltages for the unit keys, unit keys and code Converter, and one input of the code Converter is the entrance trekhchastichnogo modulator, three other input connected to three respective outputs of the power sequencing signals given shape and sequence of clock pulses, three outputs of the code Converter are connected with three corresponding inputs of the logic unit generating control voltages for the unit keys, eight other inputs of the logic unit generating control voltages for the unit keys are connected with eight corresponding outputs of the analyzer States futuremusic stress the eight outputs of logic unit generating control voltages for the unit keys are connected with the eight control inputs of block keys, four signal input unit keys are connected with the four corresponding outputs of the block sequencing signals given shape and sequence of clock pulses, the first block of keys is connected with the voltage, the second output unit of the keys connected with the second input of the second amplitude-phase modulator and the second input of the analyzer status futuremusic voltage, and two output power sequencing signals given shape and sequence of clock pulses connected to the input of the code Converter, connected to the third and fourth inputs of the analyzer status futuremusic stress.

Analyzer status futuremusic stress includes two inverter 8 elements, one element NO, three elements OR 8 wheel pulses, and the input of the first inverter is connected with the first inputs of the first and second elements And is the first input of the analyzer status futuremusic voltages, the input of the second inverter is connected with the first inputs of the fifth and sixth elements And the second input of the analyzer status futuremusic voltage, the output of the first inverter is connected with the first inputs of the 3rd and 4th elements And, the output of the second inverter is connected with the first inputs of the 7th and 8th elements And the first input of the first element OR is connected with the second inputs of the 1-, 3-, 5 - and 7-th elements of And and is the third input of the analyzer status fatouraee the fourth input of the analyzer status futuremusic stress the output of each of the elements And is connected to the corresponding input of the second element OR, alternatively, the output of the first element And is connected to a second input of the third element OR the output element And with the second to eighth connected with the first inputs of dilators pulses, respectively, from second to eighth, the output of the first element OR is connected with the first input element is NOT present and the second inputs of all of the extenders pulses, the output of the second element OR is connected with the second input element is NOT present, the output element is NOT connected to the first input of the third element OR the output of which is connected to the first input of the first pulse extender, and outputs extenders pulses are output analyzer status futuremusic stress.

The power sequencing signals given shape and sequence of clock pulses includes a master oscillator, frequency dividers by two, 4 and 6, block preset trigger frequency dividers, four differentiating circuit with a limit on the minimum, two driver sawtooth voltage, two driver voltage sine wave and one element OR the output of master oscillator is connected with lane is toty 4 and 6, second input of the frequency divider by two is connected with the first output unit preset trigger frequency dividers, the second inputs of the frequency dividers 4 and 6 are connected with the second output unit preset trigger frequency dividers, the first output of the frequency divider 6 is connected with the input of the second driver of the sawtooth voltage and to the input of the first differential circuit with a limit on the minimum, the output of which is the output of the power sequencing signals given shape and sequence of clock pulses, the second output of the frequency divider 6 is connected with the input of the first driver of the sawtooth voltage and the input of the second differentiating circuit with a limit on the minimum the output which is the output of the power sequencing signals given shape and sequence of clock pulses, the first output of the frequency divider 4 is connected with the input of the third differential circuit with a limit on the minimum, the second output of the frequency divider 4 is connected with the input of the fourth differential circuit with a limit on the minimum, the output of the first driver of the sawtooth voltage is connected with the input of the first formirovaniia signals given shape and sequence of clock pulses, the output of the second shaper of the sawtooth voltage is connected with the input of the second driver voltage sine wave output, two outputs which are the outputs of the power sequencing signals given shape and sequence of clock pulses, the output of the third differential circuit is connected to the first input element OR the fourth output of the differentiating circuit is connected with the second input of the OR element and the output element OR is the output of the power sequencing signals given shape and sequence of clock pulses.

Logical unit generating control voltages for the block of keys made on 24 elements And 14 elements OR, with the first inputs of elements And the first to the eighth are interconnected and are the first input of logic unit generating control voltages for a block of keys, the first inputs of elements And 9 through 16 are interconnected and are the second input of logic unit generating control voltages for a block of keys, the input elements And from the 17th to 24th connected to each other and a third input of logic unit generating control voltages DL the ski unit generating control voltages for a block of keys, the second inputs of the 2-, 10 - and 18-th elements And connected to each other and are the fifth input of logic unit generating control voltages for the unit key, the second inputs of the 3-, 11 - and 19-th elements And connected to each other and are the sixth input of logic unit generating control voltages for the unit key, the second inputs of the 4-, 12 - and 20-th elements And connected to each other and are the seventh input of logic unit generating control voltages for the unit key, the second inputs of 5, 13 - and 21-th elements And connected to each other and are the eighth input of logic unit generating control voltages for the unit key, the second inputs of the 6-, 14 - and 22-th elements And connected to each other and are the ninth input of logic unit generating control voltages for the unit key, the second input 7-, 15 - and 23-th elements And connected to each other and are the tenth input of logic unit generating control voltages for the unit key, the second inputs 8-, 16 - and 24-th elements And connected to each other and are eleventh input of logic unit generating control voltages for the unit key, the output of the first element And is connected to the inputs of the 1st and 8th elements OR output VMI 3-th and 10-th elements OR the fourth output element And is connected to the inputs of the 4-th and 11-th elements OR output Patou element 11 is connected to the inputs of the 4-th and 9-th elements OR the output of the sixth element And is connected to the inputs of the 3-th and 8-th elements OR the output of the seventh element And is connected to the inputs of the 2-th and 11-th elements OR the output of the eighth element And is connected to the inputs of the 1-th and 10-th elements OR the output of the ninth element And is connected to the inputs of the 5-th and 14-th elements OR the output of the tenth element And is connected to the inputs of the 5-th and 14-th elements OR the output of the eleventh element And is connected to the inputs of the 6-th and 14-th elements OR the output of the twelfth element And is connected to the inputs of the 6-th and 14-th elements OR the output of the thirteenth element And is connected to the inputs of the 7-th and 13-th elements OR the output of the fourteenth element And is connected to the inputs of the 7-th and 13-th elements OR the output of the fifteenth element And is connected to the inputs of the 7-th and 12-th elements OR the output of the sixteenth element And is connected to the inputs of the 7-th and 12-th elements OR the output of the seventeenth element And is connected to the inputs of the 1-th and 10-th elements OR output eighteenth element And is connected to the inputs of the 2-th and 11-th elements OR the output of the nineteenth element And is connected to the inputs of the 3-th and 8-th Elo element And is connected to the inputs of the 2-th and 9-th elements OR the twenty-second output element And is connected to the inputs of the 1st and 8th elements OR the output of the twenty-third element And is connected to the inputs of the 4-th and 11-th elements OR the output of the twenty-fourth element And is connected to the inputs of the 3-th and 10-th elements OR, as the outputs of all elements OR are the outputs of logic unit generating control voltages for the block of keys.

Key block consists of 14 analog switches, and the input pairs 1 and 8, 2 and 9, 3 and 10, 4 and 11, 5 and 12, 6 - and 13-th, 7 - and 14-th analog switches are interconnected and are the inputs of the block of keys, the second inputs of all of the keys are also the inputs of the block of keys, the outputs of the analog switches 1 to 7 are interconnected and are the first output unit key outputs of the analog switches with 8 to 14 are also connected to each other and are the second output block of keys.

Code Converter includes a shift register, 3 item NO, 8 items 10 items OR 7 extenders pulses and three element THERE, and the first input of the shift register is the first input of the code Converter, the second input of the shift register is connected to the first input of the first extender pulses and a second input of the code Converter,is the third input of the code Converter, the output of the first pulse extender connects to the third input of the shift register and the fourth inputs of elements And the first output of the shift register is connected with the input of the first element and NOT to the inputs 5-, 6-, 7 - and 8-th element And the second output of the shift register is connected with the input of the second element and to the inputs of 3-, 4-, 7 - and 8-th elements, And the third output of the shift register is connected with the input of the third element and NOT to the inputs of 2-, 4-, 6 - and 8-th elements And the output of the first element is NOT connected to inputs 1-, 2-, 3 - and 4-th elements And the output of the second element is NOT connected to inputs 1-, 2-, 5 - and 6-th elements And the output of the third element is NOT connected with the inputs of the 1-, 3-, 5 - and 7-th elements And the output of the first element And is connected to the inputs of the 3 - and 6-th elements OR the output of the second element And is connected to the inputs of the 3 - and 5-th elements OR the output of the third element And is connected to the inputs of the 3 - and 4-th elements OR the fourth output element And is connected to the inputs of the 2 - and 6-th elements OR the output of the fifth element And is connected to the inputs of the 2 - and 5-th elements OR the output of the sixth element And is connected to the inputs of the 2 - and 4-th elements OR the output of the seventh element And is connected to the inputs of the 1 - and 5-th elements OR the output of the eighth element And is connected to the inputs of the 1 - and 4-Steno, from the second to the seventh, the second inputs of the second, third and fourth wheel pulses are interconnected and are the fourth input of the code Converter, the output of the second pulse extender connects to the inputs 7 - and 8-th elements OR the output of the third pulse extender connects to the inputs 7 - and 9-th elements OR the output of the fourth pulse extender connects to the inputs 7 - and 10-th elements OR output Patou extender pulses is connected to the first input of the first element is NOT present, the output of the sixth pulse extender is connected with the first input of the second element is NOT present, the output of the seventh pulse extender is connected to the first input of the third element is NOT present, the output of the 7th element OR is connected with the second inputs of NO elements, the outputs of the first, second and third elements NOT connected with the inputs, respectively, of the eighth, ninth and tenth elements OR outputs which are the outputs of the code Converter.

A set of indicators in General trehkostochny modulator, provides technical result in all cases to which is sought legal protections, and the features related to the analyzer status futuremusic voltage,the logic unit generating control voltages for a block of keys, block keys and code Converter, characterize its only in the specific form of execution.

All the essential features of the claimed invention are in causal relationship with achievable technical result. Code Converter from the input modulating binary signal having a duration of elements of T0forms a ternary signal is in a position code having length parcels 3T0/2. To implement the modulation of the carrier that the ternary signal is used trichastoma modulation without breaking phase. The frequency of sending an RF signal is modified by using the elements used in the device-prototype: amplitude and phase modulators, carrier generator, the phase shifter and adder. However, in order modulation was trekhchastichnoi, to the inputs of the phase modulators must be submitted modulating (futuremouse) voltage of a special form. These stresses are formed functional nodes that are not in the prototype: analyzer status futuremusic voltages, power sequencing signals given shape and sequence of clock pulses, a logical block groups of control voltages for the unit key and block the entrances amplitude and phase modulators in each clock time, logical unit generating control voltages for the block of keys on the basis of the results of this analysis and output signals of the Converter code defines the shape futuremusic stresses, which should be received at each amplitude and phase modulator in the next clock interval, to make the output voltage had a frequency, and opens the necessary key pair in the block of keys (one for each amplitude-phase-modulator). Through the public keys necessary futuremouse voltage outputs of the power sequencing signals given shape and sequence of clock pulses arrive at the amplitude and phase modulators. At the output of the frequency modulator is formed trehkostochny modulated signal without breaking phase with the modulation index of 0.5. The duration of the parcels of this signal is 1.5 times longer than the length of the parcels binary digital signal fed to the input of the modulator and, respectively, 1.5 times longer than the length of the parcels signal MMS. The increase in the duration of assumptions leads to a decrease in the real width of the signal spectrum, which determines the technical result of the claimed invention. In addition t the manipulation is at the carrier frequency, i.e. in the middle between the first two frequencies, and these two factors also reduce the width of the signal spectrum.

In Fig.1 shows a structural diagram of a frequency modulator in Fig.2 is a block diagram of the analyzer status futuremusic stresses, Fig.3 is a structural block circuit diagram of the sequencing of the signals of the preset forms and sequences of clock pulses of Fig.4 is a structural diagram of the logic unit generating control voltages for the block of keys of Fig.5 is a structural block circuit diagram of the keys of Fig.6 is a structural diagram of the code Converter of Fig.7 is a diagram of the element 8, OR, in Fig.8 is a diagram element is NOT present, Fig.9 - diagram of the pulse extender of Fig.10 diagram of the oscillator of Fig.11 is a block circuit preset trigger frequency divider of Fig.12 is a diagram of the frequency divider at six, Fig.13 is a diagram of the forming voltage of rectangular shape and shaper of the voltage sine wave, Fig.14 is a diagram of a differentiating circuit with a limit on the minimum in Fig.15 - scheme element 4 OR of Fig.16 is a timing diagram of signals in the power sequencing signals given shape and sequence of clock pulses of Fig.17 is a time chart what about the modulator.

Trehkostochny modulator contains the analyzer 1 status futuremusic stresses, block 2 sequencing signals given shape and sequence of clock pulses, logical block 3 generating control voltages for the unit key unit 4 key Converter 5 code first amplitude-phase modulator 6, the second amplitude-phase modulator 7, the phase shifter 8, the carrier generator 9 and the adder 10. The analyzer 1 status futuremusic voltages includes inverters 11 and 12, the elements 14-21 And the elements 13, 22, 23, OR, the element 24 and NO extenders 25-32 pulses. Unit 2 sequencing signals given shape and sequence of clock pulses includes a master oscillator 33, the divider 34 frequency by two, the divider 35 frequency 6, the divider 36 frequency 4, block 37 preset, the formers 38 and 39 of the sawtooth voltage, the formers 40 and 41 of the voltage sine wave, differentiating circuits 42-45 limited to a minimum and the element 46 OR. Logical unit generating control voltages for the block of keys contains elements 47-70 And elements 71-84 OR. Key block contains analog switches 85-98. Converter 5 code register contains 99 shift, elem is the input of the Converter 5 of the code (Fig.6 this is the first input register 99 shift) is the entrance trekhchastichnogo modulator, to which is fed the input of the binary modulating signal. The second input of the inverter 5 of the code is connected with the output element 46 OR block 2 sequencing signals given shape and sequence of clock pulses (clock pulses TI, see Fig.16). The third input of the code Converter connected to the input of the expander 103 pulses, is connected with the output of the differentiating circuit 42 (pulses TI, Fig.16). The fourth input of the Converter 5 of the code connects to the output of the differentiating circuit 43 unit 2 sequencing signals given shape and sequence of clock pulses (pulses TI, Fig.16). Three inverter output code 5 are connected to three inputs of a logical block 3 generating control voltages for the unit key, and the output element 125 OR connected with the first inputs of the elements 47-54 And the output element 126 OR connected with the first inputs of the elements 55-62 And the output element 127 OR connected with the first inputs of the elements 63-70 I. 14 outputs a logical block 3 generating control voltages for the unit keys are connected with 14 inputs a block of keys, and the output element 71 OR connected with the control input of the key 85, the output element 72 OR the d element 74 OR connected with the control input of the key 88, the output element 75 OR connected with the control input of the key 89, the output of element 76 OR connected with the control input of the key 90, the output of element 77 OR connected with the control input of the key 91, the output of element 78 OR connected with the control input of the key 93, the output of element 79 OR connected with the control input of the key 92, the output of element 80 OR connected with the control input of the key 95, the output of element 81 OR connected with the control input of the key 94, the output element 82 OR connected with the control input of the key 97, the output of element 83 OR connected with the control input of the key 96, the output of the element 84 is connected with the control input of the key 98. The eight outputs of the analyzer 1 status futuremusic voltages are connected to eight inputs of a logical block 3 generating control voltages for the unit key, and the output of the expander 25 pulses is connected with the second inputs of the elements 47, 55, 63 And the output of the expander 26 pulses is connected with the second inputs of the elements 48, 56 and 64 And the output of the expander 27 pulses is connected with the second inputs of the elements 49, 57 and 65, And the output of the expander 28 pulses is connected with the second inputs of the elements 50, 58, 66, the output of the extender 29 impulses connected with the second inputs of the elements onpulse connected with the second inputs of the elements 53, 61 and 69, And the output of the expander 32 pulses is connected with the second inputs of the elements 54, 62 and 70 And. Four output unit 2 sequencing signals given shape and sequence of clock pulses are connected to four inputs of block 4 of keys, the first output driver 40 of the voltage sine wave is connected with the signal input keys 85 and 92, the first output driver 41 of the voltage sine wave is connected with the signal inputs of the keys 86 and 93, the second output driver 40 of the voltage sine wave is connected with the signal input keys 87 and 94, the second output driver 41 of the voltage sine wave is connected with the signal inputs of keys 88 and 95. At the signal inputs of keys 89 and 96 direct voltage level of +and, at the signal inputs of the keys 90 and 97, direct voltage, for signal input keys 91 and 98 is served zero voltage. The first output unit 4 keys connects with the first analyzer input 1 status futuremusic voltage, and the connection point of the keys 85-91 connected to the inputs of the inverter 11 and the elements 14 and 15, and this point is connected with a second input of the amplitude-phase modulator 6. The second output of blocmania keys 92-98 connected to the input of inverter 12 and the elements 18 and 19 And, and this point is connected with a second input of the amplitude-phase modulator 7. Two output unit 2 sequencing signals given shape and sequence of clock pulses connected to two respective inputs of the analyzer 1 status futuremusic voltages, the outputs of the differentiating circuits 42 and 43 are connected, respectively, to the inputs of the element 22 OR.

In the analyzer 1 status futuremusic voltage input of the inverter 11 is connected with the first inputs of the elements 14 and 15 And the input of the inverter 12 is connected with the first inputs of the elements 18 and 19 And the output of the inverter 11 is connected with the first inputs of the elements 16 and 17 And the output of the inverter 12 is connected with the first inputs of the elements 20 and 21 And the first input element 22 OR connected with the second inputs of the elements 14, 16, 18 and 20, And the second input element 22 OR connected with the second inputs of the elements 15, 17, 19 and 21 And, the output of each of the elements And is connected to the corresponding input of the element 13 and, in addition, the output of element 14 And is connected to a second input element 23 OR the outputs of the elements 15-21 And connected with the first inputs of dilators 26-32 pulses, the output element 22 OR connected with the first input element 24 and NO to the second inputs of all EXT is aetsa with the first input element 23 OR the output of which is connected to the first input of the expander 25 pulses, and outputs extenders pulses are output analyzer 1 status futuremusic stress.

In unit 2 the formation of sequences of signals of a given shape and sequence of clock pulses, the output of oscillator 33 (see Fig.3) is connected to the first input of the divider 34 frequency by two, the output of divider 34 frequency on two connected with the first inputs of the divider 35 frequency 6 and divider 36 frequency by 4, the second input of the frequency divider by two is connected with the first output unit 37 preset, the second inputs of the dividers 35 and 36 frequency at 4 and 6 are connected with the second output unit 37 preset trigger frequency dividers, the first output of the divider 35 frequency 6 is connected with the input of the shaper 39 of the sawtooth voltage and to the input of a differentiating circuit 42 with a limit on the minimum the output which is the output of block 2 of the sequencing of the signals of the preset forms and sequences of clock pulses, the second output of the divider 35 frequency 6 is connected with the input of the shaper 38 of the sawtooth voltage and to the input of the differentiating circuit 43 to a limitation in the minimum, the output of which is Allah pulses, the first output of the divider 36 frequency 4 is connected with the input of the differentiating circuit 44 to a limitation in the minimum, the second output of the divider 36 frequency 4 is connected with the input of the differentiating circuit 45 to a limitation in the minimum, the output of the shaper 38 of the sawtooth voltage is connected with the input of the shaper 40 voltage sine wave output, two outputs which are the outputs of block 2 of the sequencing of the signals of the preset forms and sequences of clock pulses, the output driver 39 of the sawtooth voltage is connected with the input of the shaper 41 voltage sine wave output, two outputs which are the outputs of block 2 of the sequencing of the signals of the preset forms and sequences of clock pulses, the output of the differentiating circuit 44 is connected to the first input element 46 OR the output of the differentiating circuit 45 is connected with the second input element 46 OR, as the output element 46 OR is the output of block 2 sequencing signals given shape and sequence of clock pulses.

In the logical unit 3 generating control voltages for the unit keys the input elements 47-54 And connected to each other and aviamento 55-62 And connected to each other and are the second input of logic unit 3 generating control voltages for a block of keys, the input elements 63-70 And connected to each other and a third input of logic unit 3 generating control voltages for the unit key, the second inputs of the elements 47, 55 and 63 And connected to each other and are the fourth input of logic unit 3 generating control voltages for the unit key, the second inputs of the elements 48, 56 and 64 And connected to each other and are the fifth input of logic unit 3 generating control voltages for the unit key, the second inputs of the elements 49, 57 and 65 And connected to each other and are the sixth input of logic unit 3 generating control voltages for a block of keys, second input elements 50, 58 and 66 And connected to each other and are the seventh input of logic unit 3 generating control voltages for the block of keys.

The second inputs of the elements 51, 59 and 67 are interconnected and are the eighth input of logic unit 3 generating control voltages for the unit key, the second inputs of the elements 52, 60 and 68 And connected to each other and are the ninth input of logic unit 3 generating control voltages for the unit key, the second inputs of the elements 53, 61 and 69 And connected to each other and are the tenth logic of a BDU and is the eleventh input of logic unit 3 generating control voltages for a block of keys, the output element 47 And is connected to the inputs of the elements 71 and 78 OR the output element 48 And is connected to the inputs of the elements 72 and 78 OR the output element 49 And is connected to the inputs of the elements 73 and 80 OR the output element 50 And is connected to the inputs of the elements 74 and 81 OR the output element 51 And is connected to the inputs of the elements 74 and 79 OR the output element 52 And is connected to the inputs of the elements 73 and 78 OR the output element 53 And is connected to the inputs of the elements 72 and 81, OR the output of the element 54 And is connected to the inputs of the elements 71 and 80 OR the output element 55 And is connected to the inputs of the elements 75 and 84, the output of element 56 And is connected to the inputs of the elements 75 and 84, the output of the element 57 And is connected to the inputs of the elements 76 and 84, the output of element 58 And is connected to the inputs of the elements 76 and 84, the output of element 59 And is connected to the inputs of the elements 77 and 83 OR the output element 60 And is connected to the inputs of the elements 77 and 83, OR the output element 61 And is connected to the inputs of the elements 77 and 84, the output of element 62 And is connected to the inputs of the elements 77 and 84, the output of element 63 And is connected to the inputs of the elements 71 and 80 OR the output element 64 And is connected to the inputs of the elements 72 and 81 OR the output element 65 And is connected to the inputs of the elements 73 and 78 OR the output element 66 And is connected to the inputs of elements stored the mi elements 71 and 78, OR, the output element 69 And is connected to the inputs of the elements 74 and 81 OR the output element 70 And is connected to the inputs of the elements 73 and 80 OR, as the outputs of all elements OR are the outputs of logic unit 3 generating control voltages for the block of keys.

In block 4 keys the first inputs of the analog switches in pairs 85 and 92, 86 and 93, 87 and 94, 88 and 95, 89 and 96, 90 and 97, 91 and 98 are interconnected and are the signal inputs of the block 4 keys, the second inputs of all analog switches are control inputs of the block 4 key outputs of the analog switches 85 through 91 are interconnected and are the first output unit 4 key outputs of the analog switches 92 through 98 are also connected to each other and are the second output unit 4 keys.

In the Converter 5 code first input register 99 shift is the first input of the Converter 5 of the code, the second input register 99 shift is connected to the first input of the expander 103 pulses and a second input of the Converter 5 of the code, the second input of the expander 103 pulses is connected with the second inputs of the dilators 121-123 pulses and is the third input of the Converter 5 of the code, the output of the expander 103 pulses is connected with the third input of the register 99 shift and fourth inputs of the elements 104 to 111 And, egistra 99 shift is connected with the input element 101 and to the inputs of the elements 106, 107, 110 and 111, And the third output register 99 shift is connected with the input element 102 and to the input of elements 105, 107, 109 and 111 And the output element 100 is NOT connected to the inputs of the elements 104-107, And the output element 101 is NOT connected to the inputs of the elements 104, 105, 108 and 109 And the output element 102 is NOT connected to the inputs of the elements 104, 106, 108 and 110 And the output element 104 And is connected to the inputs of elements 114 and 117 OR the output of element 105 And is connected to the inputs of elements 114 and 116 OR the output element 106 And is connected to the inputs of elements 114 and 115 OR the output element 107 And is connected to the inputs of elements 113 and 117, OR the output element 108 And is connected to the inputs of elements 113 and 116 OR the output element 109 And is connected to the inputs of elements 113 and 115 OR the output element 110 And is connected to the inputs of the elements 112 and 116 OR the output element 111 And is connected to the inputs of the elements 112 and 115 OR the outputs of the elements 112-117 OR are connected, respectively, with the first inputs of dilators 118-123 pulses, a second input extenders 118-120 pulses are interconnected and are the fourth input of the Converter 5 of the code, the output of the expander 118 pulses is connected with the first inputs of the elements 124 and 125, OR output expander 119 pulses connected to the inputs of the elements 124 and 126, OR output expander 120 is ment 128 NO the output of expander 122 pulses is connected with the input element 129 NO, output expander 123 pulses is connected with the input element 130 is NO, the output element 124 OR connected with the inputs of the elements 128, 129 and 130 NO, the outputs of the elements 128, 129 and 130 is NOT connected to the inputs, respectively, of the elements 125, 126 and 127 OR, the outputs of which are the outputs of the Converter 5 of the code.

Most of the functional nodes trekhchastichnogo modulator are performed on the IC: 2-input elements 14-21, 47-70 AND - CLI; 4-input elements 104 to 111 AND CRL; 2-input elements 22, 23, 46, 75, 76, 82, 83, 112, 117, 125-127 OR CRL; 3-input elements 113-116, 124 OR CRL (this ILI-NOT) and CRN (this item is NOT); velmuradova element 13 OR running on two elements 4OR-NOT (CLP) and one element 2I-NOT (KRAS) for the circuit of Fig.7, the elements 24, 128-130 NOT run on the same element (CRL) and one element 2I-NOT on the circuit of Fig.8, extenders 25-32, 103, 118-123 pulse - RSD-triggers KR1533TM2 and inverters CRL on the circuit of Fig.9, the master oscillator 33 can be performed on the IC KRHG on the circuit of Fig.10, block 37 preset can be performed by the circuit of Fig.11 transistors CTG, dividers 34-36 frequency can be performed on RSD-triggers CTM, and the frequency divider Nai Fig.12 before using the output of divide-by-two form elements ILI NOT CRL.

The driver of the sawtooth voltage (PNP) is performed on the integrating RC circuit (with a buffer amplifier operational amplifier, for example, CRUD). Driver voltage sine wave (FTS) is performed according to the scheme presented in the book: Earl R. Electronic circuits: 1300 examples: TRANS. from English. - M.: Mir. 1989, 688 S., ill., S. 618.

Functional scheme of the site, which includes the PNP with the buffer amplifier and the FTS shown in Fig.13. The differentiating circuit 42, 43 with the restriction on the minimum can be performed on RC circuits with elements AND CLI restrict to a minimum, eliminate the negative pulses at the outputs of the differentiating circuits (Fig.14), 4-input elements 71-74, 77-81, 84 OR CLL (combining the outputs of the two elements ILI on the circuit of Fig.15), the elements 100-102 NOT - CRL, a differentiating circuit 42, 43 are in the form of an RC circuit, analog switches 85-98 run on IMS KRKN, register 99 shift is performed on the IC CIR.

Work trekhchastichnogo modulator is as follows. Unit 2 sequencing signals given shape and sequence of clock pulses generates four sequences of a given shape S1-S4and the three posledovatelnostei to the timing charts of Fig.16. The master oscillator 33 generates a square wave with a duration of elements of T0/8, where T0- the duration of the parcels binary signal at the input of the modulator (waveform uZG). The divider 34 frequency for two and a block preset trigger frequency dividers provide mutual synchronization of the output voltage of the generator 2: the signals S1...S4at frequencies=/(3· T0), and with a clock pulse sequence TO coincide maximum positive and negative values of the signals S1and S3and with a clock pulse sequence TO coincide maximum positive and negative values of the signals S2and S4. From the output of the frequency divider by two voltage waveform u:2) is supplied to the frequency dividers 6 and 4. With the direct output of the frequency divider 6 voltage u:6is supplied to the imaging unit 39 and a differentiating circuit 42. The driver of the sawtooth voltage is an integrator (the elements of R and C in the input circuit of Fig.13). The shape of the sawtooth voltage at the output of the imaging unit 39 shown in waveform uFNP(Fig.16). The voltage of this form by the many inverse voltage in the form of sequences of half-wave sinusoid frequency=/3T0(S2and S4in Fig.16).

A differentiating circuit 42 to a limitation in the minimum, performed by the circuit of Fig.14, emits short pulses TO corresponding positive fronts of the voltage u:6(waveform TI in Fig.16). Differentiation of the pulses from the output of the divider 36 frequency by 4, and the Association of positive pulses in the element 46 OR network heartbeats THE generator output (waveform u:4and TI in Fig.16). Similarly formed voltage S1and S3at the output of the shaper 40 and sequence TI at the output of the differentiating circuit 43; waveforms of these signals is shown in Fig.16.

The unit is preset trigger frequency dividers, the scheme of which is shown in Fig.11, together with the divider 34 frequency provides two simultaneous initial operation of the frequency dividers 4 and 6 from one of the front input signal and the required mutual arrangement of the output signals on the time axis in the process. It is provided as follows. At power-charging the capacitors in the base circuits of the transistors (Fig.11). The time constant of the charge circuit of the second capacitor is smaller h is m first. The voltage output of the second transistor is supplied to the inputs R of the flip-flops of the frequency dividers 4 and 6, and sets these triggers in the same initial state. After this specified level output voltage appears at the output of the first transistor, this voltage is applied to the input R of the divider 34 frequency by two and provides it a work mode (frequency division). The first differential voltage at the output of this divider will provide simultaneous switching of flip-flops in the divider 4 and 6, i.e., the synchronism of these divisors. The received signals S1-S4go to the inputs of analog switches, the clock pulses TI and TI on the analyzer status, and TI, TI and TI - in code Converter.

Code Converter (Fig.6) solves the problem of converting binary code to the duration of parcels T0in the ternary position code duration parcels Tt=1,5· T0. The principle of his work is illustrated by the waveforms of Fig.17. Input modulating binary signal (waveform uwithrouted to the first input (S1) register 99 shift (CIR). The principle of operation of this register and the operation modes described in the book: Shyla C. L. Popular digital circuits: Handbook. 2nd ed., Corr. - Chalabi what I provide sequential mode of the input binary signal in the register is connected with the zero potential of the scheme. To the input of register serves pulsing pulses TI. The read signal is performed simultaneously with the first three digits of the register is fed to the input E0 of pulses TI (waveform TI). These pulses are generated using the expander 103 pulses in action at the input of the inverter (see Fig.9) clock pulses TI and input With trigger - clock pulses t0. When unit voltage TO register exit Z (tripping), and its outputs Q0, Q1 and Q2 appear, respectively, parcels 1, 2 and 3 from each group sequentially following assumptions, which in Fig.17 indicated by the arrows above the signal uc. Thus, sending each group of three elements appear on the outputs of the register in parallel code (waveform RG1, RG2 and RG3). The next group of elements of a code Converter - eight items And (104 to 111) together with the inverters 100-102 does NOT provide identification code combination of parcels received at the outputs of the register. If it be received code combination, 000, there is a single parcel of duration at the output of the first element And (104), if it be received code combination, 001, there is a single voltage at the output of the second element And (105), and so on Poradek the Istra (waveform I-I).

Elements 112-117 OR are identified by a code combination in the ternary positional code. Adopted under binary and ternary codes is as follows:

The first characters of the ternary code is represented in a positional code at the outputs of the first three elements OR (112-114), and the second symbols at the outputs of the second three elements OR (115-117). A single parcel on the output element 112 OR zeros on the outputs of elements 113 and 114 OR mean that the first character of the ternary code is +1. A single parcel at the output of element 113 OR zeros on the outputs of the elements 112 and 114 OR mean that the first character of the ternary code is 0. A single parcel on the output element 114 OR zeros on the outputs of the elements 112 and 113, OR mean that the first character of the ternary code is -1. Similarly, the outputs of the elements 115-117 OR determine the second character of the ternary code. For example, if you receive a single element to the output element 104 And, it means that the input is valid code group 000, the ternary code combination according to the above table must be of the form-1-1 and, therefore, must be allocated to a single parcel with a duration on the outputs of the elements 114 and 117 OR. This is provided by connecting the output of the and elements 112-117 OR.

Extenders 118-123 pulses (Fig.9) increase the duration of individual parcels. When input S is a positive voltage which is obtained at the output of the inverter after the end of the input pulse, the trigger is set in one state. The clock pulses at the input To translate the trigger is in the zero state. Thus, the leading edge of the output of parcels is determined by back-to-back pulses at the input of the inverter, and the rear front front edges of the pulses at the input C. the Feature of the dilators of the pulses in the code Converter is the extension of pulses: pulses from the outputs of the elements 112-114 OR expand to the required values of Tt=3T0/2, and the pulses from the outputs of the elements 115-117 OR expand to values 3T0. This is due to the fact that single pulses at the outputs of each pair of elements 112-117 OR appear simultaneously, and since the elements 115-117 OR determine the second character of the ternary code, next to the first, the relevant parcels on the Converter output code should appear later than those parcels, which are formed at the output of the assumptions at the outputs of the elements 112-114 OR. Delay parcels is carried out in two steps: first, the duration of the x pulses of duration 3T0/2 eliminated elements 128-130 NO. The difference in expansion of the pulses provided by the feed wheel pulses (input triggers KR1533TM2) various clock: on extenders 118-120 pulse sequence is TI and extenders 121-123 pulse sequence TI. To the timing charts of Fig.17 RE-RI (RI - extenders pulses) shows the form of the signals at the outputs of wheel pulses. See, in particular, that the end of the pulses at the output extenders 118-120 pulses determined by the pulse TI and end of the pulses at the outputs of dilators 121-123 pulses is set by the pulses TI.

Eliminating the first half of the parcels with outputs extenders 121-123 pulses is carried out in the elements 128-130 NO. For this purpose, the inputs of these elements are, respectively, the signals from the outputs of the dilators 121-123 pulses, and for prohibiting the input elements there are NO signals from the outputs of the dilators 118-120 of pulses combined in element 124 OR. The shape of the signals at the outputs of the elements 124 and OR 128-130 NOT shown in Fig.17. Association OR items (125-127) signals from the outputs of the elements in pairs 118 and 128, 119 and 129, 120 and 130 provides an output signal to position the ternary code. Waveforms of sostoyaniya futuremusic voltage determines the voltage u1and u2the outputs of the block of keys clock moments. Allocated 8 different States, including 4 state for clock times when the impulse TI, and 4 States for the moments when he acts THE. These States and their numbers are presented in the table:

The table shows that condition 1 holds, if the clock time when the clock pulse TI, the voltage u1is +a, and the voltage u2=0. State 2 occurs if the clock time when the clock pulse TO run equality u1=+a, u2=0. And so on, this takes into account that if the clock time one of the voltages u1or u2is +a or-a, the second voltage is necessarily equal to zero.

The analyzer 1 status futuremusic stresses (Fig.2) has 8 outputs. Each output corresponds to a state number according to the table above. If the analyzer detects the condition 1, there is a single parcel of duration Tt=3T0/2 at the output of the expander 25 pulses. If the detected state 2, then a single parcel appears at the output of the expander 26 pulses, etc. Direct analysis done is ementa 14 And receive short pulse, formed from the input pulse TI, acting on the analyzer input 1 status futuremusic stress. In state 2 appears a short pulse at the output of the element 15 And etc. the Duration of these pulses is increased to values of Ttexpanders pulses included in the output of each element Acting Elements 13 OR 24 NO 23 OR form the start circuit. In the initial state, when switching on the modulator, all analog switches 85-98 closed, hence, u1=0 and u2=0. In the operating mode such condition does not happen, and the analyzer 1 status futuremusic strains do not form a unit voltage on any of its outputs. Accordingly, logical block 3 generating control voltages for the unit 4 keys will not work and will not provide for opening a single analog switch; the entire modulator will remain in an unusable state. In order to transfer the modulator is in operation, the first single parcel at the output of the analyzer 1 status futuremusic stress force is formed, which serves as the trigger. She works as follows. If the modulator is enabled and the unit 2 sequencing signals of a given shape, posledovatelnostei will receive a pulse at the output of the element 13. And this impulse is prohibiting element 24 NO. Therefore, the element 24 will NOT be open, and the first clock pulse from the output element 22 OR through the element 24 and NO element 23 OR fed to the input of the expander 25 pulse. The pulse output expander 25 pulses will ensure normal operation of the logical unit 3 generating control voltages for the unit key and the occurrence of the modulator in the operating mode.

Logical block 3 generating control voltages for the block of keys forms the control voltage for the unit keys. The basis for the generation of control voltages are:

- voltages u1and u2the outputs of the block of keys in each clock time and, therefore, the initial value of the output voltage phase modulator at that time;

- the direction and angle of rotation of the vector of the output voltage of the modulator, starting from the given clock time, for the duration of the parcel next to this time; these parameters are determined by a combination of parcels, existing in each clock interval Ttthe outputs of the code Converter (O.1, O.2 and Wk.3 in Fig.17).

Based on the state of the modulator at a given clock m is the cation of control voltages for the block of keys provides opening required key pairs in block of 4 keys. This takes into account asked manipulation code that defines the correspondence between the transmitted ternary symbol and the frequency of the parcel at the modulator output. Choose, for example, the following manipulation code: transmitting element -1 corresponds to the frequency of the parcel f1transfer element 0 corresponds to the frequency f2and the transmission element +1 corresponds to the frequency f3. This is to ensure that their functions logical unit generating control voltages for the unit key 3 must have the following state table:

In this table, x1x2and x3- the values of the input modulating assumptions on the inputs 1, 2 and 3, logical block 3 generating control voltages for the unit key outputs of the code Converter; y1-y8- the logic levels on the outputs of the analyzer 1 status futuremusic stress; z1-z7- the logic levels on the outputs of the elements, respectively, 71-77 OR; z1-z7- the logic levels on the outputs of the elements, respectively, 78-84 OR logical block 3 generating control voltages for the unit keys. According to the circuit of Fig.4 there are two groups of outputs logical the group, and the outputs of the elements 78-84 - the second group. In the first group taken: z1- output element 71 OR, z2- output element 72 OR etc. In the second group it is assumed: z1the output of element 79 OR, z2- output element 78 OR, z3- output element 81 OR etc. on the circuit of Fig.4. Structural diagram of a logical block 3 generating control voltages for the unit keys (Fig.4) prepared according to the above table. The signal x1arrives on the 1st (upper circuit) input logical unit 3 generating control voltage for the unit key, the signal x2- on the 2nd input, x3- on the 3rd, y1- on the 4th, I2- 5-th input, and so on, for Example, if at some clock time analyzer state has identified the 4-th state, then this corresponds to the units in the column y4table. Suppose that after this clock, it is a single parcel on the first input of logic unit 3 generating control voltages for the unit keys. This situation corresponds to the 4th row of the table. In this row of the table, one state specified for outputs z4in the first group of outputs, and z3in the second group of outputs. This means that a single voltage at a given clock interval will appear for you the tons 50, and with its single output voltage is fed to the outputs of the elements 74 and 81 (see diagram Fig.4).

Since the information about the modulating signal is represented on the three outputs of the code Converter, the modulator uses three frequency manipulation: f1f2and f3. The average of these frequencies equal to the frequency of the carrier wave generated by the carrier generator 9, and the other two symmetrically arranged about a Central frequency. To obtain at the output of the modulator parcels with frequencies f1and f3is a smooth rotation of the carrier wave vector, as is done in dual-frequency modulation without breaking phase in the device-prototype (MMS). However, the frequency smoothing voltage trichastoma modulator is selected differently: if the modulator MMS this frequency is equal to/2P0in this case it is equal to/3T0. The rotation vector of the carrier oscillation is functional nodes within the bounding part of the invention. Futuremouse voltage u1and u2acting on the input amplitude and phase modulators 6 and 7 (Fig.9), in this case change for each parcel on /84/847630.gif" border="0">

or

These voltages determine the amplitude and phase of the voltages at the outputs of the amplitude and phase modulators 6 and 7. Taking into account the phase shift to/2, which makes the phase shifter 8 in support of oscillation, the voltage at the outputs of the amplitude and phase modulators are determined, respectively:

These oscillations are summed in the adder 10 and give the output trehkostochny signal

The amplitude U0the output voltage is calculated as follows:

From this equation it is seen that the amplitude U0does not depend on time. This means that the output signal has no amplitude modulation. Phase output voltage:

From this formula it is seen that when the modulation phase of the output voltage is changed in the direction of increasing ( + ) or decrease ( - ), and during one parcel (t=3T0/2) the phase shift costulae/2.

This phase shift corresponds to a frequency offset by the value of

1=±a, u2=0 or u1=0, u2=±a, the additional rotation of the carrier wave vector and frequency of the output of the parcel will remain equal to the carrier frequency generator 9, i.e., get the f2=f0.

Thus, in this modulator is trichastoma modulation with frequency manipulation

f1=f0-fd=f0-1/(6· T0), f2=f0f3=f0+fd=f0+1/(6· T0).

Phase RF parcels when this linearly changes or remains the same in clock intervals and does not have spikes on their boundaries.

Work trekhchastichnogo modulator generally illustrated by the waveforms of Fig.18. When you enable trekhchastichnogo modulator unit 2 sequencing signals given shape and sequence of clock pulses generates three sequences of clock pulses TI, TI and TI shown on the corresponding waveforms of Fig.18. Suppose that at the input of the modulator is fed binary modulating signal uwith(see Fig, 18) with a duration of elements of T0(this signal is accepted the same as in Fig.17). Then the three outputs of the code Converter formed three placentas is Lamy, shown in the waveform “O.1”. “O.2” and “O.3” in Fig.17). In line atishows the number of outputs of the block 4 keys, which determines the analyzer 1 status. In the first clock time when the leading edge of the signals Xi, will the device run in the analyzer 1 status futuremusic voltage and generates a pulse of duration 3T0/2 at the output of the expander 25 pulses that corresponds to the first state of the outputs of the unit keys. This momentum will be transferred to the second inputs of the elements 47, 55 and 63 And in a logical block 3 generating control voltages for the unit keys. Since the first clock interval signals Ximatter 0-1-0, single voltage X2that acts on the second from the top (Fig.4) input logical unit 3 generating control voltages for the unit key is fed to the first inputs of the elements 55-62 And. resulting from a single voltage will appear at both inputs of the element 55 I. the output of this item, there will be a single voltage duration 3T0/2, which through the element 75 OR affects the key 89, and through the element 84 OR affects the key 98. These keys are opened, and the input of the amplitude-phase modulative level. These stresses are shown, respectively, in waveform u1and u2in Fig.18.

In the second clock time, i.e. at the end of the first parcels X1X2and X3the impulse TO. In the analyzer 1 status futuremusic stress this impulse acts on the 4th from the top (Fig.2) input and applied to the inputs of the elements 15, 17, 19 and 21, and the element 22 OR. Simultaneously, the voltage u1level +and arrives at the top (Fig.2) the analyzer input 1 status futuremusic voltages supplied to the first inputs of the elements 14 and 15 Acting On both inputs of the element 15 And is a positive voltage, the output appears a clock pulse, which is input to the expander 26 pulses, the output of which is formed a pulse 3T0/2. The appearance of the pulse at the output of the expander 26 pulses indicates the second state of the outputs of the block of keys that are marked in the line yiFig.18 (second clock). This pulse is fed to the second inputs of the elements 48, 56 and 64 And the logical block 3 generating control voltages for the unit keys. In this clock time at the outputs of the code Converter is formed code combination 1-0-0 (Fig.18). USA stress for a block of keys and affects the input elements 47-54 I. A single voltage will appear at both inputs of the element 48 And the output it appears a single voltage that through the elements 72 and 79, OR will reveal the keys 86 and 92. Through the key 86 to the input of the amplitude and phase modulator 6 receives a signal S2and through the key 92 to the input of the amplitude and phase modulator 7 signal S1. The shape of these stresses in the clock interval that begins when THE shown in Fig.16. This form is shown in the waveform u1and u2during the second clock interval. Continuing the same reasoning, for the next clock interval, obtain timing diagrams futuremusic voltages u1and u2arriving at the inputs of the amplitude and phase modulators 6 and 7 trekhchastichnogo modulator. Next usual work items 6-10 frequency modulator included in the restrictive part of the claims. The voltage u1influencing the modulating input of the first amplitude-phase modulator 6, modifies (or leaves unchanged) the amplitude and phase of the RF voltage at its output; depending on the polarity of the u1the phase of the output voltage of the modulator 6 can take the values 0 orand the amplitude and the amplitude of the phase modulator 7 and also changes its amplitude and phase; phase depending on the polarity of the u2can take values of/2 or 3/2. The addition of the output voltage amplitude and phase modulators in the adder 10 gives tracestate voltage at the output of the modulator. In the subsequent waveform of Fig.18 shows the phase changeand frequency fithe output voltage of the modulator. The output voltage for each package varies according to the harmonic law.

In this modulator, there are three interrelated factors that reduce the actual width of the spectrum of the modulated signal and the achievement of the technical result of the invention. First, the reduction of clock frequency modulated signal 1.5 times, while maintaining the speed of information transmission. Because the actual width of the spectrum is proportional to the clock frequency or inversely proportional to the duration of the parcels, the reduction of clock frequency, respectively, will reduce the occupied signal bandwidth. Secondly, reduction of 1.5 times the frequency deviation. Thirdly, the use of three frequencies manipulation; the third frequency is in the middle between the other two, who use the percentage manipulation enables the transfer of the three-position modulating signal, which is formed in the modulator at lower clock frequency.

The possibility of reducing the clock frequency of the modulated signal while maintaining the speed of information transfer is determined by the difference information capacity With signals from different base code M:

C=log2M (bits).

For binary (M=2), we get C=1, i.e., one information package contains 1 bit of information. For the ternary code (M=3) from the formula obtained=1,585, i.e., one ternary parcel contains 1,585 bit of information. Therefore, when transferring information ternary code can 1,585 times to decrease the transmission speed of parcels or 1,585 times to increase the duration of the parcels. The speed of information transmission remains unchanged.

Calculations show that the actual width of the spectrum trekhchastichnogo signal determined at a relative signal strength of 99%, 0.7· V (MMS - 1,18· V); the winning of bandwidth is 1.5 times. If the actual width of the signal spectrum to determine the relative signal strength of 90%, the payout will be 2 times, because in this case the real width of the spectrum trekhchastichnogo signal two times less compared with the signal of the MMC.

2. The modulator under item 1, characterized in that the analyzer status futuremusic stress includes two inverter eight elements And one element NO, three elements OR eight wheel pulses, and the input of the first inverter is connected with the first inputs of the first and second elements And is the first input of the analyzer status futuremusic voltages, the input of the second inverter is connected with perugini, the output of the first inverter is connected with the first inputs of the third and fourth elements And the output of the second inverter is connected with the first inputs of the seventh and eighth elements And the first input of the first element OR is connected with the second inputs of the first, third, fifth and seventh elements And is the third input of the analyzer status futuremusic voltage, the second input of the first element OR is connected with the second inputs of the second, fourth, sixth and eighth elements And is the fourth input of the analyzer status futuremusic voltage, the output of each of the elements And is connected to the corresponding input of the second element, OR both, in addition, the output of the first element And connected with the second input of the third element OR the output element And from the second to the eighth connected with the first inputs of dilators pulses, respectively, from the second to the eighth, the output of the first element OR is connected with the first input element is NOT present with the second inputs of all of the extenders pulses, the output of the second element OR is connected with the second input element is NOT present, the output element is NOT connected to the first input of the third element OR the output of which is connected to the first input of the first expander is th.

3. The modulator under item 1, characterized in that the power sequencing signals given shape and sequence of clock pulses includes a master oscillator, frequency dividers by two, four and six, the unit is preset, four differentiating circuit with a limit on the minimum, two driver sawtooth voltage, two driver voltage sine wave and one element OR the output of master oscillator is connected to the first input of the frequency divider by two, the output of the frequency divider by two is connected with the first inputs of the frequency dividers four and six, second input of the frequency divider by two is connected with the first output unit preset, the second inputs of the frequency dividers four and six are connected with the second output unit preset, the first output of the frequency divider of six connected with the input of the second driver of the sawtooth voltage and to the input of the first differential circuit with a limit on the minimum, the output of which is the output of the power sequencing signals given shape and sequence of clock pulses, the second output of the frequency divider of six connected with the input of the first fornerod which is the output of the power sequencing signals given shape and sequence of clock pulses, the first output of the frequency divider by four is connected with the input of the third differential circuit with a limit on the minimum, the second output of the frequency divider by four is connected with the input of the fourth differential circuit with a limit on the minimum, the output of the first driver of the sawtooth voltage is connected with the input of the first driver voltage sine wave output, two outputs which are the outputs of the power sequencing signals given shape and sequence of clock pulses, the output of the second shaper of the sawtooth voltage is connected with the input of the second driver voltage sine wave output, two outputs which are the outputs of the power sequencing signals given shape and sequence of clock pulses, the output of the third differential circuit is connected to the first input element OR the fourth output of the differentiating circuit is connected with the second input of the OR element and the output element OR is the output of the power sequencing signals given shape and sequence of clock pulses.

4. The modulator under item 1, characterized in that the logical block formation upprice the input elements And the first to the eighth are interconnected and are the first input of logic unit generating control voltages for a block of keys, the input elements And from the ninth to the sixteenth are interconnected and are the second input of logic unit generating control voltages for the unit key, the input elements And from the seventeenth to the twenty-fourth connected to each other and a third input of logic unit generating control voltages for the unit key, the second inputs of the first, ninth and seventeenth elements And connected to each other and are the fourth input of logic unit generating control voltages for the unit key, the second inputs of the second, tenth and eighteenth elements And connected to each other and are the fifth input of logic unit generating control voltages for a block of keys, the second inputs of the third, eleventh and nineteenth elements And connected to each other and are the sixth input of logic unit generating control voltages for the unit key, the second inputs of the fourth, twelfth and twentieth elements And connected to each other and are the seventh input of logic unit generating control voltages for the unit key, the second input of the fifth, thirteenth and twenty-first elements And are interconnected IDA sixth, the fourteenth and twenty-second elements And connected to each other and are the ninth input of logic unit generating control voltages for the unit key, the second input of the seventh, fifteenth and twenty-third elements And connected to each other and are the tenth input of logic unit generating control voltages for the unit key, the second input of the eighth, sixteenth and twenty-fourth elements And connected to each other and are eleventh input of logic unit generating control voltages for the unit key, the output of the first element And is connected to the inputs of the first and eighth elements OR the output of the second element And is connected to the inputs of the second and ninth elements OR the output of the third element And is connected to the inputs of the third and tenth elements OR the fourth output element And is connected to the inputs of the fourth and eleventh elements OR the output of the fifth element And is connected to the inputs of the fourth and ninth elements OR the output of the sixth element And is connected to the inputs of the third and eighth elements OR the output of the seventh element And is connected to the inputs of the second and eleventh elements OR the output of the eighth element And connects to Togo elements OR the tenth output element And is connected to the inputs of the fifth and fourteenth elements OR the output of the eleventh element And is connected to the inputs of the sixth and fourteenth elements OR the output of the twelfth element And is connected to the inputs of the sixth and fourteenth elements OR the output of the thirteenth element And is connected to the inputs of the seventh and the thirteenth element OR the output of the fourteenth element And is connected to the inputs of the seventh and the thirteenth element OR the output of the fifteenth element And is connected to the inputs of the seventh and twelfth items OR exit the sixteenth element And is connected to the inputs of the seventh and twelfth items OR the output of the seventeenth element And is connected to the inputs of the first and tenth elements OR output eighteenth element And is connected to the inputs of the second and eleventh elements OR exit the nineteenth element And is connected to the inputs of the third and eighth elements OR exit the twentieth element And is connected to the inputs of the fourth and ninth elements OR the output of the twenty-first element And is connected to the inputs of the second and ninth elements OR, the twenty-second output element And is connected to the inputs of the first and eighth elements OR exit the twenty the that element And is connected to the inputs of the third and tenth elements OR and the outputs of all elements OR are the outputs of logic unit generating control voltages for the block of keys.

5. The modulator under item 1, characterized in that the block of keys consists of fourteen analog switches, and the input pairs of the first and the eighth, the second and the ninth, third, and tenth, fourth, and eleventh, fifth and twelfth, sixth, and thirteenth, seventh and fourteenth analog switches are interconnected and are the inputs of the block of keys, the second inputs of all analog switches are inputs of the unit key outputs of the analog switches from the first to the seventh are interconnected and are the first output of the block keys the outputs of the analog switches with eight through fourteen are also connected to each other and are the second output block of keys.

6. The modulator under item 1, characterized in that the code Converter includes a shift register, three element, eight items And ten items OR seven extenders pulses and three element THERE, and the first input of the shift register is the first input of the code Converter, the second input of the shift register is connected to the first input of the first extender pulses and a second input preobrazovala extenders pulses and the third input of the code Converter, the output of the first pulse extender connects to the third input of the shift register and the fourth inputs of elements And the first output of the shift register is connected with the input of the first element and NOT to the inputs of the fifth, sixth, seventh and eighth elements And the second output of the shift register is connected with the input of the second element and to the inputs of the third, fourth, seventh and eighth elements, And the third output of the shift register is connected with the input of the third element and NOT to the inputs of the second, fourth, sixth and eighth elements And the output of the first element is NOT connected with the inputs of the first, second, the third and fourth elements And the output of the second element is NOT connected with the inputs of the first, second, fifth, and sixth elements And the output of the third element is NOT connected with the inputs of the first, third, fifth and seventh elements And the output of the first element And is connected to the inputs of the third and sixth elements OR the output of the second element And is connected to the inputs of the third and fifth elements OR the output of the third element And is connected to the inputs of the third and fourth elements, OR the fourth output element And is connected to the inputs of the second and sixth elements OR the output of the fifth element And is connected to the inputs vtoro the seventh output element And is connected to the inputs of the first and fifth elements OR the output of the eighth element And is connected to the inputs of the first and fourth elements OR output elements OR from the first to the sixth connected with the first inputs of dilators pulses respectively from the second to the seventh, the second inputs of the second, third, and fourth wheel pulses are interconnected and are the fourth input of the code Converter, the output of the second pulse extender connects to the inputs of the seventh and eighth elements OR the output of the third pulse extender connects to the inputs of the seventh and ninth elements OR the output of the fourth pulse extender connects to the inputs of the seventh and tenth elements OR the output of the fifth pulse extender is connected to the first input of the first element is NOT present, the output of the sixth pulse extender is connected with the first input of the second element is NOT present, the output of the seventh pulse extender is connected to the first input of the third element is NOT present, the output of the seventh element OR is connected with the second inputs of NO elements, the outputs of the first, second and third elements NOT connected with inputs respectively of the eighth, ninth and tenth elements OR outputs which are the outputs of the code Converter.



 

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