A method of manufacturing a planar power mos transistor
Usage: in the semiconductor power electronics. The technical result of the invention is to reduce the resistance of the conducting transistor, reducing the input capacitance, increase the breakdown voltage of the drain of the planar power MOS transistor, increasing the reproducibility of the device parameters. The inventive between stokovoj diffusion region and a gate region formed region with an insulating oxide (Locos) and the diffusion region in the substrate under the insulating oxide (Locos) of the same source type conductivity-creating together with an insulating oxide near the drain structure, fixing the length of the channel under the gate between the source and drain and the distance between signalground regions of source and drain regardless of the accuracy of combining layers of photomasks for forming the gate insulating oxide, the source and drain. 4 Il., 1 tab.
The present invention relates to semiconductor power electronics, semiconductor devices unipolar transistors with field effect created by the insulated gate.
To ensure a high breakdown voltage is TEI drain and source. In  proposed to justify strong area of flow, in the patent  proposed to introduce low-alloy region on the perimeter drain with pinch-resistive effect. In both of these cases, there is the difficulty of ensuring the accuracy of the alignment of the shutter with the edge of the pinch resistor region or highly dispersed area runoff. Area source camooweal shutter when using the polysilicon gate as a mask during ion doping source. The inaccuracy of alignment with the shutter drain region formed in independent shutter process, tends to increase the length of the channel, which increases the resistance of the conducting transistor, and leads to the variation of the main parameters of the power MOS transistor, the resistance of the open channel and the breakdown voltage-gated transistor.
Different ways of making power planar MOS transistors is described in many articles, books and patents. In the paper  described samozavestna manufacturing technology conventional, non-coercive instruments. In the paper  investigated the effect of substrate doping level on the breakdown voltage. In the paper  investigated the effect of applying samosobrannoy technology n the well-trodden areas largest breakdown voltage and conductivity of the planar power MOSFET transistors. In the paper  describes a method of manufacturing a device with grooves under the shutter. In articles [8, 9] considered in more detail the features of forming a local oxide in the structure of the power transistors and the effect of the size of the shutter on the parameters of the device. In the paper  considered the compatibility of the technology of power transistors with CMOS technology. In  are defined technological features create planar power MOS transistors when the displacement of the shutter relative to the source and drain. In  discussed in detail the modern ways of making power MOS transistors, depending on the scope of their application. In patents [13-19] are different ways of making patterns planar power MOS transistors to improve their parameters.
The closest analogue adopted us for the prototype is a high voltage device is a unipolar transistor with the field effect created by the insulated gate, and the manufacturing method . In this device compared to the previously known power MOS transistors with local areas of thick oxide (Locos) between drain and gate and low-alloy regions (pockets) near the source and drain are tiravanija runoff etched groove. Proposed in this patent the structure of the device and method of manufacturing increase the breakdown voltage, but low-alloy region (pockets) near the source and drain are formed in a single photolithographic operations, so resumeedge masks and care size pockets at diffusion justify impurities exclude the possibility of samoobladanie these pockets with the other areas of the structure of the source, drain and gate. Inaccurate alignment of the elements of the structure requires an increase in the sizes of the elements and does not allow to produce devices with a small channel length between source and drain.
The purpose of the invention is the improvement of the parameters of the planar power MOSFET transistors: the reduction of the resistance of the conducting transistor, reducing the input capacitance, increase the breakdown voltage of the drain of the planar power MOSFET through the creation of a method of manufacturing a structure with samoobladanie gate with the source and drain. Fully samozavestna technology can also improve the reproducibility of the device parameters.
The essence of the invention lies in the fact that is offered simultaneously with the formation of the pinch resistor area runoff (pocket) and an insulating oxide (Locos) above the pinch is m gap between the two panes of insulating oxide (Locos) camooweal with Locos, so resumeedge shutter and the gap between the source and the pinch resistor does not affect the location of the source and drain and the distance between them. Low-alloy region and source and drain under the insulating oxide (Locos) is formed using the hard mask silicon nitride, which also serves as a mask for growing Locos that provides samoobladanie source and drain with a gap. The area of source and drain, which are the contacts are formed on the other outer edges of the two areas of the Locos. When this input capacitance and the channel length is determined by the size of the gap between the fields of Locos and does not depend on the accuracy of alignment of the gate with a gap between lokasari. The position of the source and drain is determined by the position of the Locos, and the outer edge of the Locos fixes the distance between signalground regions of source and drain relative to the channel of the transistor, which is located in the gap between lokasari under the shutter. Thus, it provides a full samoobladanie all elements of the structure of the MOS transistor.
In Fig.1 shows a planar structure of a power MOS transistor with samoobladanie all areas in the form of the cross section, where the power of the planar MOS transistor is made of the ti (2) thin gate dielectric (4) and two insulating thick dielectrics (Locos) (5) and (6); the first conductive electrode and source (7) is located on the surface (2) and is in contact with stokovoj diffusion region (8) located in the substrate; a second conductive electrode flow (9) is also located on the surface (2) on stock diffusion region (10) located in the substrate; a third conductive gate electrode (11) is located on the surface of the control electrode (3); under the Locos (5) is formed in the substrate diffusion region (12) between stokovoj area (8) and the gate diffusion region (13), which is identical with the substrate conductivity type and which is due to the high concentration impurity prevents the closure space charges pn junctions of the source and drain; between regions (10) and (12) in the substrate under the Locos (6) is formed in the diffusion region (14) having the same stock diffusion region of a conductivity type and due to the small doping level with a pinch resistor effect, which increases the breakdown voltage of the drain is closed and transistor provides a high conductivity of the transistor is open.
A phased sequence of operations forming power planar MOS transistor with a full samoobladanie all elements Sneh higher areas of the device:
A) Forming diffusion regions of n-type conductivity additional area source (12) and the pinch resistor (14) through photomasks and using a mask of silicon nitride.
B) forming an insulating thick oxide (5) and (6) over (12) and (14). Insulating thick oxide (Locos) is grown by LOCOS method.
B) Ion doped gate region of the p-type conductivity (13), the region of n-type conductivity source (8) and n-type conductivity drain (10) through a separate photomasks and using an additional mask insulating oxide, limiting the area of doping.
G) Forming region gate dielectric (4) and gate electrode (3)
D) the Formation of the ohmic contact metal wiring(7), (9), (11) to the origin of (8) to the drain (10), bolt (3).
Planar power MOS transistor with a high operating voltage with full samoobladanie represents (see the topology of the transistor in Fig.4) ring structure with polysilicon gate octagonal shape (1); an insulating oxide (Locos) (2) is located on both sides of the gate and below the pinch resistor region and the source; inside the ring gate is p-n junction of the drain-substrate (3) with the contact in the centre of the figure; the outside ring of the Torah with a high operating voltage to ensure operation at high currents are composed of a large number, for example, from 5000 included in the separate parallel transistors shown in Fig.3.
The following is an example of the route of making high-speed planar power MOS transistor on silicon substrates.
The fixed distance between the two rings of the Locos formed in a single operation provides high fidelity channel length of MOS transistors independent of the displacement of the polysilicon gate relative to the Locos. When the channel length of 3 μm and inaccuracies of combining layers of polysilicon and Locos 0.5 µm proposed a method of manufacturing a planar power transistor allows to select the channel length of 2 μm and, thus, 1.5 times to reduce input capacitance and 1.5 times increase of the conductivity of the channel. The area of the drain and source samozavestna with the outer edges of the Locos that allows to reduce by 20% the dependence of the variation of the main parameters of the transistors of the resistance of the conducting transistor and the breakdown voltage-gated transistor from resumeware with Locos photomasks for forming drain and source.
Sources of information
1. H. Ballan, M. Declercq/ High voltage devices and circuits in standard CMOS te.G.Dili, K. G. Aubuchon, S. A. Thompson // IEEE Trans. Electron Devices, 1968, vol.ED-15, p.757-761.
4. The effect of substrate doping level on the breakdown voltage of MOS transistors/ Fujimoto.//Nikkei arcotronics," 1978, No. 5, PP 1-8.
5. D. Ueda, H. Tagagi, G. Kano, "An ultra-low on-resistance power MOSFET fabrication by using a fully self-alligned process", IEEE Trans. Electron Devices, vol.ED-34., p.926-930, 1987.
6. A Complementary Pair of Planar Power MOSFET's / T. Okabe, I. Yoshida, S. Ochi, S. Nishida, M. Nagata // IEEE Trans. Electron Devices, 1980, vol.ED-27, No. 2, p.334-339.
7. N. Fujishima, C. A. Salama, "A trench lateral power MOSFET using self-aligned trench bottom contact holes", "IEEE Trans. Electron Devices", vol.7, p.14.3.1, 1997.
8. News of higher educational institutions. Electronics. 2001, No. 3, pages 91-92/ Study the influence of the structure of the pinch resistor passive channel on the parameters of the MOSFETs smart power integrated circuits//M. A. Korolev, R. D. Tikhonov, A. C. Shvets.
9. M. A. Korolev, R. D. Tikhonov, A. C. Shvets/ investigation of the influence of the length of the gate over the active and passive channels on the parameters of the MOS transistors smart power integrated circuits// proceedings of higher educational institutions. Electronics, 2001, No. 5, pages 54-58.
10. E. M. S. Narayanan, G. A. J. Amaratunga, W. I. Milne, J. I. Humphrey, Q. Huang / Analysis of CMOS-Compatible Lateral Insulated Base Transistors// IEEE Trans. Electron Devices, vol.38, No. 7, p.1624-1632, 1991.
11. Blicher A. C./ Physics power bipolar and field traistaru// M.: Mir, 1986.
12. D. A. Grant and J. Gowar/ Power MOSFETs theory and a is t No. 0780907 A2.
16. International patent No. 97/41604.
17. International patent No. 98/10470.
18. The Japan Patent No. 2002057326 20020222.
19. The Japan Patent No. 2002057327 20020222.
20. U.S. patent No. 20010011752 A1 prototype.
A method of manufacturing a planar power MOS transistor, including the formation of diffusion regions of a source, a drain in the silicon substrate with an insulated gate dielectric, an insulating oxide (Locos) over the portion of low-alloy region of the flow, characterized in that the above part of the diffusion region of the source adjacent to the gate region is made of insulating oxide (Locos) simultaneously with the formation of insulating oxide (Locos) over low-alloy part of the diffusion region of the drain and separate ion doping portions of the diffusion regions of the drain and source adjacent to the gate region, is carried out to grow an insulating oxide (Locos), so that the channel length is determined by the distance between the inner edges of the panes of insulating oxide (Locos), and the distance between the heavily doped regions of source and drain is determined by the position of the outer edges of the regions of insulating oxide (Locos).
FIELD: electronic engineering.
SUBSTANCE: device provided with short channel for controlling electric current has semiconductor substrate to form channel. Doping level of channel changes extensively in vertical direction and keeps to constant values at longitudinal direction. Electrodes of gate, source and discharge channels are made onto semiconductor substrate in such a manner that length is equal or less than 100 nm. At least one of source and discharge electrodes form contact in shape of Schottky barrier. Method of producing MOS-transistor is described. Proposed device shows higher characteristics at lower cost. Reduction in parasitic bipolar influences results to lower chance of "latching" as well as to improved radiation resistance.
EFFECT: improved working parameters.
24 cl, 11 dwg
FIELD: microelectronics; integrated circuits built around silicon-on-sapphire structures.
SUBSTANCE: proposed method for manufacturing silicon-on-sapphire MIS transistor includes arrangement of silicon layer island on sapphire substrate, formation of transistor channel therein by doping silicon island with material corresponding to channel type, followed by production of gate insulator and gate, as well as source and drain regions; prior to doping silicon island with material corresponding to channel type part of silicon island is masked; mask is removed from part of silicon island of inherent polarity of conductivity upon doping its unmasked portion and producing gate insulator; in addition, part of gate is produced above part of silicon island of inherent polarity of conductivity; source region is produced in part of silicon island of inherent polarity of conductivity and drain region is produced in part of silicon island doped with material corresponding to channel type.
EFFECT: improved output characteristics of short-channel transistor at relatively great size of gate.
1 cl, 7 dwg
FIELD: integrated-circuit manufacture on silicon-on-insulator substrate; transistor structures of extremely minimized size for ultra-high-speed integrated circuits.
SUBSTANCE: proposed method for manufacturing self-aligning planar two-gate MOS transistor on SOI substrate includes production of work and insulator regions of two-gate transistor on wafer surface, modification of hidden oxide, formation of tunnel in hidden oxide, formation of polysilicon gate and drain-source regions; upon formation of insulator and work regions; supporting mask layer is deposited onto substrate surface and ports are opened to gate regions to conduct ionic doping of hidden oxide with fluorine through them; then doped part of oxide under silicon is removed by selective etching to form tunnel in hidden oxide whereupon silicon surface is oxidized in open regions above tunnel and gate is formed; port in supporting layer and tunnel are filled with conductive material, and gate-source regions are produced upon etching supporting layer using gate as mask. Transistor structure channel length is up to 10 nm.
EFFECT: reduced length of transistor structure channel.
2 cl, 1 dwg
SUBSTANCE: invention relates to semiconductor technology. The method of making power insulated-gate field-effect transistors involves making a protective coating with a top layer of silicon nitride on the face of the initial silicon nn+ or pp+ - substrate, opening windows in the protective coating, making channel regions of transistor cells in the high-resistivity layer of the substrate and heavily-doped by-pass layers and source regions inside the channel regions using ion implantation of doping impurities into the substrate through windows in the protective coating and subsequent diffusion distribution of implanted impurities. When making by-pass layers, the doping mixture is implanted into the substrate through windows in the protective coating without using additional masking layers. After diffusion redistribution of implanted impurities in by-pass layers on the entire perimetre of windows in the protective coating, selective underetching of lateral ends of the protective coating under silicon nitride is done. The silicon nitride layer is then removed from the entire face of the substrate and source regions of the transistor cells are formed through implantation of doping impurities into the substrate through windows in the protective coating.
EFFECT: invention is aimed at increasing avalanche break down energy, resistance to effect of ionising radiation and functional capabilities of silicon power transistors.
5 dwg, 1 tbl
FIELD: physics; semiconductors.
SUBSTANCE: invention concerns electronic semiconductor engineering. Essence of the invention consists in the manufacturing method of SHF powerful field LDMOS-transistors, including forming of a primary sheeting on a face sheet of an initial silicon body with top high-resistance and bottom high-alloy layers of the first type of conductance, opening of windows in a primary sheeting, sub-alloying of the revealed portions of silicon an impurity of the first type of conductance, cultivation of a thick field dielectric material on the sub-alloying silicon sites in windows of a primary sheeting thermal oxidising of silicon, creation in a high-resistance layer of a substrate in intervals between a thick field dielectric material of elementary transistor meshes with through diffused gate-source junctions generated by means of introduction of a dopant impurity of the first type of conductance in a substrate through windows preliminary opened in a sheeting and its subsequent diffused redistribution, forming of connecting busbars and contact islands of a drain and shutter of transistor structure on a thick field dielectric material on a face sheet of a substrate and the general source terminal of transistor structure on its back side, before silicon sub-alloying and cultivation of a thick field dielectric material in windows of a primary sheeting a high-resistance layer of a substrate is underetched on the depth equal 0.48 - 0.56 of thickness of a field dielectric material, and before dopant impurity introduction in the formed source crosspieces of transistor meshes in a high-resistance layer of a substrate in sheeting windows etch a channel with inclined lateral walls and a flat bottom depth of 1.5 - 2.6 microns.
EFFECT: improvement of electric parametres of SHF powerful silicon LDMOS transistors and increase of percentage output of the given products.
5 dwg, 2 tbl
SUBSTANCE: in a field-effect transistor which includes an oxide film as a semiconductor layer, the oxide film has a channel part, a source part and a drain part, and concentration of one of hydrogen or deuterium in the source part and in the drain part exceeds that in the channel part.
EFFECT: invention enables to establish connection between the conducting channel of a transistor and each of sources and drain electrodes, thereby reducing change in parameters of the transistor.
9 cl, 13 dwg, 6 ex
SUBSTANCE: in manufacturing method of semiconductor device, which involves processes of ion implantation and formation of active areas of instrument on silicon substrate, after formation of active areas there created is hidden p-layer under channel of instrument by alloying of substrate with Be ions with energy of 125-175 keV, dose of (2-5)·1012 cm-2 and with further annealing at 650-750°C during 20-30 minutes and H2 atmosphere.
EFFECT: reducing leakage current values in semiconductor devices, providing processibility, improving parameters, reliability and increasing percentage yield.
SUBSTANCE: in the method for manufacturing of a semiconductor device including formation of a semiconductor substrate of the first type of conductivity, a gate electrode formed above a subgate dielectric and separated with interlayer and side insulation from a metal source electrode (emitter), a channel area of the second conductivity type and a source area of the first conductivity type, formed by serial ion alloying of admixtures into windows of the specified shape in the gate electrode, and the metal source electrode, a subgate dielectric is developed, as well as a gate electrode and interlayer insulation above the gate electrode in a single photplithographic process by plasma-chemical feeble anisotropic etching with ratio of vertical and horizontal components of etching speed making (3÷5)/1.
EFFECT: reduced resistance in open condition without increasing dimensions of a crystal and improved efficiency without deterioration of other characteristics.
11 cl, 4 dwg
SUBSTANCE: manufacturing method of SHF LDMOS transistors includes growth of thick field dielectric at surface of high-ohmic epitaxial p- -layer of source silicone p-p+-substrate at periphery of transistor configurations, formation of source p+-junctions and p-wells of transistor cells in epitaxial p- -layer of substrate not covered with field dielectric, growth of gate dielectric and formation of polysilicone electrodes of transistor cells gate in the form of narrow lengthwise teeth of rectangular section with close adjoining tapped contact pads from source side over p-wells, creation of high-alloy n+-areas of sink, source and low-alloy n-area of transistor cells by introduction and further diffusion redistribution of donor dopant using gate electrodes as protective mask, formation of metal electrodes of sinking, source, screens and buses shunting gate electrodes of transistor cells through tapped contact pads at substrate face and common metal source electrode of transistor configuration at backside, the first degree of low-alloy multistage n-area of transistor cell source is formed after formation of source p+-junctions by introduction of donor dopant to epitaxial p--layer of substrate without usage of protective masks, p-wells, sink and source areas of transistor cells are created with use of additional dielectric protective mask identical in configuration and location of lengthwise teeth of polysilicone gate electrode without tapped contact pads adjoining to them, simultaneously with p-wells similar areas are formed at edges of low-alloy n-area of transistor cells sink and gate electrodes with tapped contact pads adjoining to teeth are formed after removal of additional dielectric protective mask and subsequent growth of gate dielectric, at that width of polysilicone gate electrode teeth are selected so that it exceeds length of transistor cell induced channel per overlay error value.
EFFECT: improvement in electric parameters of powerful silicone generating SHF LDMOS transistors, increase of their resistance to ionising radiation exposure and increase of production output in percents.
SUBSTANCE: transistor based on a semiconductor compound comprises a semiconductor plate, a channel and a contact layers, ohmic contacts of a source and a drain, made on the basis of a thin-film compound of Ge and Cu, and a gate, where thin films of barrier-forming metal, a diffusion barrier and a conductor are installed in layers on a semiconductor plate. The gate conductor material is a thin-film compound of Ge and Cu with thickness of 10-1,000 nm, with mass content of Ge in the range of 20-45%.
EFFECT: higher thermal stability of gate parameters, lower value of reduced contact resistance of ohmic contacts of a source and a drain.
6 cl, 6 dwg, 1 tbl