Device for the users ' access to sections of text documents

 

The invention relates to computing. Its use allows to obtain a technical result in increasing the reliability of the users ' access to sections of text documents. The device contains three register, a memory unit, synchronizer, two group elements And group elements OR the trigger element And three-element and four OR delay elements. The technical result is achieved that the device entered the selector sections of text documents, the address selector sections, the shift register, two counters, a comparator, two elements OR element And. a user ID is entered in the first register and the identification code of the section of the document in the second case. 4 Il.

The invention relates to computing, and in particular to a device for restricting access to sections of text documents.

The known device that could be used to solve the task [1, 2].

The first known device has a Central processing unit connected to the logical processing unit and the control outputs are connected to the memory blocks the current of this device is the low reliability of access of different users to the editable information in sections one and the same document.

Known and other device containing a Central processing unit (CPU), a memory unit, the control inputs of which are connected to the outputs of the CPU, and outputs connected to the data processing unit, logic gates AND, OR and interface unit [2].

The last of the above technical solutions closest to being described.

Its disadvantage is that it cannot provide reliable access of users to different sections editable text documents. The latter circumstance is due to the fact that the constructive implementation of this device does not provide for the consolidation of user IDs for those sections editable text documents, which are allocated to the appropriate users for editing.

The purpose of the invention is to enhance reliability of the users ' access to sections of text documents by assigning user IDs for those sections of text documents, which are entrusted to them for editing.

This objective is achieved in that the device containing the first register, the information input of which is the first information input of the s entrance of which is a second information input device, and the clock input of the second clock input unit, a memory unit, the information input of which is connected to the outputs of the respective elements OR group of address inputs of the memory block connected to the corresponding outputs of the third register and the outputs of the memory block is connected to one inputs of the respective elements And the first group, the outputs of which are information output devices, the second group of items, some inputs which are information input device groups, and outputs connected to the inputs of the respective elements OR groups, synchronizer, first and second control inputs of which are the first and second control inputs of the device, the trigger, the single output of which is connected with one input of the first element And the other input of which is connected to shift the output of the synchronizer, the first, second and third elements OR, the first, second, third and fourth delay elements, put the selector sections of text documents, an information input connected to the output of the first register, a clock input connected to the first pulsing the output of the synchronizer, and control outputs connected to inputs of respective elements stored the register, the information output is connected to the information input of the third register, the clock output is connected to the clock input of the third register, the shift register, the information input of which is connected to the information output of the selector sections of text documents, word clock input is connected to the synchronizing output of the selector sections of text documents, and the control input of the shift is connected to the output of the first element And the first counter, a counting input connected to the output of the first element And the output of the transfer of the first counter is connected to one input of the first element OR another input connected to the clock output selector sections of text documents, and the output connected to the input of the first delay element, a second counter, a counting input connected to the output of the transfer of the first counter and an output connected to one input of the second OR element, another input connected to the output of the transfer of the first counter, and the output connected to the set input of the trigger comparator, information inputs which are connected to the outputs of the second register and the shift register clock input connected to the output of the first delay element, the first output comp is and, to the third input of the second element OR to one input of the third element OR another input connected to the second pulsing the output of the synchronizer, and the output connected to the clock input of address selector sections, which synchronizes the output of which is connected to the input of the second delay element, the output of which is connected to the adjusting input of the shift register, the second And gate, one input of which is connected to first control the output of the synchronizer, the other connected to the output of the second delay element, and the output connected to the input of the third delay element, with the control input of the read memory block and to the corresponding inputs of elements And the first group, the third element And one input of which is connected to the second control output of the synchronizer, the other connected to the output of the second delay element, and the output connected to the control input record block of memory and to the input of the fourth delay element, the fourth element OR the input of which is connected to the outputs of the third and fourth delay elements, and the output is connected with the installation of the inputs of the first, second and third registers, with the first installation clock input connected to the output of the third delay element, and Elenia illustrated by drawings, where in Fig.1 shows a block diagram of the device of Fig.2 and 3 shows examples of specific structural embodiment of the selector sections of text documents and the address selector sections, respectively, in Fig.4 shows an example of a specific structural embodiment of the synchronizer.

The device (Fig.1) contains the first 1, second 2, third 3 registers, the shift register 4, a comparator 5, the first 6 and second 7 counters, memory unit 8, a selector 9 sections of text documents, the selector 10 addresses sections, the synchronizer 11, the first 12 and second 13 and 14 third elements, the first 15, 16, 17 and second 18, 19, 20 group members, a group of 21 elements OR, the trigger 22, the first 23 and second 24, third 25, 26 fourth elements OR the first 27, the second 28, third 29 and 30 fourth delay elements.

In Fig.1 also shows the first 31 and second 32 information input device, the first 33 and second 34 clock inputs of the device, the first 35 and second 36 control inputs of the device, group 37, 38, 39 information input device, the signal 40 output device and group 41, 42, 43 information output device.

In addition, the synchronizer 11 contains the first 44 and second 45 installation inputs, shear output 46, the first 47 and second 48 pulsing in the information 51 and the clock 52 inputs, control 53 outputs information output 54 and the clock 55 outputs respectively. The selector 10 addresses sections contains information input 56, the clock input 57, the information output 58 and the clock output is 59.

The selector 9 sections of text documents (Fig.2) contains the decoder 60, the elements 61-63 And the memory unit 64, made in the form of a persistent storage device (ROM) and a delay element 65.

The selector 10 addresses sections (Fig.3) contains the decoder 66, the elements 67-69 And the memory block 70, made in the form of a persistent storage device (ROM) and a delay element 71.

Synchronizer 11 (Fig.4) contains triggers 72, 73, generator 74 pulses and the elements 75, 76 And. Generator 74 has two outputs. To the first output 46 of the generator 74 generates shift pulses with a specified frequency, and the second output is pulsing pulses obtained by dividing the frequency of the shift pulses.

All nodes and elements of the device are made on the standard of potentially switching elements.

The device operates as follows.

In the information network group of users working on editing different sections of the same document. A fundamental requirement for a t is to those sections of text documents, he was instructed to edit. However, access to view other sections of this document, however, these users must be blocked.

In the process in case 1 with the information of the entrance 31 to the clock input 33 enters a user ID. In case 2 from the information input 32 on the clock input 34 receives the code section of a text document with which the user intends to work. Then through the inlet 35 synchronizer 11 on a single input trigger 72 receives the request signal at the beginning of the work. The trigger 72 high potential with a single exit opens the element 75 And through which the first clock pulse generator 74 is supplied to the output 47 of the synchronizer 11 and then to the clock input 52 of the selector 9.

The decoder 60 of the selector 9 code received at its input 51 from the outputs of the register 1, issue on one of its outputs a high potential, and opens one of the elements I.

For definiteness we will assume that this element is the element 61 I. In this case, the pulse from the input 52 of the selector 9 passes through this element to the input of the reading corresponding to the fixed memory ROM 64 and reads its contents through the outlet 54 to the input of the register 4 with OSISA in register 3.

The contents of the fixed cell ROM is a set of consecutive numbers of the sections of the text document, represented as a binary-decimal code, the access to edit the content which is permitted to the user identification code. The first of the codes presented in the upper bits of the shift register 4 is applied to one input of the comparator 5, the other input is from the output of the register 2 is supplied code section number requested for editing and is also represented in binary-decimal code.

To synchronize the process of comparing codes in the comparator 5 is used, the pulse from the output 55 of the selector 9, which passes through the element 23 OR delay element 27 at the time of entering code in the register 4, and then supplied to the clock input of the comparator 5.

If the codes of the register 2 and the high-order bits of register 4 match, then the output a of the comparator 5, a signal is generated which passes through the element 25 OR to the input 57 of the selector 10.

To this point in time code output register 2 decoder 66 of the selector 10 at one of its outputs has issued a high potential and opened one of the elements 67-69 And. For definiteness, suppose that element e is the characteristic of its contents through the outlet 58 to the input of register 3, where the code is placed by a pulse, the delayed element 71 at the time of reading.

In fixed-cell in the ROM 70 stores the code of the address of the text section of the document that the user invokes to edit. After entering the code addresses section in case 4, this code is supplied to the address input of the memory unit 8, and the pulse from the output 59 of the selector 10, the detainee element 28 at the time of enrollment code in register 3, comes first, setup the input of the shift register 4, and secondly, through the element 13 And open at a second input a high potential with a zero exit 49 trigger 73 synchronizer 11, to the input of the reading unit 8 memory.

From the output of the unit 8, the contents of the corresponding section of the text document is fed through the corresponding group of items 15-17 And at the user's workplace. Given that in our example, the high potential of the decoder was on the input element 61 And the selector 9, the transfer of the content will be carried out through the group 15 elements And are also connected with the output of the decoder 60 of the selector 9. To this end, the pulse reading is fed to the inputs of the elements 15 And rewriting the contents of the partition of the memory block to the output 41.

Cycles to the memory unit 8 ends the and the installation log trigger 72. The trigger 72 is returned to its original state and blocks the passage of clock pulses to the output 47. In addition, the pulse input element 29 delay passes through the element 26 OR on the installation inputs of the registers 1, 2, 3.

After editing the relevant section of the text document in case 1 the newly entered user ID, in case 2 - the code section, but now signal the end of the editing is fed through the inlet 36 to the single input trigger 73, which is a high potential opens the element 76 And the clock pulse from the output of synchronizer 48 11 through the element 25 and is fed to the input 57 of the selector 10. Work selectors 9, 10, and case 4 is similar to the process described above. The difference lies in the fact that in this case, the pulse from the output of the delay element 28 passes through the element 13 And, as previously, and through the element 14 And to the control input of the recording unit 8.

In accordance with an example to this point in time, the selector 9 high potential open items 18 And groups. As a result of this information input device 37 through the elements 18 And the elements 21 OR will be connected to the information input unit 8 memory.

The output signal from Eli. After that, the same impulse records detained by the delay element 30 at the time of recording, first, through the inlet 45 of the synchronizer trigger 73 is set in the initial state, blocking further passage of pulses from the output of the element 76 And, secondly, through the element 26 OR are in the initial state of the registers 1, 2 and 3.

If the codes of the register 2 and the high-order bits of register 4 does not match, then a signal is generated at the output of the comparator, which receives a single input trigger 22, setting it in one state. High capacity single output trigger 22 opens one input element 12 And at the other input of which receives pulses shift generator 74 synchronizer 11 through the outlet 46.

The shift pulses fed to the input of shift register 4 and the counting input of the counter 6 which counts their number. Bit counter 6 is chosen according to the dimension of the binary-decimal representation of a section numbering in text documents, so that after counting the total number of shifts in which one partition number in the upper bits of the shift register is replaced by the following in order, the output transfer counter 6 receives the impulse. This impulse is, first, h is ha through the element 12 And to the inputs of register 4 and the counter 6, secondly, he entered the counting input of the counter 7 sections and, thirdly, through the element 23 OR the pulse is delayed by element 27 on the end time of the shift register 4 and is supplied to the clock input of the comparator 5.

If the compared codes match, then the output a of the comparator 5 receives the impulse and the process is repeated in the manner described above with matching codes.

If the code section number register 2 and the next code in the upper bits of the register 4 again does not match, then the output of comparator 5, a signal occurs. Last again sets the trigger 22 in one state, thereby providing a receipt to the inputs of the shift register 4 and the counter 6 of the shift pulses from the generator 74, and further the process of comparing codes again repeated.

If requested by the user section of the text document is not in the number of partitions to which he admitted, after comparing the code of the register 2 with all codes listed in the register 4, the counter 7 counting cycles comparison will fix the lack of match codes the issuance of the momentum transfer at its output. This impulse is, firstly, available at the output 40 of the device as a signal of unauthorized access to the d input of the trigger 22, returning it to its original state.

Thus, unlike known devices, this device provides reliable separation of user access to the editable sections within the same text document.

Sources of information

1. U.S. patent No. 5144556, CL G 06 F 15/38, 15/40, public. 1992

2. U.S. patent No. 5129083, CL G 06 F 12/00, 15/40, public. 1992 (prototype).

Claims

Device for the users ' access to sections of text documents containing the first register, the information input of which is the first information input device, and the clock input of the first synchronizing input of the second register, the information input of which is the second information input device, and the clock input of the second clock input unit, a memory unit, the information input of which is connected to the outputs of the respective elements OR group of address inputs of the memory block connected to the corresponding outputs of the third register and the outputs of the memory block is connected to one inputs of the respective elements And the first group, the outputs of which are informational outputs of the mouth of the outputs connected to the inputs of the respective elements OR groups, synchronizer, first and second control inputs of which are the first and second control inputs of the device, the trigger unit the output of which is connected with one input of the first element And the other input of which is connected to shift the output of the synchronizer, the first, second and third elements OR, the first, second, third and fourth delay elements, characterized in that it contains a selector sections of text documents, an information input connected to the output of the first register, a clock input connected to the first pulsing the output of the synchronizer, and control outputs connected to inputs of the respective elements And the first and second groups, the address selector sections, an information input connected to the output of the second register, data output is connected to the information input of the third register, the clock output is connected to the clock input of the third register, the shift register, the information input of which is connected to the information output of the selector sections of text documents, word clock input is connected to the synchronizing output of the selector sections of text documents, and the control input of the shift is connected to the output of the first EO counter is connected to one input of the first element OR the other input of which is connected to the synchronizing output of the selector sections of text documents, and the output connected to the input of the first delay element, a second counter, a counting input connected to the output of the transfer of the first counter and an output connected to one input of the second OR element, another input connected to the output of the transfer of the first counter, and the output connected to the set input of the trigger comparator, information inputs which are connected to the outputs of the second register and the shift register clock input connected to the output of the first delay element, the first output of the comparator is connected to a single input trigger and a second output connected to the set input of the second counter, to the third input of the second element OR to one input of the third element OR another input connected to the second pulsing the output of the synchronizer, and the output connected to the clock input of address selector sections, which synchronizes the output of which is connected to the input of the second delay element, the output of which is connected to the adjusting input of the shift register, the second And gate, one input of which is connected to first control the output of the synchronizer, the other connected to the output of VTEM memory block and to the corresponding inputs of elements And the first group, the third element And one input of which is connected to the second control output of the synchronizer, the other connected to the output of the second delay element, and the output connected to the control input record block of memory and to the input of the fourth delay element, the fourth element OR the input of which is connected to the outputs of the third and fourth delay elements, and the output is connected with the installation of the inputs of the first, second and third registers, with the first installation clock input connected to the output of the third delay element and the second mounting a clock input connected to the output of the fourth delay element.



 

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Processor // 2248608

FIELD: computers, data protection.

SUBSTANCE: processor has bus interface device, device for selection/decoding of commands, device for dispatching/execution, program string decoding device, which string is selected from program and loaded in first levels command cash, which contains a set of N two-input elements XOR, keys memory, storing different N-bit decoding keys.

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FIELD: technologies for authentication of information.

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EFFECT: higher reliability.

6 cl, 12 dwg

FIELD: computers.

SUBSTANCE: method includes, on basis of contents of central processor registers, received after processor performs some sort of command, by means of mathematical logical operation, forming certain finite control sum and storing it in memory, and on basis of contents of registers, received before start of execution by said processor of directly next command, certain starting checksum is formed, while if starting checksum mismatches finite checksum, error message is generated, which can be followed by halting of processor operation or blocking of chip board with its removal from circulation.

EFFECT: higher reliability.

2 cl, 2 dwg

FIELD: copy protection.

SUBSTANCE: system has content distribution block, multiple recording and playback devices for digital data, calculations processing block, meant to perform communications with recording and playback devices and performing calculations processing for transferring license payments.

EFFECT: higher reliability of copy protection.

5 cl, 55 dwg

FIELD: electronics.

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EFFECT: higher reliability of protection.

2 cl, 7 dwg

FIELD: microprocessors.

SUBSTANCE: device has central processing devices, including first cryptographic block, at least one peripheral block, including second cryptographic block, device also has data bus, random numbers generator, conductor for supplying clock signal, conductor for providing random numbers signal, set of logical communication elements, while each cryptographic block has register of displacement with check connection.

EFFECT: higher level of unsanctioned access protection.

7 cl, 1 dwg

FIELD: digital memory technologies.

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EFFECT: higher efficiency.

3 cl, 23 dwg

FIELD: computer science.

SUBSTANCE: method includes protective mathematical conversion of service data of network frame prior to transfer to environment for transfer of a LAN. To said protective conversion the data is subjected, which is contained in headers of network frames of channel level, and also in headers of all encapsulated network packets and segments. As a result the very possibility of interception is prevented.

EFFECT: higher efficiency.

7 cl, 2 dwg

FIELD: data carriers.

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EFFECT: higher reliability, higher efficiency.

4 cl, 46 dwg

FIELD: data carriers.

SUBSTANCE: device has calculating, reserving and recording modules. Each variant of semiconductor memory card contains area for recording user data for controlling volume and area for recording user data. On carrier method for computer initialization is recorded, including calculation of size of volume control information, reserving areas and recording therein of control information for volume and user data, recording main boot record and sectors table in first section of first area, skipping preset number of sectors, recording information of boot sector of section, file allocation table and root directory element to following sectors.

EFFECT: higher efficiency.

5 cl, 59 dwg

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