The distribution management system data in the information network of gas "vybory"

 

The invention relates to computing, and in particular to control systems for the distribution of data in the information network of the State automated system “Elections”. The technical result is to increase the reliability of data protection in the system by eliminating the possibility of unauthorized access of users to distribute data. The unit contains registers, memory blocks, and selectors addresses, Comparators, flip-flops, elements And the elements OR the decoder, the delay elements. 2 Il., table 2.

The invention relates to computing, and in particular to systems for managing the distribution of data in the information network of the State automated system (GUS) “Election”.

Feature solved the technical problem lies in the fact that in each election management system data distribution is to perform the functions defined by the form of the election campaign (the referendum, elections for the position, the election of members, feedback and role of Election commissions in these campaigns. The system for managing the distribution of data in the information network of gas “Vybory” shall provide automatic generalization of certain types of information, coming from a lower-level election commissions. All these requirements must be implemented in the subsystem automation of the electoral process.

For definiteness we will consider a system of distributing data in a data network of gas “Vybory on the main system object that represents the Central election Commission (CEC), and as objects - sources of information - objects of election commissions of subjects of the Russian Federation (subject election Commission).

Known systems that could be used to solve the task (1, 2).

The first of the known systems contains blocks receiving and storing data, connected to the control blocks and data blocks search and selection, connected to the blocks of the data storage and display, the clock inputs are connected to outputs of the control unit (1).

A significant disadvantage of this system is that you cannot solve the problem of updating data stored in memory in the form of relevant documents simultaneously with the solution of the issue of the content of these documents to users in real time.

Famous another formation system objects with different object pointers alderase CPU and memory blocks, connected to the Central processor, the processing blocks of data containing the registers, triggers, and elements AND, OR, and blocks of data output connected to the memory blocks, the Central processing unit and the processing units of the data structures (2).

The last of the above technical solutions closest to being described.

Its disadvantage is the low reliability of data protection from unauthorized user access, which leads to the leakage of confidential information, operating in the distribution management system data.

The purpose of the invention is to enhance reliability of data protection by eliminating unauthorized user access to documents, functioning in the system.

This objective is achieved in that in the known system, containing the first register, the information input of which is the first information input system clock input connected to the output of the first element And one input of which is the first clock input of the system and the corresponding output of the first register is connected to the information input of the first memory block, the first selector address information whose input is connected to the corresponding output of the first is vtorogo connected with the information output of the first selector address, synchronizing the output of which is connected to the clock input of the second register, the elements OR the first group, one input of which is connected with the corresponding output of the second register, other inputs connected to the outputs of the respective elements And the first group, one of the inputs of which are the first address input of the system, and the outputs of the elements OR of the first group are connected to the address input of the first memory block, the control input record which is connected to the output of the first delay element, which is the first clock of the system output, control input reading is connected to the output of the second element, And the output of the first memory block is the first information output system, the second delay element, the input connected to the output of the first delay element, and the output connected to the set inputs of the first and second registers and to the input of the third delay element, the output of which is connected with one input of the second element And whose output is connected to the input of the fourth delay element and to the other inputs of elements And the first group, the third register, the information inputs which are the second information input of the system, and the clock input is the second sync the om system, installation input connected to the output of the fourth delay element, a direct output of the first flip-flop connected to another input of the second item, and the inverted output connected to another input of the first element And the fifth delay element, the output of which is connected to the input of the sixth delay element, the element OR the output of which is connected to the set input of the second trigger and the third register, the third element And one input connected to the inverse output of the second trigger, and the other is the fourth synchronizing input of the system, the second memory block, the address input connected to the outputs of the elements OR the second group, information entry is the third information input system and the output is connected to one input elements And block elements, the outputs of which are groups of information system outputs, entered the second selector address information input connected to one output of the third register, a clock input connected to the second clock input of the system, the fourth register, the information input connected to the information output of the second selector address, which synchronizes the output of which is connected to the clock input chetvertiti which is connected to the other output of the third register and to the first output of the fourth register, the clock input of the first comparator is connected to the synchronizing output of the second selector addresses, and one output connected to one input element OR the second comparator, the information input of which is also connected to another output of the third register and a second output of the fourth register, a clock input connected to another output of the first comparator, the first output of the second comparator is connected to another input of the OR element and the second output is the second synchronizing system output, the decoder, the input of which is connected with the third output of the fourth register elements And the second group, one input of which is connected to the fourth output of the fourth register, other inputs connected to the output of the fifth delay element and direct the second trigger, and outputs connected to one input elements OR the second group, the elements And the third group, some inputs which are the second address input of the system, the other is connected to the inverse output of the second trigger and the output of the third element, And outputs connected to the other input elements OR the second group, the seventh delay element, the input connected to the output of the third element, And an output connected to the input umenta delay and with other input elements And block elements third inputs are connected to the corresponding outputs of the decoder, and the elements of the fourth group, one input of which is connected to another output of the third register, other inputs connected to the second output of the second comparator, and outputs the second information output system, while the second output of the second comparator is connected to the input of the fifth delay element with a single input of the second trigger.

The invention is illustrated by drawings, where Fig.1 shows a block diagram of the device, and Fig.2 is a block diagram of the address selector.

System (Fig.1) contains the first 1, second 2, third 3 and fourth 4 registers, the first 5 and second 6 selectors addresses, the first 7 and second 8 memory blocks, the first 9 and second 10 triggers, the first 11, second 12 and third 13 elements, And the first 14 and second 15 and third 16 member groups And unit groups 17, 18 and 19 elements And the fourth 20 the group of items, the first 21 and second 22 groups of elements OR first 23 and second Comparators 24, a decoder 25, the element 26 OR the first 27 and second 28, 29 third, fourth, 30, 31 fifth, sixth, 32 and 33 seventh delay elements.

In Fig.1 also shows the first 35 and second 36 and 37 third information input system, the first 38 and second 39 address inputs of the system, PE is, uhodi 45-1, 45-2, 45-3 group of information outputs of the system, the first 46 and second 47 synchronizing the system outputs, and 48 second information output system.

The selector 5, 6 address (Fig.2) contains the decoder 50, the first 51, second 52, and third 53 elements And block memory 54, made in the form of a persistent storage device, the element 55 OR the first 56 and second 57 delay elements.

In Fig.2 also shows information 58 and 59 clock inputs of the selector addresses and information 60 and the clock 61 outputs of the selector address.

All nodes and elements of the system are made on the standard of potentially switching elements.

The system works as follows.

On the information input 35 system transmission path of data sequentially received messages (codogram) of Election commissions of subjects of the Russian Federation on the voting of the voters in the respective subjects of the Russian Federation.

Codogram contain indicative and informative part.

Structure codogram has the following form:

The indicative part of the message contains the ID of the subject election Commission, sent codogram, and the information part contains information about the number of voters in this region who participated in oneirogen pulse input 40, which goes to the sync input of the register 1 through the element 11 And open at the second input high potential with inverted output of the trigger 9 mode, which in its original state.

The decoder 50 of the selector 5 determines the sign of the received messages, throwing on one of its outputs a high potential. For definiteness, suppose that a high potential is received at one input element 51 And.

In parallel, the clock pulse from the output element 11 And is fed to the input 59 of the selector 5, which is delayed by element 56 during operation of the decoder 50, and then queries the state of the elements 51-53 I. Considering the fact that open on one input will be only element 51 And then passing this element And the sync pulse arrives, firstly, to the input of the read fixed memory permanent storage device 54, which stores the starting address of the memory areas of the block 7, where it is necessary to record information, adopted by the register 1. Secondly, the same impulse to read the output of the element 55 OR delayed by the delay element 57 at the time of reading the contents of a fixed cell ROM and then supplied to the clock input of the register 2, the locking code of the address area PA is no input to the recording unit 7, recording information part of codogram messages from the information output of the register 1 to the address output register 2 through the group of items 21 and is fed to the address input of the memory block 7.

The output 44 of the memory block 7 is connected to the server information system (not shown), which according to the interrupt signal from the output 46 after another adding the contents of register 1 in block 7, sets the address inputs 38 address zone the memory, whence must be one of the few who came patterns, and outputs receive data on a single input trigger 9. The trigger 9, moving in one state, closes the element 11 And the reception of codogram server and opens the element 12 I.

The interrupt signal to the server from the output element 27 is delayed by element 28 at the time of preparing the server to accept the data and then enters the installation inputs of registers 1 and 2, returning to their original state, and then after a delay element 29 at the time of installation of the registers 1, 2 in the initial state goes to poll the status of the element 12 And. Since this point in time, the element 12 And is opened, the pulse from the output of the element 12 And through the elements 14 And the groups and items 21 OR group will set the address inputs of the block 7 agreementon delay of 30 at the time of reading data, the trigger 9 is returned to its original state, and the system is again ready to receive the next codogram.

Read from unit 7 the data used by the server as input to the functional tasks to be solved in the information system client-server. By addressing these problems results in the form of appropriate certificates issued by the server to the information input device 37 and further information on the input of the memory unit 8.

Officials of the electoral Commission (let's call them users of the system), tracking the progress of the electoral process, can get processed by the server, the data only within the limits of their powers.

For this purpose, each of them on your remote control (not shown) dials ID code of the help, which he would like to get. ID code reference input 36 is supplied to a part of the information inputs of register 3, in another part of the information input of which is constantly applied (constructively, QR) code, user ID, which is structurally hidden from the user, and the latter do not have access to it.

After the user presses a key Issue, to the input 42 receives the clock pulse, which enters into the variable frequent erator 50 of the selector 6 decrypts the ID code of the user, throwing on one of its outputs a high potential. For definiteness, suppose that a high potential is received at one input element 52 And. in Parallel, the clock pulse from the input 42 is fed to the input 59 of the selector 6, which is delayed by element 56 during operation of the decoder 50, and then queries the state of the elements 51-53 I. Considering the fact that open on one input will be only element 52 And, after this item, the sync pulse arrives, firstly, to the input of the read fixed memory random-access memory 54 that stores the address of the working place of the user and the identity range of certificates, who is entitled to receive an official working at the work place.

Structure codogram has the following form:

Secondly, the same impulse to read the output of the element 55 OR delayed by the delay element 57 at the time of reading the contents of a fixed cell ROM and then supplied to the clock input of the register 4, the locking code it addresses areas of memory and identity range reference, presents the highest and lowest number identifiers.

The greatest number of helpcontextid shady Comparators 23 and 24 from the output of the register 3 receives the identification number of the reference, which demanded the officer.

The pulse from the output 61 of the selector 6 is supplied to the clock input of the comparator 23. In this case, if the number of the required certificates is greater than the maximum number set for this user, then the output is “no comparison” of the comparator 23 a signal, which through the element 26 OR passes on the installation input register 3 and resets the variable portion of this register to its original state, thereby blocking the issuance of the certificate.

If the number of the required certificate shall be equal to or less than the maximum, the signal appears at the output of comparison of the comparator 23, whence it is fed to the clock input of the comparator 24 which compares the requested room with a minimum of largest room available to the current user. If the requested number is greater than or equal to the minimum, then the output “comparison” of the comparator 24 receive the clock signal, which first passes through the outlet 47 to the input of the interrupt server as a request signal reference, and secondly, he goes to one input of the respective elements 20 And, at the other input of which is supplied identifier code reference, and overwrites the last logon server through the outlet 45.

Thirdly, this Givet one input elements 15 And group, through which the address code memory areas storing reference the same pulse delayed element 31, is connected to the address input of the memory unit 8. After the pulse, the delayed delay elements 32 and supplied to the input of the reading unit 8, the requested data is read via the corresponding group of items 17 to 19, and one of the outputs 48 to the workplace officials.

If the trigger 10 is in the initial state, the inverted potential with direct access trigger it blocks the connection addresses of the memory areas through the elements 15 And unit 8. In this mode, a high potential with inverted output open element 13 And the elements 16 And groups that are connected to the address input 8 address zone the memory returned by the server to the input 39 and the clock pulse server sign-43 pass element 13 And connects the address storage area of the inlet 39 through the elements 16 And the groups and items 22 OR group. The same pulse, the delayed element 33 at the time of installation address, the recording reference, prepared by the server at the user's request.

Thus, the introduction of new units and new constructive relationships will significantly improve the reliability of the data protection system from nesactium the s system users.

Sources of information

1. U.S. patent No. 0505651, M CL G 06 F 13/40, 13/38, 1992.

2. U.S. patent No. 05129083, M CL G 06 F 12/00, 15/40, 1992 (prototype).

Claims

The distribution management system data in the information network of gas “Vybory”, containing the first register, the information input of which is the first information input system clock input connected to the output of the first element And one input of which is the first clock input of the system and the corresponding output of the first register is connected to the information input of the first memory block, the first selector address information whose input is connected to the corresponding output of the first register, a clock input connected to the output of the first element And the second register, an information input connected to the information output of the first selector address, synchronizing the output of which is connected to the clock input of the second register, the elements OR the first group, one input of which is connected with the corresponding output of the second register, other inputs connected to the outputs of the respective elements And the first group, one of the inputs of which are the first address input of the system, and output e is connected to the output of the first delay element, the first synchronizing system output, control input reading is connected to the output of the second element, And the output of the first memory block is the first information system output, the second delay element, the input connected to the output of the first delay element, and the output connected to the set inputs of the first and second registers and to the input of the third delay element, the output of which is connected with one input of the second element And whose output is connected to the input of the fourth delay element and to the other input elements And the first group, the third register, the information inputs which are the second information input of the system, and the clock input is the second synchronizing input of the system, the first trigger, a single entrance which is the third synchronizing input of the system, installation input connected to the output of the fourth delay element, a direct output of the first flip-flop connected to another input of the second item, and the inverted output connected to another input of the first element And the fifth delay element, the output of which is connected to the input of the sixth delay element, the element OR the output of which is connected to the set input of the second trigger and the third is by the fourth clock input system, the second memory block, the address input connected to the outputs of the elements OR the second group, the information input is the third information input system and the output is connected to one input elements And block elements, the outputs of which are groups of information system outputs, characterized in that it contains the second selector address information input connected to one output of the third register, a clock input connected to the second clock input of the system, the fourth register, the information input connected to the information output of the second selector address, which synchronizes the output of which is connected to the clock input of the fourth register, installation input connected to the output element OR the first comparator, the information input of which is connected to another output of the third register and to the first output of the fourth register, the clock input of the first comparator is connected to the synchronizing output of the second selector addresses, and one output connected to one input element OR the second comparator, the information input of which is also connected to another output of the third register and a second output of the fourth register, the Torah is connected to another input of the OR element, and the second output is the second synchronizing system output, the decoder, the input of which is connected with the third output of the fourth register elements And the second group, one input of which is connected to the fourth output of the fourth register, other inputs connected to the output of the fifth delay element and direct the second trigger, and outputs connected to one input elements OR the second group, the elements And the third group, some inputs which are the second address input of the system, the other is connected to the inverse output of the second trigger and the output of the third element, And outputs connected to the other input elements OR the second group, the seventh delay element, the input connected to the output of the third element, And an output connected to the control input of the recording of the second memory block, the control input reading which is connected to the output of the sixth delay element and with the other input elements And block elements, the third inputs are connected to the corresponding outputs of the decoder, and the elements of the fourth group, one input of which is connected to another output of the third register, other inputs connected to the second output of the second comparator, and outputs the second information output of the speed of the second trigger.

 

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