Device for controlling electronic objects

 

The invention relates to the field of measurement technology and can be used in systems of automated control and diagnostics of electronic objects. The technical result is to increase speed control in the identification of failures. The device contains the start button, the driver gate pulses, the element OR, T-trigger, elements, keys, delay element, an analog-to-digital converters, memory block of the assessment results, counters, frequency multiplier pulses of the comparison circuit, the memory blocks of the signs of failure, the registers, the block output. 3 Il.

The invention relates to the field of measurement technology and can be used in systems of automated control and diagnostics of electronic objects.

A device for monitoring the parameters of containing the object of control, analog-to-digital Converter, unit variance, and estimation of parameters, element, OR an element And trigger the pulse generator, a counter, a memory unit, registers, delay element, the switch signals, switches, block the stimulating signals and output unit of the control (see copyright sweeties control of the object due to the need to measure a large number of different parameters, describing its technical condition.

The closest to the technical nature of the claimed invention is a device for controlling analog objects containing the key, analog-to-digital Converter, the comparison circuit, the memory blocks, registers, output unit information, click “start”, shaper Gating pulses, a counter, a multiplier frequency pulse, delay element, the set of reference signals, blocks the multiplication, frequency Converter, a phase shifter, the switch driver grid frequency, integrators, block squaring, the adder and the power rating (see USSR author's certificate No. 1718189, CL G 05 In 23/02, publ. 7.03 1992, bull. No. 9).

The disadvantage of this device is the low performance of the diagnostic control object. This is because for the identification of failures in the facility must measure the N values of the coefficient of mutual differences between the reference and the monitored signals. When N>>1, that is caused by the need to ensure the required accuracy of recognition failure (minimizing the probability of false identification). The duration of the measurement for a single value of the coefficient of mutual differences are not less �232D/img_data/84/842142.gif">

where Zto(t) and Ze(t) is a function of time, determine patterns, respectively, of the controlled and reference signals;(t) is a function of time, coupled by Hilbert with Ze(t); Reand T -, respectively, the power and the period of the reference signal.

The main task, which directed the inventive device is to increase speed control electronic objects in the identification of failures.

This assumes control of the object to be implemented in two stages:

at the first stage (the evaluation phase) to obtain N samples of the measurement results during the duration T of one period of the signal (and not to spend on each sample time T, as implemented in the prototype);

in the second phase (phase analysis) during the time T to carry out the identification of the obtained results of the evaluation signal with a class definition of a technical condition (denial) of the object.

This technical result is achieved by the fact that in the known device for the implementation of the first phase control to the driver gate pulses, the first key, analog-to-digital Converter and the delay element is additionally introduced the first item, Staroverova phase control addition to the multiplier frequency pulses, the diagrams compare registers and the block of output data are input to the second counter and the memory blocks of the signs of failure, and to control the stages of control to the start button and the first counter is additionally introduced element OR, the flip-flop and two elements And (second and third).

In Fig.1 shows a structural electrical diagram of the device.

Device for controlling electronic objects contains 1 button start, driver 2 Gating pulses, item 3, OR T-trigger 4, the first element 5 And two keys 6 and 7, the delay element 8, two analog-to-digital Converter 9 and 10, block 11 of RAM evaluation results, the first counter 12, the second element 13 And the multiplier 14 frequency pulses, a second counter 15, scheme 161-16mcomparison blocks 171-17mmemory signs of failure, the registers 181-18mblock 19 output data, and the third element 20 I.

In Fig.2 and 3 shows examples of the results of the evaluation of the control object when the following failures: Fig.2 - failure of the driver of the third harmonic component of the digital signal; Fig.3 - disruption of forming the filter, leading to rejectee signal components above the fifth harmonic. In this case, Fig. 2 and 3,and illustrate 32D/chr/916.gif">t, and Fig. 2,b and 3 b - state unit 11 RAM evaluation results after the first stage of the control.

The device operates as follows.

Before you begin the flip-flop 4, block 11 of RAM evaluation results, as well as the registers 18 are in the initial (reset) state. In cells blocks 17 of the memory contains information about the signs of the failure of the object.

When pressing button 1 start voltage is applied to the input of the shaper 2 Gating pulses and, through the element 3 OR the input of the T flip-flop 4, throwing him into a state of logical “unit”. With direct access T-flip-flop 4, the voltage of positive polarity is supplied to the input of the first element 5 I.

The analyzed signal from the test object is supplied to the information input keys 6 (directly) and 7 (via the delay element 8). The gate pulses from the shaper 2 through the open element 5 And the control inputs of the keys 6 and 7, provide samples of values of the signal at intervals of time T/N, where T is the period of the signal. The results of the samples are fed to the inputs of analog-to-digital converters 9 and 10 and then transformed to corresponding inputs of a block 11 of RAM evaluation results.

Unit 11 of each of the readout of the measured signal results in a logical “unit” is written in the (AB)-th memory cell, which corresponds to the a-th level of the output signal of the inverter 9 (as-I line conditional matrix) and b-th level of the output signal of the transducer 10 (b-th column of the conditional matrix). In Fig.2,b and 3 b logical “units” correspond to the shaded matrix elements.

The gate pulses from the output of the driver 2 receives the input of the first counter 12. When calculating the N-th pulse output of the counter 12 through the second input element 3 OR the signal on the flip-flop 4, throwing it into a state of logical “zero”, then the counter 12 is reset to zero. The device is switched from a mode estimation signal mode of analysis results. The first element 5 and closes, And the voltage of positive polarity with the inverted output of the T-flip-flop 4 opens the second element 13 And passing through the gate pulses from the output of the imaging unit 2 to the input of the multiplier 14 pulses. The coefficient of the multiplication is equal to the number n

From the output of the multiplier 14 pulses with a repetition rate NN/T proceed to the second counter 15, which is connected to the control inputs of the circuits 161-16mcomparison. The first information input circuits 161-16mcomparison is connected to the output of block 11 one connected to the outputs of the blocks 171-17mmemory signs of failure.

The code sequence output from the output of the second counter 15 provides a consistent comparison of the contents of the memory cells of block 11 to the information stored in the respective cell blocks blocks 171-17mmemory signs of failure. In the presence of a logical “units” in the memory cell block 11 and in similar (with the same number of rows and the number of conditional matrix, the memory cell of any unit 17j(1jM) from the output of the corresponding circuit 16jthe comparison signal is a logical “unit” will be available in the appropriate register 18. After analyzing the status of the last (NN)-th memory cell block 11 the number of the register 18 with the maximum number of logical “units” will match the block number 17 memory characteristic failure, in which the recorded information, to the greatest extent appropriate to the content of the block 11 RAM of the results of the evaluation signal.

The outputs of the registers 181-18mconnected to the information input unit 19 to output information. After admission (NN)-th pulse from the multiplier 14 to the input of the counter 15 with its second output is R is s at the output of the second counter 15 corresponds to the N-th pulse, counted by the first counter 12 at the second stage operation of the device, the output of the counter 12 through the third element 20 And an outdoor voltage with the inverted output of the T-flip-flop 4, is fed to the control input unit 11 of RAM for its “zeroing”. This output signal of the counter 12 is supplied through the element 3 OR the input of the T flip-flop 4, throwing him into a state of logical “unit”. The device returns to its original position and ready to operate in the first mode estimation signal.

The total duration of operation of the device in both modes (assessment and analysis) is equal to two periods of the signal, which is much faster than in the control object using the prototype, when the time to obtain a single reference was not less than the period of the signal, and the number of samples N>>2.

Claims

Device for controlling electronic objects containing connected in series with the start button and the driver gate pulses, a first counter, connected in series, the first key and the first analog-to-digital Converter, a delay element, a multiplier frequency pulse, M schema comparison, the M registers and output unit of information is connected to the corresponding output of the comparison circuit, characterized in that additionally introduced element OR, T-trigger, three element, And a second counter, the second key, the second analog-to-digital Converter, a memory block of the assessment results and M memory blocks signs of failure, the output of each of which is connected to the second information inputs of the respective schemes comparison, the first information input of which is connected to the output of the block RAM of the evaluation results, the first information input connected to the output of the first analog-to-digital Converter, and the second information input from the output of the second analog-to-digital Converter, the inlet of which is connected to the output of the second key information the input of which is connected to the output of the delay element, the input of which is combined with the input of the first key and an input device, and the control inputs of the second and the first key is connected to the output of the first element And the first input of which is connected to the direct output of the T flip-flop whose input is connected to the output element OR the first input connected to the start button, and the second input with the output of the first counter, the input of which together with the second input of the first element And connected to the output of the shaper strawberryhead multiplier frequency pulses, the output of which is connected to the input of the second counter, the first output of which is connected to the control inputs M schema comparison and the second output of the second counter connected to the control input of the output information, the output of which is the output device, the control input of the block RAM of the evaluation results is connected to the output of the third element And the first input of which is connected to the output of the first counter and the second input of the third element And with the second input of the second element And is connected to the inverse output of the T flip-flop.

 

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