Device synchronization pulses

 

The invention relates to a pulse technique and can be used in automation devices, computing, and measurement techniques. Technical result achieved - increased reliability and enhanced functionality by optimizing the number of elements. The device contains seven elements AND IS NOT (1-7), the input bus 8, the output bus 9, 10 and 11, the tire 12 clock pulses, the capacitor 13. Introduced elements 6 and 7 AND do NOT resolve temporary restrictions on synchronized sequences of pulses, and the input elements 4 and 5 AND IS NOT allowed to form a complete synchronous clock pulses. 2 Il.

The invention relates to a pulse technique and is intended for use in automation devices, computing, and measurement techniques.

It is known device, which is described in U.S. patent No. 3382455, CL 331-111, 07.11.88. The device contains a chain of logic elements, each of which is connected to the two inputs of the subsequent elements, each element input connected to the outputs of the previous two, and bus control and the clock signal is connected directly to the corresponding inputs of one of the elements, the management bus the AI pulse shall meet the following requirement, whereby the duration of the control pulse must be longer than the length of clock pulses, but less than its period. The duration of the clock pulse should be as short as possible. This condition defines the low reliability of the device due to possible failure of synchronization and reduces its functionality, as it is only used for pulse shaping, and to synchronize this device can only be used after pre-selection pulses.

A device according to patent No. 1226636, CL N 03 To 5/24 9 December 1992, which can be used for synchronization pulses. This device comprises a comparison element, which is connected to the input of the direct trigger output type RS and the first input element of coincidence AND IS NOT, the second input is a clock input, the third input element AND IS NOT connected to the direct output of the trigger, the output element AND is NOT output short pulse synchronous clock and connected to the input of the opposite setup trigger.

The disadvantage of these devices that sync pulses necessary to fulfill the condition on which the duration of the control pulse must be longer than the length of tactoe condition reduces the reliability of the device due to possible failure of synchronization and reduces its functionality, as it is only used for komprimovane (comparison) pulses, and for synchronizing such a device can only be used with the specified constraints at the time of receipt of the pulses. To ensure the required time limits, you can enter the selectors on the input device, which complicates and reduces its reliability.

A device for the selection of the clock pulse in patent No. 1525876, CL N 03 To 5/01, 5/153 of 9 December 1992, which contains a D-flip-flop, the output of which is connected to the output bus, s and R inputs are connected with the bus clock pulses, RS-trigger and the control bus, the first and second pulse shapers, the first input of which is connected with the bus clock pulses, the output to the R input of RS flip-flop, the output of which is connected to the D-input of D-flip-flop, S input through the second shaper pulses from the control bus.

Such a device can be used for synchronization pulses, as temporary restrictions on the synchronized sequence shot, but even the minimum performance required eleven elements AND IS NOT, which complicates the device and reduces its reliability. In addition, this device does not receive pulses of the desired duration synchronously with the Adelina minimum duration with a minimum performance of device failure due to quantization levels and not the perception of the subsequent elements, AND IS NOT, which further reduces the reliability.

The closest technical solution is the device described in the patent No. 1221728, CL N 03 To 5/15, 3/284 from December 9, 1992

The device has an input and output bus, the bus clock pulses, the condenser, the three elements, the first input of the first and the second input of the second of which is connected to the input bus, the output of the first element is connected with the first inputs of the second and third, the output of the second element is connected to an output bus and to the second input of the third, the output of which is connected to a second input of the first, the third input of the second element is used to supply clock pulses, and a capacitor connected between the outputs of the first and third elements.

A disadvantage of the known device is its lack of reliability and low functionality for synchronization irregular sequence input (control) pulses to the regular sequence of clock pulses. This is because synchronization pulses necessary to fulfill the condition on which the duration of the control pulse must be longer than the length of clock pulses, but less than its period. The duration of the clock pulse should be dostaticcompression reliability of such devices is low, because it may lead to distortion of the period of the output pulses, if the duration of the clock pulse is longer than the length of the control pulse. If instead the output of the two elements AND IS NOT performing the function of storing the result of comparison from one element AND NOT, to use a more sophisticated trigger, triggered, for example, from the front (slice) of the clock pulse, then the reliability will be reduced from complications of device, item number, AND IS NOT required to implement only the functions of such actuation of the trigger from the front (slice) of the clock pulse. Thus, the known device with a small number of elements AND requires NO time limit imposed on magdelaine intervals synchronized sequences of pulses, or during the implementation of the device on a larger number of logic elements AND IS NOT, decreases the reliability from complications of this device the number of elements and their relationships.

The purpose of the invention is to enhance reliability and enhanced functionality by optimizing the number of elements AND their relations to ensure synchronization irregular sequence of pulses to the clock pulses with simultaneous allocation of spruce is achieved by in the device synchronization pulses containing the input and output bus, the bus clock pulses, the condenser, the three elements, the first input of the first and the second input of the second of which is connected to the input bus, the output of the first element is connected with the first inputs of the second and third, the output of the second element is connected to an output bus and to the second input of the third, the output of which is connected to a second input of the first, the third input of the second element is connected to a bus for supplying clock pulses, and a capacitor connected between the outputs of the first and third elements, the input elements AND NOT from the fourth to the seventh and two output bus synchronized clock pulses, the first of which is connected to the output of the fourth element and the first input of the fifth element, the output of which is connected to the second output bus synchronized clock pulses and to the first input of the fourth element, a second input connected to the output bus and the first input of the sixth element, the second input is connected to the seventh output, the first input connected to the input bus and a second input connected to the fourth input of the second element and the output of the sixth element, a third input connected to the second input of Patton AND IS NOT, in Fig.2 is a timing diagram explaining the operation of the device.

Device synchronization pulses contains 1, 2,...,7 with the first seven elements AND IS NOT, the input and output bus 8 and 9, two output bus synchronized clock pulses 10 and 11, the bus clock pulses 12, a capacitor 13. The first input of the first element 1 AND the second input of the second element 2 AND IS NOT and the first input of the seventh element 7 AND IS NOT connected to the input bus 8. The output of the first element AND IS NOT connected to the capacitor plate 13, the first input of the second element 2 AND IS NOT and the first input of the third element 3 AND IS NOT, the output of which is connected to the other capacitor plate 13 and the second input of the first element 1 AND IS NOT. The output of the second element 2 AND IS NOT connected with the second input of the third element 3 AND, with the second input of the fourth element 4 AND IS NOT, to the first input of the sixth element 6 AND IS NOT, and the output bus 9. The third input of the second element 2 AND IS NOT, the second input of the fifth element 5 AND the third input of the sixth element 6 AND IS NOT connected to input bus clock pulses 12. The output of the fourth element 4 AND IS NOT connected to the first output bus synchronized clock pulses 10 and the first input of the fifth element 5 AND IS NOT, the output of which is connected to the second output bus synchronise the fourth input of the second element 2 AND IS NOT and the second input of the seventh element 7 AND IS NOT, the output of which is connected to a second input of the sixth element 6.

Device synchronization pulses is as follows.

In the initial state at the outputs of the elements 1, 2, 5, 6, 7 (Fig.2B, d, C, e, I) the level of logical units, and the outputs of the elements 3 and 4 (Fig.2G, j) - logic level zero, resulting in the capacitor 13 is charged.

If on the bus 8 will operate the unit level (see Fig.2B), the triggered element 7, the output of which is zero (Fig.2i), at the output of element 6 - level logical units (Fig.2E).

When on the bus 12 (Fig.2A) single level on the output element 2 is zero (Fig.2D), at the output of element 4 - unit level (Fig.2ZH), and the output element 3 will begin increasing levels (Fig.2G). Single level at the output of element 4 (Fig.2ZH) changes the state of the element 5, the output of which is zero (Fig.2H). The increase of the level of the output element 3 gives the possibility to change the state of the element 1, however, because of the high potential capacitor plates connected to the output of the element 1, such a change does not change the potential of its output, and the capacitor 13 begins its overcharging.

As soon as the charging capacitor 13 project element 2, which is installed in the original one state. Thus, at the output of element 2 (Fig.2D), the impulses, the duration of which is determined by the overcharge of the capacitor 13 to the threshold of this item 2.

Slice clock pulse on the bus 12 (Fig.2A) element 5 changes its state, the output of which is a single level (Fig.2H), which returns the element 4 (Fig.1G) in the initial state.

Thus, when a single level on the bus 8, the output element 4 (Fig.2ZH) allocated full clock pulse, and the output element 2 (Fig.2D) pulse, the duration of which is determined by the timing capacitor 13 and, therefore, more 3t, where t is the propagation time of the signal in a single element.

The slice of the input pulse on the bus 8 after the action of the clock pulse at the output of the elements 1 and 7 appear isolated levels (Fig.2B, and). Single level on the output of the element 1 after overcharging of the capacitor 13 sets the element 3 in the zero state (Fig.2 g).

The front of the clock pulse on the bus 12 (Fig.2A), arrived at a zero level on the bus 8 (Fig.2B) causes the zero level at the output of element 6 (Fig.2E), which blocks the element 2 in a single state. If the bus is 8 obrazuetsya element 7 (Fig.2i), as the elements 6 and 7 formthe trigger logic 2I at the entranceand item 6 continues to block element 2 in a single state. Only after cutoff of the pulse on the bus 12 element 6 (Fig.2E) acquires a single level and only on the front of the next pulse on the bus 8 element 7 becomes zero (Fig.2i), which blocking element 6 in a single position (Fig.2E). Therefore, selection of the clock pulse in this case is not happening, and in the stage of bringing to the initial state of charge of the capacitor 13 has no effect on elements 2 and 1, however, being included in the feedback circuit element 3, only affects the shape of its output signal. In these cases, the function element 3 is the creation of a chain of overcharging of the capacitor 13, and the output waveform is not determinative. The output signal of element 2 will be formed depending on the value of its threshold and parameters of the integrating circuit, collected on the element 1 and the capacitor 13, and the element 3 will ensure the efficiency of the proposed device synchronization pulses.

A case is possible when the bus is 8 single level valid after the front of the clock pulse on the bus 12, to change the meet place the zero level (Fig.2D), at the output of the element 4 is formed of a single potential (Fig.2ZH), and the output element 3 will begin increasing levels (Fig.2 g). Single level at the output of element 4 (Fig.2ZH) changes the state of the element 5, the output of which is zero (Fig.2H). Raising the level at the output of element 3 (Fig.2G) gives the possibility to change the state of the element 1, however, because of the high potential capacitor plates connected to the output of the element 1, such a change does not change the potential of its output, and the capacitor 13 begins its overcharging. Because the bus is 8 arose zero potential before the end of the charging capacitor 13, from the zero level on the bus at the output of element 2 occurs a single level, specifying in this case, the pulse duration on the bus 9 (Fig.2D) until the end of the transitions in elements 3 and 1. In this case, the pulse duration at the output of element 2 (Fig.2D) and on the bus 9 depends on the level of coincidence of the individual potentials of the control and clock pulses on the tire 8 and 12 and not quantized with the level of potential output element 1 (Fig.2B).

If the pulse on the bus 8 (Fig.2B) will change from zero on the unit between the slice and the front adjacent clock pulses on the bus 12 (Fig.2A), the pulses from Shi at the output of which produces a zero level (Fig.2E), which, in turn, blocks the element 2. Slice clock pulse from bus 12 element 6 is returned to its original state (Fig.2E).

Thus, when using only the seven elements AND IS NOT isolated as a full clock pulse, and a duration of more than 3t, and at a zero level on the bus 8 pulses from the bus 12 selected can not be. The reliability of the device in this case, increasing not only due to the minimal number of elements AND IS NOT, but at the expense of the locking element 2 AND IS NOT output from the entered element 6 AND IS NOT forming member 7 AND NOTthe trigger logic 2I at the entrancethat warns the false appearance of an output pulse if the front of the control pulse ahead of the front of the clock pulse. This lock and removes the limitation on the duration of the clock pulse and does not allow for his actions appear to repeated pulses of matches, which is false for synchronization. The presence breathalyser capacitor in comparison with the prototype, provides not only obtain the desired pulse width, but also improves the reliability of the actuation element 4 AND which, together with the entered item 5 AND NOT form a simple b the capabilities of the device. If the capacitor 13 in the device of the prototype increases the reliability of the formation, and the reliability of the synchronization did not depend on him, in the proposed device the condenser 13, jointly and because of the blocking action of the introduced element 6, increases the reliability of the synchronization pulses. Due to the action of the totality of characteristics of the proposed device achieves the technical and economic effect that is specified in the objectives of the invention.

Claims

Device synchronization pulses containing the input and output bus, the bus clock pulses, the condenser, the three elements, the first input of the first and the second input of the second of which is connected to the input bus, an output of the first element AND IS NOT connected with the first inputs of the second and third elements, AND IS NOT, the output of the second element AND IS NOT connected to an output bus and to the second input of the third element AND IS NOT, the output of which is connected with the second input of the first element AND IS NOT, the third input of the second element AND IS NOT connected to the bus to clock pulses, and a capacitor connected between the outputs of the first and third elements AND, wherein the input elements AND NOT from the fourth to the seventh and two output bus of synchronize ATAGO element AND-NOT, the output of which is connected to the second output bus synchronized clock pulses and to the first input of the fourth element AND IS NOT, a second input connected to the output bus and the first input of the sixth element, AND IS NOT, the second input is connected to the output of the seventh element AND-NOT, the first input connected to the input bus and a second input connected to the fourth input of the second element AND-NOT and the output of the sixth element, AND IS NOT, a third input connected to the second input of the fifth element AND-NOT and the bus clock pulses.

 

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