The trigger device


H03K3/29 - PULSE TECHNIQUE (measuring pulse characteristics G01R; mechanical counters having an electrical input G06M; information storage devices in general G11; sample-and-hold arrangements in electric analogue stores G11C0027020000; construction of switches involving contact making and breaking for generation of pulses, e.g. by using a moving magnet, H01H; static conversion of electric power H02M; generation of oscillations by circuits employing active elements which operate in a non-switching manner H03B; modulating sinusoidal oscillations with pulses H03C, H04L; discriminator circuits involving pulse counting H03D; automatic control of generators H03L; starting, synchronisation, or stabilisation of generators where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
H03K3/037 - PULSE TECHNIQUE (measuring pulse characteristics G01R; mechanical counters having an electrical input G06M; information storage devices in general G11; sample-and-hold arrangements in electric analogue stores G11C0027020000; construction of switches involving contact making and breaking for generation of pulses, e.g. by using a moving magnet, H01H; static conversion of electric power H02M; generation of oscillations by circuits employing active elements which operate in a non-switching manner H03B; modulating sinusoidal oscillations with pulses H03C, H04L; discriminator circuits involving pulse counting H03D; automatic control of generators H03L; starting, synchronisation, or stabilisation of generators where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

 

The invention relates to a pulse technique and can be used in computer equipment and control systems. The technical result is to increase the noise immunity and in odnoaremenno ternary code. The device comprises two clocked dvuhstvornyh D-flip-flop (1) and (2), two switches (3) and (4), four resistor (5) to(8), two capacitor (9) and (10), two EXCLUSIVE OR element (11) and (12), two inverter (13) and (14), two element AND-NOT (15) and (16), the bus counting signals (17), two output bus (18) and (19), the control bus (20). The device operates in the mode of addition or subtraction mode depending on the signal on the control bus (20), represents one digit of the counter in odnoaremenno ternary code. 1 Il.

The invention relates to the field of pulse technique and can be used in the counting devices of computer engineering and control systems.

Known tractability counting trigger (see and.with. The USSR №585591, CL N 03 To 3/286, publ. 25.12.77, bull. No. 47), is selected as the analogue of the invention and containing three RS-flip-flop, each of which is arranged on Tregubova and two-input logic elements AND NOT with cross-links, shemo counting signals. The outputs of two-input elements AND are the first outputs of the respective RS-triggers. The first and second inputs of two-input elements AND are NOT, respectively, the first and second inputs of the corresponding RS-triggers. The first and second inputs trehshipovyh elements AND are NOT, respectively, third and fourth inputs of the respective RS-triggers. The first inputs of the first, second and third trehshipovyh output elements AND are NOT, respectively, the first, second and third inputs of the control circuit. The second inputs of the first, second and third trehshipovyh output elements AND are NOT, respectively, the fourth, fifth and sixth inputs of the control circuit. The third inputs of the first, second and third trehshipovyh output elements AND are NOT, respectively, the seventh, eighth and ninth input of the control circuit. The outputs of the first, second and third trehshipovyh output elements AND are NOT, respectively, the first, second and third outputs of the control circuit. The first outputs of each of the RS-flip-flops are connected, respectively, with the first, second and third inputs of the control circuit, the outputs of which are the respective outputs of the device. The first inputs of the RS-flip-flops connected with Shi is, the second and third RS-triggers connected to third inputs, respectively, of the third, first and second RS-trigger. The fourth input of the first RS-flip-flop is connected with the fourth and sixth inputs of the control circuit and the second output. The fourth input of the second RS-flip-flop is connected to the fifth and the seventh input of the control circuit and the third output. The fourth input of the third RS flip-flop is connected to the eighth and ninth input of the control circuit and the first output.

A disadvantage of the known trigger is low immunity, due to the absence of protection measures trigger the structures included in its composition, from the external impulse noise.

Known trigger device (see RF patent №2093955 from 16.04.93, IPC: N 03 To 3/29, “Tractability counting trigger, option 2, Shishkin, I., Dikarev I. I., publ. 20.10.97, bull. No. 29), selected as a prototype and containing first and second dvuhtarifnye triggers, the first inputs of which are connected with the bus of the counting signals, the inverted output of the first dvukhstadiinogo trigger connected to the first input element AND the output of which is connected to the first output bus, a second output bus, the EXCLUSIVE OR element, two switch, three resistors and a capacitor. Dvuhtarifnye triggers to perform the first of which is connected to the first input of the EXCLUSIVE OR element and with direct input of the first switch. The output of the first switch via the first resistor is connected to the first output of the second resistor and the first capacitor plate, the second plate which is connected to the information input of the second D-flip-flop and through the third resistor from the output of the second switch. An inverse input of the second switch is connected to the second output bus and to the output of the EXCLUSIVE OR element, a second input connected to the direct output of the second D-flip-flop and a second input element. The output element AND IS NOT connected to the negative input of the first switch, the control input of which is connected with the control input of the second switch and bus counting signals. The information input of the first D-flip-flop is connected with the second output of the second resistor.

The first disadvantage of the prototype is a low immunity due to high rates of failure under the effect of external noise on the bus counting signals and the power bus. Upon receipt of each of the second counting pulse in the trigger device is charging the capacitor. If instead of the second counting pulse is received by the impulse interference limited duration, the capacitor may have time only to discharge and the trigger device from the second ustawie discharged capacitor. This corresponds to the loss of two counting pulses.

The second disadvantage is the inability to ensure the operation of the trigger device in odnoaremenno ternary code due to the inability of the switching device when the overflow from the addition mode in the subtraction mode and back.

The problem solved by the claimed invention is the creation of a trigger device having high immunity to external interference and the ability to work in odnoaremenno ternary code.

The technical result is to increase the noise immunity and in odnoaremenno ternary code.

This is achieved in that the trigger device containing the tire of counting signals, the first element AND whose output is connected to the first output bus, the first element of XOR, the output of which is connected to the second output bus, the first and second dvuhtarifnye triggers, made by CMOS technology in the form of a clocked D-flip-flops, the clock inputs are connected together and are connected to control inputs of the first and second switches, the output of the first switch via the first resistor is connected with the first findings of the first capacitor and the second resistor, second the m input of the first switch and to the first input of the first EXCLUSIVE OR element, the second input is connected to the first input of the second switch and the output of the second D-flip-flop, information whose input is connected to the first output of the third resistor. What's new is that inputs of the second EXCLUSIVE OR element, the first and second inverters, the fourth resistor and the second AND gate, the output of which is connected to the clock inputs of the first and second D-flip-flops, the first input with the output of the second inverter, the second input with the output of the first inverter and the first input of the first element AND the second input connected to the input of the second inverter and the output of the second EXCLUSIVE OR element, the first input connected to an inverted output of the first D-flip-flop, and the second input to the third input of the first EXCLUSIVE OR element, the second input of the second switch and a control bus, a second input of the first switch is connected to the first input of the second switch, the output of which through the fourth resistor is connected to the second output of the third resistor and to the first output of the second capacitor, the second terminal of which is connected to a common bus, the input of the first inverter is connected to the bus of the counting signal, the second terminal of the first capacitor is connected to a common bus.

Pointed to by the Oia rates of failure by eliminating overcharging of the capacitor when receiving the pulses and to ensure the operation of this device in odnoaremenno ternary code by switching the trigger device when the overflow from the addition mode in the subtraction mode and back.

The drawing shows a schematic diagram of a trigger device.

The trigger device comprises two clocked dvuhstvornyh D-flip-flop 1 and 2, made by CMOS technology, two switches 3, 4, four resistor 5, 6, 7, 8, two condensers 9, 10, two EXCLUSIVE OR element 11, 12, two inverter 13, 14, two elements AND NOT 15 and 16, the tire of counting signals 17, two output bus 18, 19 and the control bus 20.

Clock inputs of D-flip-flops 1 and 2 have been combined and connected to the joint control inputs of the switches 3 and 4 and to the output of element AND-NOT 15. The output of the switch 3 through the resistor 5 is connected with the second output of the resistor 7, the first output of which is connected to the information input of D-flip-flop 1, the output of which is connected to the first and second inputs of the switches 3, 4, respectively, and to the second input of the EXCLUSIVE OR element 11. The first input of the EXCLUSIVE OR element 11 is connected to the first input of switch 4 and direct access to D-flip-flop 2, the information input through the resistor 8 is connected with the second output resistor 6, the second terminal of which is connected to the output of switch 4. Inverted output of D-flip-flop 2 is connected to the first input of the EXCLUSIVE OR element 12, a second input connected to the second input of the switch 3, on the bus, the inverter 14 is connected to the first input element AND-NOT 15 the second input is connected to the first input element AND-NOT 16 and to the output of the inverter 13, an input connected to the bus of the counting signals 17. The output of the EXCLUSIVE OR element 12 is connected to the input of the inverter 14 and the second input element AND-NOT 16, the output of which is connected to output bus 18. The second terminals of the resistors 6 and 7 are connected through capacitors 10 and 9, respectively, with a common bus.

The trigger device is a one digit counter in odnoaremenno ternary code. To build a multi-digit counter, you must connect the control bus 20 of the previous discharge from the output bus 19 subsequent discharge, and the bus counting signals 17 subsequent discharge from the output bus 18 of the previous discharge.

The trigger device operates as follows.

In the first (initial) state, in the mode information storage, D-triggers 1 and 2 are in the state of logical “0”. On the control bus 20 all bits of the counter is a signal of logical “1”, therefore, at the output of the EXCLUSIVE OR element 12 is a signal of logical “0”, prohibiting the passage of the counting signals through an AND-NOT 16 on the output bus 18 and through an inverter 14 to permit their passage through the element AND NOT 15. During the absence of MF is rtor 13 - signal is logical “0” and the outputs of the elements AND NOT 15 and 16 - signal logic “1”. In the absence of the pulses at the output of element AND-NOT 15 on the clock inputs of D-flip-flops 1, 2 and the control inputs of the switches 3 and 4 is stored signal is logical “1”, permitting writing of data in the D-flip-1, 2 with their information inputs and outputs of the switches 3, 4 are connected to its first input XI, which are connected with the direct output of D-flip-flops 1, 2. D-triggers 1, 2 are held in the state of logical “0” signals on their information inputs discharged capacitors 9, 10. At the output of the EXCLUSIVE OR element 11 is a signal of logical “1”. If under the influence of external interference D-flip-flop 1 are set to logical “1”, the output of the switch 3 will be generated signal is a logical “1”, and the condenser 9 will begin charging through resistor 5, while it is positively charged plate connected through a resistor 7 to the information input of D-flip-flop 1. If during the period of the pulse noise voltage on the capacitor 5 reaches the switching threshold of the D-flip-flop 1 in the state of logical “1” at the end of the pulse interference D-flip-flop 1 will return to the state of logical “0”. Similar to the way the persecuted logical “0” on the bus counting signals 17) at the output of the inverter 13 a signal of logical “1”, and the output element AND-NOT 15, the control inputs of the switches 3, 4 and on the clock inputs of D-flip-flops 1,2 - a logical signal “0”. D-triggers 1, 2 become insensitive to signals on their information inputs and are in a state of logical “0”. The outputs of the switches 3, 4 are connected to their first inputs X0, for which there is a signal of logical “1” and logical “0”, respectively. Therefore, the outputs of the switches 3, 4 are the signals of logic “1” and logic “0” respectively. The capacitor 9 starts to charge, and the duration of the counting of the pulse must be sufficient to charge to the supply voltage. Signal is logical “0” at the output of the EXCLUSIVE OR element 12 prevents the passage of the counting pulse on the output bus 18. After the first counting pulse D-flip-1, 2 will be set in the logical state “1” and logical “0”, respectively. On the output bus 19 is set to a logical signal “0” on the output bus 18 is stored signal is logical “1” and the control bus 20 is a signal of logical “1”. Inputs X0 switches 3, 4 are the signals of logic “1”, and the inputs XI switches 3, 4 signals of logical “1” and logiteck the CSOs counting pulse D-flip-1, 2 are in the state of logical “1” and logical “0”, respectively, on the control bus 20 is supported by a logical signal of “1” and the output element AND IS NOT 15 a signal of logical “0”. The outputs of the switches 3, 4 are connected to their first inputs X0, which have a signal of logical “1”. The capacitor 10 is charged, the duration of the counting of the pulse must be sufficient to charge to the supply voltage. At the end of the second counting pulse D-flip-flop 2 is set to be logic “1” on an output bus 19 is set to a logical signal “1”. At the output of the EXCLUSIVE OR element 12 is set to a logical signal “0” to allow passage of the following counting pulses on the output bus 18, which is supported by the logical signal “1”. The resistors 7, 8 prevents rapid discharge of the capacitors 9, 10, respectively, through the input protective diodes D-flip-flops 1 and 2, respectively, at power interruptions (Zeldin E. A. Digital integrated circuits in information-measuring equipment. - L.: Energoatomizdat, 1986, S. 65, Fig. 6-4). The resistance of the resistors 7 and 8 should be large enough.

Upon receipt of the third counting pulse D which is a logical signal “1”, from the output of the EXCLUSIVE OR element 12 is a logical signal “1” to allow passage of the pulses on the output bus 18 and forth on the bus counting signals 17 senior level meter. Third counting pulse causes the output bus 18 LSB of the counter signal is a logical “0”. Signal is logical “0” at the output of the inverter 14 prohibits the passage of the pulses through the element AND-NOT 15, setting its output signal to a logical “1”, therefore, during the term of the third counting signal D-flip-1, 2 save the state of logical “1”. After the end of the third counting pulse in the trigger device senior level counter D-triggers 1, 2 are in the state of logical “1” and logical “0”, respectively, and on the bus 19 is formed by a logical signal of “0”. On the control bus 20 is formed by a logical signal of “0”, the switching trigger device LSB counter mode of addition in the subtraction mode. The trigger device remains in the storage of information.

Upon receipt of the fourth counting pulse D-triggers 1, 2 are in the state of logical “1”. On the control bus 20 and input X0 switch 3 supported accommodation. the and the control inputs of the switches 3, 4 is set to a logical signal “0”, which causes the connection of the outputs of the switches 3, 4 to their first inputs X0, in which a signal of logical “0” and logical “1”, respectively. The capacitor 9 is discharged through a resistor 5 to a voltage logical “0”. After the end of the fourth counting pulse D-triggers 1, 2 are installed in the state of logical “0” and logical “1”, respectively. On the output bus 19 is set to a logical signal “1”, the output of the EXCLUSIVE OR element 12 is set to a logical signal “0” prohibiting the completion of the counting of the signals on the output bus 18. Trigger the device goes into storage mode information.

Upon receipt of the fifth counting pulse D-triggers 1, 2 are in the state of logical “0” and logical “1”, respectively, and the control bus 20 is supported by a logical signal of “0”. At the output of element AND-NOT 15 a signal of logical “0” and the capacitor 10 is discharged through the resistor 6 and the output of switch 4. Thus, after the end of the fifth counting pulse D-triggers 1, 2 are installed in the state of logical “0”. At the output of the EXCLUSIVE OR element 12 Junior of times the signal on the output bus 18. On the output bus 19 is set to a logical signal “0” on the output bus 18 is supported by a logical signal “1”.

Sixth counting signal, without changing the status of the device LSB of the counter, is counting on bus 17 of its senior level, which installs its D-flip-flops 1, 2 in the logical state “1”. After the end of the sixth counting signal on the control bus 20 LSB counter a signal of logical “1”. The device is returned to its original state.

Thus, this trigger device operates in the mode of addition or subtraction mode depending on the signal on the control bus 20, and in each of these modes there are three counting pulse from the bus counting signals 17 that define the steady state D-flip-flops 1 and 2. Thus the work of the triggering device in odnoaremenno ternary code, and also increases its immunity to external interference by reducing the rates of failure due to the lack of recharge capacitors 9 and 10.

Made laboratory model of a trigger device, tests proved the functionality and practical value of the proposed object.

 

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