A method of manufacturing a semiconductor device with a control electrode nanometer length

 

Usage: in the field of micro - and nanoelectronics when manufacturing semiconductor devices and integrated circuits, and devices functional microelectronics. The inventive method of manufacturing a semiconductor device with a control electrode (gate) of nanometer length enables selection on a semiconductor substrate active area of the device, forming a gate dielectric comprised of the first and second dielectrics, applying an auxiliary layer containing the third dielectric and the first metal, forming a temporary rectangular elements with vertical side walls in the auxiliary layer, and the formation of the control electrode (gate), regions of the drain/source and the conductive contact layer to the source-gate-drain. A control electrode is formed by successive deposition on rectangular elements with vertical walls of the auxiliary layer and the second dielectric substrate of the fourth dielectric plasmochemical etching the fourth dielectric with the formation of the first half of the first spacer on the vertical wall of a rectangular element, deposition and plasma chemical etching of the material prakim etching the fifth dielectric in the gate of the second half of the first spacer", the first metal supporting layer and the second dielectric gate dielectric is used as a protective mask underlying layers during plasma-chemical etching, then formed layers "spacer" - gate"spacer" is used as a mask for subsequent alloying of the contact areas of the drain/source, while the offset region doping from the Beltway. Next, form the second double-sided "spacer on the side walls of the gate and use it to conduct deep doping, as well as for the formation in contact with the silicon conductive regions of the metal silicide of the deposited layer of the second metal, then spend the destruction of the second metal, the remaining two "spacers" after cililizacia, thereby forming samoobladanie conductive contact region source-gate-drain. The technical result of the invention is to reduce the length of the control electrode to a few tens of nanometers, as well as providing the possibility of making items nanotransistor-drain, gate, source, samosobrannoy technology using any lithography in the fabrication of semiconductor devices. 1 C. and 8 C.p. f-crystals, 11 ispolzovano when manufacturing semiconductor devices and integrated circuits, and devices functional microelectronics.

A simple scaling of the modern designs of semiconductor integrated circuits in the direction of the smaller sizes to achieve a high degree of integration, increase performance, reduce energy costs faced by the fundamental limitations caused by the so-called korotkokanal effects.

The main problem associated with reducing the size of the transistor, exacerbated by the fact that the exponential increase in the number of transistors on a chip leads to exponential growth of the power consumption and, consequently, overheating of the chip, due to the resulting leakage currents. Leakage currents occur through the dielectric layer that separates the gate from the silicon substrate and between the drain and source in the "off" state of the transistor. Because reducing the size of the transistor entails a reduction in the thickness of the gate dielectric, as a consequence, begin to influence the effects of tunneling of charges through the layers of dielectric, which leads to leakage currents.

Using materials with a high dielectric constant (K30), it is possible to make the thickness of the gate dielectric Gorm - the occurrence of leakage current between drain and source, is solved by eliminating the parasitic charge in the areas of the drain and the source. This is achieved by using structures of silicon-on-insulator (SOI), where the doped region of the drain and the source, and gate, placed directly on the dielectric, and there are no areas of accumulation of spurious charge, therefore, no leakage current.

Thus, reducing the depth of the transitions and the thickness of the gate dielectric, substrate using silicon on insulator", seeking to get rid of the "korotkokanal" effects, thus reducing the size of transistors and, more importantly, the length (channel) gates of nanotransistors, therefore, to increase the speed of the integrated circuits.

In the works [1-3], the authors propose the fabrication of semiconductor devices with regard to solve the above problems on Si substrates and SOI. Unfortunately, the authors do not specify the minimum length of the control electrode and lithographic methods. We can only assume that the length of the shutter >0.1 ám, because even the use of 0.13 μm technology enables the manufacture of the device with a control electrode0.1 ám, and sledovatel solve the problem of reducing the length of the control electrode (less than 100 nm).

The closest technical solution of the invention is a method of manufacturing a semiconductor device with a control electrode submicron length and gate dielectric with a dielectric constant k>7 (Al2About3, TiO2, ZrO2and others) [3], where the authors propose the method of forming the control electrode of 0.1 μm or less) is shorter than the length defined by lithography.

The main disadvantages of this method lie in the complexity and instability (uncontrolled) formation of a shutter inside the slit mask size0.1 ám, because the depth of the slit is larger than the width of cracks (greater than 2:1). In addition, when the size of the gap0.1 µm, further narrowing the gap at the base of the mask, due to the etched layer of SiO2angle45problematic, uncontrolled and leads to unequal reproducibility of manufacturing semiconductor devices.

The technical result of the present invention is to reduce the length of the control electrode to a few tens of nanometers, production elements nanotransistor (drain, gate, source) samosobrannoy technology, use the Noah boundary frequency and the minimum noise factor, but also significantly improves the reproducibility of the parameters simplifies and cheapens the manufacture of semiconductor devices.

This is achieved by the method of manufacturing a semiconductor device with a control electrode nanometer length, including the allocation on a semiconductor substrate active area of the device, the formation of the gate dielectric, the deposition of the auxiliary layer insulator-metal, forming a temporary rectangular elements in the metal of this layer, followed by plasma-chemical etching of the unprotected this metal mask dielectric layer, the formation of the control electrode formation regions of the drain/source and the conductive contact layer to the source-gate-drain, gate is formed on the vertical side wall of the rectangular element of the auxiliary layer, which is located in the center of the active area of the device sequential deposition and plasma chemical etching of dielectric layers, conductive layer and the dielectric, due to the fact that the metal and the top layer of gate dielectric resistant to the anisotropic plasma etching (PCT) of these layers and serve as a boundary etching, resulting in the complete removal of the layer is in the auxiliary layer are formed of vertical layers "spacer"-gate"spacer" of the control electrode nanometer length who are simultaneously mask for the subsequent doping of the contact areas of the drain/source providing a bias field implant channel shutter, and the second formed "spacer"mask allows a deeper doping, reducing the capacitance between the gate and source/drain. Deposited second metal on the silicon surface, after removing the gate dielectric from a semiconductor substrate, is converted in the process of low-temperature annealing in contact with silicon in the silicide of the metal, as lying on the "spacers" metal layer is discharged, thereby forming samoobladanie conductive contact region source-gate-drain.

There is a variant in which the second dielectric is used as a mask from the damaging effects of doping ions at the surface of the semiconductor substrate.

There is also an option, where the gate dielectric with the exposed semiconductor substrate is removed after a deep doping.

Possible variants, in which the conductive layer of the control electrode use polysilicon, CoSi2, TiSi2, NiSi, and as the second metal - Co, Ti, Ni.

It is advisable as 4, Al2About3- Cr, Ni, FeNi, V, Al, Ti.

As materials for the formation of the spacers can be used, layers of SiO2Si3N4.

As the semiconductor substrate may be used a substrate of SOI or bulk silicon.

There is also an option, where the gate dielectric used layers of silicon dioxide and a dielectric with k>10 (SiO2+ZnO2, HfO2TA2About5, Al2About3).

In Fig.1-11 presents the technological sequence of manufacturing a semiconductor device with a control electrode nanometer length on the SOI substrate.

In the drawings is shown the SOI substrate 1, dielectric layer 2, comprised of silicon dioxide (first insulator), the dielectric layer 3 to>10 (second insulator), dielectric layer 4 (third dielectric auxiliary layer (SU), metal 5 (the first metal) auxiliary layer, photoresistive elements 6, the first dielectric layer, the first spacer "7 (fourth dielectric) material of the control electrode 8 (the gate), the second dielectric layer, the first spacer "9 (fifth dielectric), the dielectric layer of the second "spacer" 10 (sixth dielectric), the second metal 11, forming a conductive con the SiO214.

As the source material is taken the SOI substrate 1 (Fig.1) formed with isolated active regions of the transistors (not shown). This structure was formed gate dielectric comprised of the first dielectric 2 (SiO2and the second dielectric 3 (for example, ZrO2and the supporting layer consisting of a third dielectric 4 (for example, SiO2and the first metal 5 (e.g., vanadium). Then the auxiliary layer by photolithography formed photoresistive elements 6 (Fig.2) in the form of rectangles, the minimum size of which was determined by the desired width of the shutter located so that one side of each rectangle photoresistive element was located at the future site of the gate between the drain and source, determining a boundary of the formation of the shutter. After etching the first metal 5 (Fig.3) removed photoresistive elements 6 and PCT was travelpulse third dielectric 4, forming temporary rectangular elements auxiliary layer containing the first metal 5 on the third dielectric 4. Next was deposited fourth dielectric first 7 "spacer" (e.g., Si3N4) (Fig.4) so that a closed vertical side with whom tverdogo dielectric 7 to complete its removal on the first metal 5 and the second dielectric 3 with the formation of the fourth dielectric layer, the first half of the first 7 "Spencer". After this was done the deposition of the material of the control electrode 8 (for example, polycrystalline silicon (polysilicon) with subsequent chemical etching before formation of the next to the first dielectric layer first "Spencer" shutter 8 of polysilicon. Subsequent re-deposition of the fifth dielectric 9 (Fig.6), which is also used Si3N4and its plasma-chemical etching until the first metal 5 auxiliary layer and the second insulator 3 formed the second half of the first spacer "9 shutter 8.

It was further held removal of the residue of the first metal 5 (Fig.7) and the third dielectric layer 4 of the subsidiary, silicon doping 13 through the gate dielectric to a depth that provides a combination of surface boundaries of the p-n junctions of the drain and the source with the boundaries of the shutter 8 with the formation of the layer 15. Further on the substrate was deposited sixth dielectric 10 (Fig.8), and carried out his plasma etching with education on the vertical walls of the second two-way "spacer". This was followed by a deep silicon doping 13 with the formation of the layer 16 (Fig.9), removing the gate dielectric from an open surface of the SOI substrate (Fig.10), napalitano, drain semiconductor substrate and removing the second metal 11 from the side surfaces of the second two-way "spacer" (Fig.11).

The use of the proposed method of manufacturing semiconductor devices and integrated circuits with a control electrode nanometer length provides the following benefits:

- there is a possibility of formation of nanometer control electrode using a conventional photolithography and existing equipment;

- the possibility of sustainable formation on samosobrannoy technology areas drain-gate-source;

it becomes possible to simultaneously use the metal supporting layer and the top layer of gate dielectric to protect the surface of the semiconductor substrate from exposure to radicals, such as CF3, F3O2and other gases used in chemotherapy;

- the top layer of gate dielectric is used as a mask from the damaging effects of doping ions at the surface of a semiconductor substrate;

- the formation of the conductive contacts of the source, gate, drain is on samosobrannoy technology without the use of lithography.

These advantages provide taloto, but also improves the reproducibility of the parameters of the devices, while simplifying and reducing costs of their production.

Sources of information

[1] US Patent US 6238960 1, 2001 (Fast MOSFET with low-doped source/drain. Maszara et al.).

[2] US Patent US 6465313 Bl, 2002 (SOI MOSFET with graded source/drain silicide. Yu et al.).

[3] US Patent US 6271094 Bl, 2001 (Method of making a MOSFET with high dielectric constant gate insulator and minimum overlap capacitance. D. C. Boyd et al.).

Claims

1. A method of manufacturing a semiconductor device with a control electrode (gate) of nanometer length, including the allocation on a semiconductor substrate active area of the device, forming a gate dielectric comprised of the first and second dielectrics, applying an auxiliary layer containing the third dielectric and the first metal, forming a temporary rectangular elements with vertical side walls in the auxiliary layer, and the formation of the control electrode (gate), regions of the drain/source and the conductive contact layer to the source-gate-drain, characterized in that what control electrode is formed by successive deposition on rectangular elements with vertical walls of the auxiliary layer and the second dielectric substrate a fourth dielectric is a vertical wall of a rectangular element, deposition and plasma chemical etching of the material of the control electrode in the first half of the first spacer "shutter deposition and plasma chemical etching of the fifth dielectric in the gate of the second half of the first "spacer", the first metal supporting layer and the second dielectric gate dielectric is used as a protective mask underlying layers during plasma-chemical etching, then formed layers "spacer - gate - spacer" is used as a mask for subsequent alloying of the contact areas of the drain/source, while the offset region doping from the channel of the shutter; then by successive deposition and plasma chemical etching of the sixth dielectric form the second double-sided "spacer on the side walls of the gate and use it to conduct deep doping, as well as for the formation in contact with silicon (region source - gate - drain) conductive regions of the metal silicide of the deposited layer of the second metal, then spend the destruction of the second metal, the remaining two "spacers" after cililizacia, thereby forming samoobladanie conductive contakes from the damaging effects of doping ions at the surface of the semiconductor substrate.

3. The method according to p. 1, wherein the gate dielectric with the exposed semiconductor substrate is removed after a deep doping.

4. The method according to p. 1, wherein as the conductive layer of the control electrode use polysilicon, Si2, TiSi2, NiSi.

5. The method according to p. 1, characterized in that as the second metal are Co, Ti, Ni.

6. The method according to p. 1, characterized in that the auxiliary layer, the third dielectric and the first metal layers are used polyimide, SiO2Si3N4, Al2O3- Cr, Ni, FeNi, V, Al, Ti.

7. The method according to p. 1, characterized in that as the material for the formation of "spacers" are used layers of SiO2Si3N4.

8. The method according to p. 1, characterized in that the semiconductor substrate can be used a substrate of SOI, bulk silicon.

9. The method according to p. 1, characterized in that as the gate dielectric used layers of silicon dioxide and a dielectric with k>10 (SiO2+ZnO2, HfO2Ta2O5, Al2O3).

 

Same patents:

The invention relates to electronic devices and can be used in the manufacture of integrated circuits with increased radiation resistance

The invention relates to a method of manufacturing a nonvolatile semiconductor memory cell (SZ) with a single cell (TF) with the tunnel window, and the tunneling region (TG) using cells (TF) with the tunnel window as a mask to perform at a late stage of tunnel implantation (IT)

The invention relates to semiconductor technology and can be used for the manufacture of discrete field-effect transistors and integrated circuits

FIELD: electronic engineering.

SUBSTANCE: device provided with short channel for controlling electric current has semiconductor substrate to form channel. Doping level of channel changes extensively in vertical direction and keeps to constant values at longitudinal direction. Electrodes of gate, source and discharge channels are made onto semiconductor substrate in such a manner that length is equal or less than 100 nm. At least one of source and discharge electrodes form contact in shape of Schottky barrier. Method of producing MOS-transistor is described. Proposed device shows higher characteristics at lower cost. Reduction in parasitic bipolar influences results to lower chance of "latching" as well as to improved radiation resistance.

EFFECT: improved working parameters.

24 cl, 11 dwg

FIELD: microelectronics; integrated circuits built around silicon-on-sapphire structures.

SUBSTANCE: proposed method for manufacturing silicon-on-sapphire MIS transistor includes arrangement of silicon layer island on sapphire substrate, formation of transistor channel therein by doping silicon island with material corresponding to channel type, followed by production of gate insulator and gate, as well as source and drain regions; prior to doping silicon island with material corresponding to channel type part of silicon island is masked; mask is removed from part of silicon island of inherent polarity of conductivity upon doping its unmasked portion and producing gate insulator; in addition, part of gate is produced above part of silicon island of inherent polarity of conductivity; source region is produced in part of silicon island of inherent polarity of conductivity and drain region is produced in part of silicon island doped with material corresponding to channel type.

EFFECT: improved output characteristics of short-channel transistor at relatively great size of gate.

1 cl, 7 dwg

FIELD: integrated-circuit manufacture on silicon-on-insulator substrate; transistor structures of extremely minimized size for ultra-high-speed integrated circuits.

SUBSTANCE: proposed method for manufacturing self-aligning planar two-gate MOS transistor on SOI substrate includes production of work and insulator regions of two-gate transistor on wafer surface, modification of hidden oxide, formation of tunnel in hidden oxide, formation of polysilicon gate and drain-source regions; upon formation of insulator and work regions; supporting mask layer is deposited onto substrate surface and ports are opened to gate regions to conduct ionic doping of hidden oxide with fluorine through them; then doped part of oxide under silicon is removed by selective etching to form tunnel in hidden oxide whereupon silicon surface is oxidized in open regions above tunnel and gate is formed; port in supporting layer and tunnel are filled with conductive material, and gate-source regions are produced upon etching supporting layer using gate as mask. Transistor structure channel length is up to 10 nm.

EFFECT: reduced length of transistor structure channel.

2 cl, 1 dwg

FIELD: physics.

SUBSTANCE: invention relates to semiconductor technology. The method of making power insulated-gate field-effect transistors involves making a protective coating with a top layer of silicon nitride on the face of the initial silicon nn+ or pp+ - substrate, opening windows in the protective coating, making channel regions of transistor cells in the high-resistivity layer of the substrate and heavily-doped by-pass layers and source regions inside the channel regions using ion implantation of doping impurities into the substrate through windows in the protective coating and subsequent diffusion distribution of implanted impurities. When making by-pass layers, the doping mixture is implanted into the substrate through windows in the protective coating without using additional masking layers. After diffusion redistribution of implanted impurities in by-pass layers on the entire perimetre of windows in the protective coating, selective underetching of lateral ends of the protective coating under silicon nitride is done. The silicon nitride layer is then removed from the entire face of the substrate and source regions of the transistor cells are formed through implantation of doping impurities into the substrate through windows in the protective coating.

EFFECT: invention is aimed at increasing avalanche break down energy, resistance to effect of ionising radiation and functional capabilities of silicon power transistors.

5 dwg, 1 tbl

FIELD: physics; semiconductors.

SUBSTANCE: invention concerns electronic semiconductor engineering. Essence of the invention consists in the manufacturing method of SHF powerful field LDMOS-transistors, including forming of a primary sheeting on a face sheet of an initial silicon body with top high-resistance and bottom high-alloy layers of the first type of conductance, opening of windows in a primary sheeting, sub-alloying of the revealed portions of silicon an impurity of the first type of conductance, cultivation of a thick field dielectric material on the sub-alloying silicon sites in windows of a primary sheeting thermal oxidising of silicon, creation in a high-resistance layer of a substrate in intervals between a thick field dielectric material of elementary transistor meshes with through diffused gate-source junctions generated by means of introduction of a dopant impurity of the first type of conductance in a substrate through windows preliminary opened in a sheeting and its subsequent diffused redistribution, forming of connecting busbars and contact islands of a drain and shutter of transistor structure on a thick field dielectric material on a face sheet of a substrate and the general source terminal of transistor structure on its back side, before silicon sub-alloying and cultivation of a thick field dielectric material in windows of a primary sheeting a high-resistance layer of a substrate is underetched on the depth equal 0.48 - 0.56 of thickness of a field dielectric material, and before dopant impurity introduction in the formed source crosspieces of transistor meshes in a high-resistance layer of a substrate in sheeting windows etch a channel with inclined lateral walls and a flat bottom depth of 1.5 - 2.6 microns.

EFFECT: improvement of electric parametres of SHF powerful silicon LDMOS transistors and increase of percentage output of the given products.

5 dwg, 2 tbl

FIELD: physics.

SUBSTANCE: in a field-effect transistor which includes an oxide film as a semiconductor layer, the oxide film has a channel part, a source part and a drain part, and concentration of one of hydrogen or deuterium in the source part and in the drain part exceeds that in the channel part.

EFFECT: invention enables to establish connection between the conducting channel of a transistor and each of sources and drain electrodes, thereby reducing change in parameters of the transistor.

9 cl, 13 dwg, 6 ex

FIELD: electricity.

SUBSTANCE: in manufacturing method of semiconductor device, which involves processes of ion implantation and formation of active areas of instrument on silicon substrate, after formation of active areas there created is hidden p-layer under channel of instrument by alloying of substrate with Be ions with energy of 125-175 keV, dose of (2-5)·1012 cm-2 and with further annealing at 650-750°C during 20-30 minutes and H2 atmosphere.

EFFECT: reducing leakage current values in semiconductor devices, providing processibility, improving parameters, reliability and increasing percentage yield.

FIELD: electricity.

SUBSTANCE: in the method for manufacturing of a semiconductor device including formation of a semiconductor substrate of the first type of conductivity, a gate electrode formed above a subgate dielectric and separated with interlayer and side insulation from a metal source electrode (emitter), a channel area of the second conductivity type and a source area of the first conductivity type, formed by serial ion alloying of admixtures into windows of the specified shape in the gate electrode, and the metal source electrode, a subgate dielectric is developed, as well as a gate electrode and interlayer insulation above the gate electrode in a single photplithographic process by plasma-chemical feeble anisotropic etching with ratio of vertical and horizontal components of etching speed making (3÷5)/1.

EFFECT: reduced resistance in open condition without increasing dimensions of a crystal and improved efficiency without deterioration of other characteristics.

11 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: manufacturing method of SHF LDMOS transistors includes growth of thick field dielectric at surface of high-ohmic epitaxial p- -layer of source silicone p-p+-substrate at periphery of transistor configurations, formation of source p+-junctions and p-wells of transistor cells in epitaxial p- -layer of substrate not covered with field dielectric, growth of gate dielectric and formation of polysilicone electrodes of transistor cells gate in the form of narrow lengthwise teeth of rectangular section with close adjoining tapped contact pads from source side over p-wells, creation of high-alloy n+-areas of sink, source and low-alloy n-area of transistor cells by introduction and further diffusion redistribution of donor dopant using gate electrodes as protective mask, formation of metal electrodes of sinking, source, screens and buses shunting gate electrodes of transistor cells through tapped contact pads at substrate face and common metal source electrode of transistor configuration at backside, the first degree of low-alloy multistage n-area of transistor cell source is formed after formation of source p+-junctions by introduction of donor dopant to epitaxial p--layer of substrate without usage of protective masks, p-wells, sink and source areas of transistor cells are created with use of additional dielectric protective mask identical in configuration and location of lengthwise teeth of polysilicone gate electrode without tapped contact pads adjoining to them, simultaneously with p-wells similar areas are formed at edges of low-alloy n-area of transistor cells sink and gate electrodes with tapped contact pads adjoining to teeth are formed after removal of additional dielectric protective mask and subsequent growth of gate dielectric, at that width of polysilicone gate electrode teeth are selected so that it exceeds length of transistor cell induced channel per overlay error value.

EFFECT: improvement in electric parameters of powerful silicone generating SHF LDMOS transistors, increase of their resistance to ionising radiation exposure and increase of production output in percents.

7 dwg

FIELD: electricity.

SUBSTANCE: transistor based on a semiconductor compound comprises a semiconductor plate, a channel and a contact layers, ohmic contacts of a source and a drain, made on the basis of a thin-film compound of Ge and Cu, and a gate, where thin films of barrier-forming metal, a diffusion barrier and a conductor are installed in layers on a semiconductor plate. The gate conductor material is a thin-film compound of Ge and Cu with thickness of 10-1,000 nm, with mass content of Ge in the range of 20-45%.

EFFECT: higher thermal stability of gate parameters, lower value of reduced contact resistance of ohmic contacts of a source and a drain.

6 cl, 6 dwg, 1 tbl

Up!