Device for frame synchronization

 

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal. The technical result is the extension of functionality by providing information transfer with asynchronous merging of digital streams of the first to fourth levels with views of the phase modulation of the FM-4, FM-8 and various types of quadrature-amplitude modulation in which one clock signal at the input device corresponds To the information signals. Device for frame synchronization includes random access memory device, the device configuration and diagnostics, the decoder synchronously, generating equipment, environment unit, prescrotal signals, the decoder counter. 1 C.p. f-crystals, 2 Il.

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal.

The known device for frame synchronization [1, 2, 3], containing the shift register, the detector clock cycle, the analyzer matches the clock, unit retention and retrieval of synchronism, the x device is:

- the impossibility of the same device to synchronize the various transmission information with asynchronous merging of digital streams of the first to fourth levels;

- significant hardware costs, because the distribution of the positions of synchronously on the large length of the cycle (a few thousand bits) required the shift register with the same bit width.

The closest to the technical nature of the claimed invention is selected as a prototype device for frame synchronization [4], containing random access memory device, the device configuration and diagnostics, the storage device criteria input in synchronism, and the storage device criteria exit synchronism, the decoder synchronously, environment unit, generating equipment.

The disadvantage of this device is:

- the impossibility of synchronization in digital transmission with views of the phase modulation of the FM-4, FM-8 and various types of quadrature-amplitude modulation in which one clock signal at the input device corresponds To the information signals.

An object of the invention is the extension of functionality by providing one device regulated by swedami phase modulation of the FM-4, FM-8 and various types of quadrature-amplitude modulation in which one clock signal at the input device corresponds To the information signals.

This task is solved in that the device for frame synchronization, containing the first random access memory device, the device configuration and diagnostics, the decoder synchronously, environment unit, generating equipment, and the clock input devices for frame synchronization is connected to the corresponding inputs of the decoder synchronously and generator equipment, the address outputs of which are connected to the corresponding inputs of the first memory device and the address are output devices for frame synchronization, the output of the reading, recording output and the first output of the selection device configuration and diagnostics are connected to the corresponding inputs of the first memory device, the input/output end of the super-frame, which is connected with the respective input generating equipment, with a corresponding input/output device configuration and diagnostics and is the output end of the multiframe device for frame synchronization, the input/output end of singlecompartment, environment devices and input/output device configuration and diagnostic inputs/outputs position synchronously and values of synchronously first random access memory connected to respective inputs/outputs of the device configuration and diagnostics and the corresponding inputs of the decoder synchronously, the output response which is connected with the respective input environment of the device, the output of the zero state which is connected with the respective input generator equipment, inputs clock cycles settings and options are in zero which is connected to respective outputs of the device configuration and diagnostic information inputs/outputs, input mode selection, new address, set to zero, write, read, customizable random access memory, select memory device or register device configuration and diagnostics are the corresponding inputs of the device for frame synchronization, the output of the availability of the synchronization environment of the device is appropriate output device for frame synchronization, the input mode selection generating equipment connected to the corresponding input device is trojstva, prescrotal signals, the counter and decoder, and the address inputs entered operational storage devices connected to respective outputs of the generator equipment, the outputs of the positions of synchronously and outputs values synchronously for the respective positions entered operational storage devices connected to respective inputs/outputs of the device configuration and diagnostics, and to the corresponding inputs of the decoder synchronously, information inputs which information output device for frame synchronization connected to respective outputs of Perestroikas signals, a clock input and a clock input of the counter is connected with the respective input device for frame synchronization, the information inputs of Perestroikas signals connected to respective inputs of the device for frame synchronization, the outputs of the device configuration and diagnostics that determine the number of information inputs of the device for frame synchronization, connected to respective inputs of the decoder, the input bits which are connected with the corresponding outputs of bits of the counter, the input end rebuild which is similar to the input g is dynany to the corresponding inputs of Perestroikas signals, the output of the zero state of the environment the device is connected to the corresponding input of the counter, the input end of synchronously which is connected with the corresponding output of the first memory device, the inputs read inputs and write the entered memory devices connected to respective outputs of the device configuration and diagnostics, the outputs of which are connected to the selection input is entered the corresponding memory devices.

Prescrotal signal contains the first K-1 triggers, where K equals the number of information inputs, and To groups of valves, with each group contains valves To valves, and information inputs from the second to K-th Perestroikas signals are connected to information inputs, respectively, of the trigger from the first to the (K-1)-th, the first information input of Perestroikas signals connected to the inputs from the first to K-th gates of the first group of gates, the second information input of Perestroikas signals connected to the inputs of the second to K-th gates of the second group of valves, the third information input of Perestroikas signals connected to the inputs from the third to the K-th gates of the third group of valves, (K-1)-th informationonly entrance of Perestroikas signals connected to the input For the second valve To the second group of valves, informational inputs between the third and the (K-1)-th inputs of Perestroikas signals connected to the inputs of gates groups located between the third and the (K-1)-th groups of valves, in accordance with the procedure of the compounds described above, the output of the first flip-flop connected to the input of the first valve and the second group of gates, the output of the second trigger is connected to the inputs of the first and second gates of the third group of gates, the output of the (K-2)-th flip-flop is connected to the inputs from the first to the (K-2)-th gates (K-1)the second group of gates, the output of the (K-1)-th flip-flop is connected to the inputs from the first to the (K-1)-th gates To the second group of valves, the information outputs of the triggers that are located between the second and the (K-2)-th flip-flops, connected to the inputs of gates groups located between the third and the (K-1)-th groups of valves, in accordance with the procedure of the compounds described above, the control input 1 of Perestroikas signals connected to the control inputs of gates, the sequence number in which the groups of gates corresponds to the ordinal number of the group of valves, the control input 2 of Perestroikas signals connected to the control inputs of gates, the sequence number in which the groups of gates from the first to the (K-1)-th is determined by the ordinal number of the group of valves is increased above 3 Perestroikas signals connected to the control inputs of gates, the sequence number in which the groups of gates from the first to the (K-2)-th is determined by the ordinal number of the group of gates increased by the number 2, and the K-th and (K-1)-th groups of gates is the ordinal number of the group of valves, reduced by the number of K-2, the control input of the K-1 Perestroikas signals connected to the control inputs of gates, the sequence number in which the first and second groups of gates is determined by the ordinal number of the group of gates plus the number of K-2, and in groups of gates from the third to the K-th - the ordinal number of the group of valves, reduced by the number 2, the control input To Perestroikas signals is connected with the control input of the K-th gate of the first group of valves and control inputs of gates from the second to K-th group of valves, in which the sequence number of the valves is determined by the ordinal number of the group of valves, reduced by the number 1, the control inputs located between the third and the (K-1)-m control inputs of Perestroikas signals, is connected with the control inputs of gates in accordance with the order of connection described above, the same outputs of gates from the first to K-th group of gates connected with each other and with relevant information outputs of Perestroikas signals, the clock is th solution is available in the claimed device new circuit elements: 12,..., 1kRAM, Perestroikas signals, the counter and decoder.

Thus, the invention meets the criterion of "novelty."

Analysis of the known technical solutions in the study and related fields allows us to conclude that the introduced functional units known. However, their introduction into the device for frame synchronization with the above links gives it new properties. Introduced functional units interact in such a way that allow you to extend its functionality by providing one device frame synchronization of a wide class of transmission of information with asynchronous merging of digital streams of the first to fourth levels with views of the phase modulation of the FM-4, FM-8 and various types of quadrature-amplitude modulation in which one clock signal at the input device corresponds To the information signals.

Thus, the invention meets the criterion of "inventive step", as it is for the expert is not obvious from the prior art.

The invention can be used in digital communication systems with asynchronous merging of digital streams.

Thus, sobremesa device for frame synchronization, in Fig.2 is a circuit diagram of Perestroikas signals.

Device for frame synchronization (Fig.1) contains a random access memory 11,..., 1kthe device configuration and diagnostics 2, the decoder synchronously 3, generating equipment 4, environment unit 5, prescrotal signals 6, a decoder 7, a counter 8, and a clock T input device for frame synchronization is connected to the corresponding inputs of the decoder synchronously 3 and generator equipment 4, the address 0,..., N, the outputs of which are connected to corresponding inputs of RAM 11and address are 0,..., N outputs of the device for frame synchronization, the output of the read SECOND, the record coming out and WE first select CE1device configuration and diagnostics 2 connected to respective inputs of the first memory device 11the input/output end of the multiframe KSC which is connected with the respective input generator equipment 5, with the respective input/output device configuration and diagnostics 2 and is the output end of the multiframe KSC device for frame synchronization, the input/output end of synchronously Kaishakunin 3, environment device 5 and the input/output device configuration and diagnostics 2, inputs/outputs position synchronously UCS1and values of synchronously PCC1the first memory device 11connected to respective inputs/outputs of the device configuration and diagnostics 2 and the corresponding inputs of the decoder synchronously 3, the output response of the IC which is connected with the respective input environment of the device 5, the output of the zero state of the DS is"0" which is connected with the respective input generator equipment 4 input clock cycles settings T and setting to zero RES which is connected to respective outputs of the device configuration and diagnostics 2, information, 0,..., N inputs/outputs, inputs mode select DIR, new address, set to zero RES, WE write, read ND, select the custom of RAM And0... , Andn, set the RAM or register RAM/RG device configuration and diagnostics are the corresponding inputs of the device for frame synchronization, the output of the availability of synchronization F. environment device 5 is the corresponding output device for frame sync is La frame synchronization, address 0,..., N inputs RAM 12,..., 1kconnected to respective outputs of generator equipment 4, UCS2,...,PSKkoutputs the positions of synchronously and KYC2,..., PCCkoutputs values synchronously for the respective positions of the RAM 12,..., 1kconnected to respective inputs/outputs of the device configuration and diagnostics 2 and to the corresponding inputs of the decoder synchronously 3, information And1... , Andkthe inputs of which information And1... , Andkthe outputs of the device for frame synchronization connected to respective outputs of Perestroikas signals 6, clock t of the input clock and the T input of the counter 8 are connected with the respective input device for frame synchronization, information And1... , Andkthe inputs of Perestroikas signals 6 are connected to the corresponding inputs of the device for frame synchronization, outputs And0,..., Andevice configuration and diagnostics that determine the amount of information And1... , Andkinput device for frame synchronization, connected to respective inputs of the decoder 7, the value of which is similar to the input frequency generating equipment connected to the corresponding output of the decoder 7, control 1,..., K, the outputs of which are connected to corresponding inputs of Perestroikas signals 6, the output of the zero state DS"0" environment device 5 is connected with the corresponding input of the counter 8, the CSC input end of synchronously which is connected with the corresponding output of RAM 11the inputs read TH and recording inputs WE RAM 12,..., 1kconnected to respective outputs of the device configuration and diagnostics 2, the outputs of the selection CE2,...,CEkwhich are connected respectively to the inputs of the selection CE2,...,CEkRAM 12,..., 1k.

Prescrotal signals (Fig.2) contains triggers 91,..., 9k-1where K equals the number of information inputs, and To groups of valves, with each group contains valves To valves, and information And2... , Andkthe inputs of Perestroikas signals 6 are connected to the appropriate information inputs triggers 91,..., 9k-1information H1 entrance of Perestroikas signal 6 is connected to the inputs from the first to K-th gates of the first group of gates, information And1the entrance of Perestroikas signal 6 is connected to the input is connected to the inputs from the third to the K-th gates of the third group of valves, information And2the entrance of Perestroikas signal 6 is connected to the inputs (K-1)-th and K-th gates (K-1)-th group of gates, information Andkthe entrance of Perestroikas signal 6 is connected to the input For the second valve To the second group of valves, informational inputs between information And3andk-1inputs of Perestroikas signals 6 are connected to inputs of gates groups located between the third and the (K-1)-th groups of valves, in accordance with the procedure of the compounds described above, the trigger output is 91connected to the input of the first valve and the second group of gates, the output of the trigger 92connected to the inputs of the first and second gates of the third group of gates, the output of the trigger 9k-2connected to the inputs from the first to the (K-2)-th gates (K-1)-th group of gates, the output of the trigger 9k-1connected to the inputs from the first to the (K-1)-th gates To the second group of valves, the information outputs of the triggers, located between triggers 92and 9k-2connected to the inputs of gates groups located between the third and the (K-1)-th groups of valves, in accordance with the procedure of the compounds described above, managing 1 input of Perestroikas signal 6 is connected to the control inputs of gates, the sequence number in which the groups of gates salewski the inputs of gates, the sequence number in which the groups of gates from the first to the (K-1)-th is determined by the ordinal number of the group of gates increased by 1, and in the K-th group of valves is the ordinal number of the group of valves, reduced by the number K-1, managing 3 input Perestroikas signal 6 is connected to the control inputs of gates, the sequence number in which the groups of gates from the first to the (K-2)-th is determined by the ordinal number of the group of gates increased by the number 2, and the K-th and (K-1)second groups of gates is the ordinal number of the group of valves, reduced by the number of K-2, managing To-1 input of Perestroikas signal 6 is connected to the control inputs of gates, the sequence number in which the first and second groups of gates is determined by the ordinal number of the group of gates plus the number of K-2, and in groups of gates from the third to the K-th - the ordinal number of the group of valves, reduced by the number 2, managing To the entrance of Perestroikas signal 6 is connected with the control input of the K-th gate of the first group of valves and control inputs of gates from the second to K-th group of valves, in which the sequence number of the valves is determined by the ordinal number of the group of valves, reduced by the number 1, the control inputs located between managers is soedineniya, as described above, the same outputs of gates from the first to K-th group of gates connected with each other and with relevant information And1... , andkthe outputs of Perestroikas signals 6, clock T the entrance of Perestroikas signal 6 is connected to the clock inputs of flip 91,..., 9k-1.

Device for frame synchronization (Fig.1) works as follows. Device for frame synchronization (CA) has two modes of operation. The first mode of operation and diagnosis, and the second operation mode.

In the first mode, the input device settings and diagnostics 2 (UND) receives signals from the controller working in conjunction with the personal electronic computing machine (PC). Mode settings and diagnostics allowed the signal Log."0", which is fed to the input mode selection (input DIR) UND 2. The Signal Log."1" at the input select RAM or register (input RAM/RG) UND 2, you can customize random access memory devices (RAM). Select custom RAM is made by the selection signals custom RAM coming in binary code And0... , Andninputs UND 2. When you configure the first RAM (OSU1) input select (input CE1) with N11output read (output OE) UND 2 on the appropriate input OSU1signal Log."1". On the input set to zero (input RES) UND 2 signal Log."1". Output setup to zero (output RES) UND 2 signal Log."1" is supplied to the corresponding input of the generator equipment 4 (TH), setting it to zero state. Address 0,..., N outputs TH 4 connected to respective address inputs OSU1,..., OSUk. Further according to the recording signal coming from the recording output (output WE) UND 2 on the appropriate input OSU1in the last at address zero in the discharge position of the end of the multiframe (input/output KSC), the position of the end of synchronously (input/output KCK), the position of synchronously (input/output UCS1), the position values of synchronously (input/output KYC1) writes data received from the respective inputs/outputs UND 2. Then input the new address (input) UND 2 signal, which, coming from the output cycle setting (output T) UND 2 on the appropriate input TH 4, carries out the change of address OSU1.

Next, the write data at the new address is the same as described above.

To verify the settings OSU1signal installation in the Nol is the following which the signal Log."1received on the input record (log CE) UND 2 and then output WE UND 2 on the appropriate input OSU1the latter is translated into a read mode. Then the signal Log."0" is received at the input read (input OE) UND 2 and then output OE UND 2 on the appropriate input OSU1is reading information from OSU1in his address zero. The signals from the I/o CSC, CSC, PSC1, PCC1the last act on the corresponding inputs/outputs AND 2 and then to the controller PC to compare them with the original. Then at a signal the new address is the address change OSU1and reading of data at the new address in the same way as described above.

Similarly, you can set and verify that you have properly configured the following RAM. Number custom RAM is set by the signals on the a0... , Andninputs UND 2. The amount of RAM in the device for frame synchronization based on the number of inputs/outputs.

After you configure and verify the settings for all RAM is the setting of the register memory, located in UND 2. Configuration register memory allowed by the signal Log."0", coming on RAM/RG input UND 2. The order attitude is in the information input device for frame synchronization in binary code comes on And0... , Andnoutputs UND 2 and then to corresponding inputs of a decoder 7.

The transfer device for the CA mode is performed by the signal Log."1" at the input DIR UND 2. While the selection signals received from CE1,...,CEkoutputs UND 2, may be permitted OSU,..., Ozuk, and the signal Log."1 and the Log."0", coming respectively from the outputs WE write and read TH UND 2 to corresponding inputs of RAM, the latter are transferred to the read data.

In setup mode input clock cycles settings (log TN) item counter TH 4 receives the clock pulses from the corresponding output UND 2, and in mode clock input (input T) counter position TH 4 receives clock pulses from clock input (input T) devices for CA.

The operation of the device for the CA as follows. The address inputs (inputs 0,..., N) OSU1,..., OSUkreceived signals from the respective outputs of the FIRST 4, with the output end of the multiframe, the end of synchronously, the position of synchronously, values synchronously respective RAM are formed corresponding signals. According to the signal output end of the multiframe (output KSC) OSU1in TH 4 is a synchronous setting in the zero state Schnee common multiple between the length of the transmission cycle and the number of information inputs. Signal the end of synchronously from the output end of synchronously (exit CSC) OSU1the signals of the positions and values of synchronously from the corresponding OSU1,..., OSUkinformation signals from the respective information outputs (outputs And1... , Andk) Perestroikas signal 6, and the clock signal from clock input (input T) devices for the CA act to corresponding inputs of a decoder of synchronously 3 (DS). DS 3 provides comparison information signals with predetermined OSU1,..., OSUkthe positions of synchronously, also defined in OSU1,..., OSUkand the outcome of the comparison at the output of the response (output IC). In case of a positive response to IC output DC 3 a signal is generated the Log."1, and in case of a negative response signal Log."0". The signal response from the IC output DC 3 and the signal of the end of synchronously with CSC output OSU1go to corresponding inputs of environment of the device. Before the first positive response from the IC output DC 3 environment unit 5 (FU) is in the zero state and the signal Log."1" coming from the zero output state (output DC"0") FU 5 to corresponding inputs of the FIRST 4 and the counter 8, the resolution is on its KSK input signal from the corresponding output OSU1and then the clock signal at its T input from the respective input devices for CA. The signals from the outputs of the bits of the counter 8 outputs 0,..., N) in the binary code are received at the respective inputs of the decoder 7, the signals from the control outputs (outputs 1,..., K) are fed to the corresponding inputs of the PS 6. The presence of a signal on one of the governors 1,..., K inputs PS 6 determines the order the rebuild of information signals with information And1... , Andkinput devices for the CA to corresponding inputs of PS. The number of control inputs of the PS 6 is determined by the number of information inputs of the device for the CA. In the absence of positive responses on the IC output DC 3 after the occurrence of a signal on the control To the output of the decoder 7 a signal from the output end rebuild (output KP) decoder 7 counter 8 is set in the zero state, and the FIRST 4 are removed (blank) a single clock cycle. Signal the end of the rebuild is formed by the coincidence of signals, determining the number of information inputs of the device for the CA coming from the outputs (outputs And0,..., An) UND 2 to corresponding inputs of a decoder 7, and signals from outputs (outputs 0,..., N) of bits of the counter according to the first singlecompany. At IC output DC 3 a signal of the positive feedback that comes on the appropriate input 5 FU. After receipt of the relevant inputs FU 5 signal positive response and signal the end of synchronously reversible counter the latter is set in the positive mode account and increases its state unit. When this signal Log."0", formed at the Palace of sports"0" output FU 5 it is forbidden to work the remover of tact TH 4 and the counter 8. Thereby prohibited the further rebuilding of the information signals received at the inputs of the PS 6. Thus, when the presence of a signal of positive responses on the IC inlet FU 5 reversible counter recent increases your status on the unit, and in the absence decreases by one. When the difference in the number of signals of positive and negative feedback reaches specified in FU 5 value, the device for the CA enters the mode of synchronism, as evidenced by the signal Log."1" at the output (output f) synchronization FU 5. In this mode, the device for the CA is as long as the difference in the number of signals of negative and positive feedback reaches specified in FU 5 values. When this FU 5 is set in the zero state the use of Perestroikas signals 6 and tick remover TH 4 information signals are converted and sent to the output in order when the first bit of the multiframe transmission is located on the first information output.

Prescrotal signals (Fig.2) works as follows. When the presence of a signal at the first control input (input 1) of Perestroikas signal 6 (PS) open valves, whose numbers in the groups correspond to the group number. While the current values of the information signals from the information And1... , Andkinput PS 6 go through the open gates respectively on information And1,..., Hkthe outputs of PS 6.

When the presence of a signal on the second control input (input 2) PS 6 open valves order number in groups of gates from the first to the (K-1)-th is determined by the ordinal number of the group of gates is increased by one, and in the K-th group of valves is the ordinal number of the group of valves, reduced by the number K-1. Thus memorized in the trigger 9k-1the signal received from the information Andkinput PS 6 on the D-input of the trigger, with the release of the latest fed to the information And1the output of PS 6, and the current values of the information signals from the information And1... , Andk-1input PS 6 act accordingly on the information And2... , Andkthe outputs of PS 6.

When the presence of a signal on Tretiak-2)-th is determined by the ordinal number of the group of valves, increased by the number 2, and the K-th and (K-1)-th groups of gates is the ordinal number of the group of valves, reduced by the number of K-2. Thus memorized in triggers 9k-2 and 9k-1 signals received information Andk-1andkinput PS 6 on D inputs, respectively, triggers 9k-2and 9k-1with outputs of the last act on the information And1and2the outputs of PS 6, and the current values of the information signals from the information And1... , Andk-2input PS 6 act accordingly on the information And3... , Andkthe outputs of PS 6.

When the presence of a signal on the control K-1 log PS 6 open the valves, the sequence number in which the first and second groups of gates is determined by the ordinal number of the group of gates plus the number of K-2, and in groups of gates from the third to the K-th - the ordinal number of the group of valves, reduced by the number 2. Thus memorized in triggers 92,..., 9k-1the signals received information And1... , Andkinput PS 6 on the D-inputs, respectively, triggers 92,..., 9k-1with outputs of the last act accordingly on the information And1... , Andk-2the outputs of PS 6, and the current values of the information signals from the information And1and1,..., 9k-1the signals received information And2... , Andkinput PS 6 on the D-inputs, respectively, triggers 91,..., 9k-1with outputs of the last act accordingly on the information And1... , Andk-1the outputs of PS 6, and the current value of the information signal with information And1input PS 6 is supplied respectively to information Andkthe output of PS 6.

When the presence of a signal on one of the governors from the fourth to the (K-2)-th inputs prescrotal signal operates in accordance with the procedures described earlier.

For the technical realization of the device for frame synchronization used static random access memory (RAM) imported type KM68257CJ-15 firms and the SEC user programmable logical integrated circuit (PPLIS) XC4020XLA by XILINX.

The present invention allows cyclic synchronization of the various transmission information with asynchronous merging of digital streams of the first to fourth levels with views of FA is the input device corresponds To the information signals.

Claims

1. Device for frame synchronization, containing the first random access memory device, the device configuration and diagnostics, the decoder synchronously, environment unit, generating equipment, and the clock input devices for frame synchronization is connected to the corresponding inputs of the decoder synchronously and generator equipment, the address outputs of which are connected to the corresponding inputs of the first memory device and the address are output devices for frame synchronization, the output of the reading, recording output and the first output of the selection device configuration and diagnostics are connected to the corresponding inputs of the first memory device, the input/output end of the super-frame, which is connected with the respective input generator equipment, with the appropriate input/output device configuration and diagnostics and is the output end of the multiframe device for frame synchronization, the input/output end of synchronously the first memory device is connected to the corresponding inputs of the decoder synchronously, environment devices and input/output is pout random access memory connected to respective inputs/outputs of the device configuration and diagnostics and the corresponding inputs of the decoder synchronously, the output response which is connected with the respective input environment of the device, the output of the zero state which is connected with the respective input generator equipment, inputs clock cycles settings and options are in zero which is connected to respective outputs of the device configuration and diagnostic information inputs/outputs, input mode selection, new address, set to zero, write, read, customizable random access memory, select memory device or register device configuration and diagnostics are the corresponding inputs of the device for frame synchronization, the output of the availability of the synchronization environment of the device is appropriate output device for frame synchronization, input mode selection generating equipment connected to the respective input device for frame synchronization, characterized in that the input from the second to K-th memory device, prescrotal signals, the counter and decoder, and the address inputs entered operational storage devices connected to respective outputs of the generator equipment, the outputs of the positions of synchronously the TV connected to respective inputs/outputs of the device configuration and diagnostics, and to the corresponding inputs of the decoder synchronously, information inputs which information output device for frame synchronization connected to respective outputs of Perestroikas signals, a clock input and a clock input of the counter is connected with the respective input device for frame synchronization, the information inputs of Perestroikas signals connected to respective inputs of the device for frame synchronization, the output device settings and the diagnosis, determine the number of information inputs of the device for frame synchronization, connected to respective inputs of the decoder, the input bits which are connected with the corresponding outputs of bits of the counter, the input end rebuild which is similar to the input frequency generating equipment connected to the corresponding output of the decoder, control outputs which are connected to corresponding inputs of Perestroikas signals, the output of the zero state of the environment the device is connected to the corresponding input of the counter, the input end of synchronously which is connected with the corresponding output of the first memory device, the inputs read inputs and write the entered memory devices connected to the Bohr introduced the respective memory devices.

2. The device under item 1, characterized in that prescrotal signals includes first to (K-1)-th flip-flops, where K equals the number of information inputs, and To groups of valves, with each group contains valves To valves, and information inputs from the second to K-th perestroika signals are connected to information inputs, respectively, of the trigger from the first to the (K-1)-th, the first information input of Perestroikas signals connected to the inputs from the first to K-th gates of the first group of valves, the second information input of Perestroikas signals connected to the inputs of the second to K-th gates of the second group of valves, the third information input of Perestroikas signals connected to the inputs from the third to the K-th gates of the third group of valves, (K-1)-th information input Perestroikas signals connected to the inputs (K-1)-th and K-th gates (K-1)-th group of valves, To the second information input of Perestroikas signals connected to the input For the second valve To the second group of valves, informational inputs between the third and the (K-1)-th inputs of Perestroikas signals connected to the inputs of gates groups located between the third and the (K-1)-th groups of valves, in accordance with the procedure of the compounds described above, the output of the first trigger connection is the second gates of the third group of valves, output (K-2)-th flip-flop is connected to the inputs from the first to the (K-2)-th gates (K-1)-th group of gates, the output of the (K-1)-th flip-flop is connected to the inputs from the first to the (K-1)-th gates To the second group of valves, the information outputs of the triggers that are located between the second and the (K-2)-th flip-flops, connected to the inputs of gates groups located between the third and the (K-1)-th groups of valves, in accordance with the procedure of the compounds described above, the control input 1 of Perestroikas signals connected to the control inputs of gates, the sequence number in which the groups of gates corresponds to the ordinal number of the group of valves, the control input 2 of Perestroikas signals connected to the control inputs of gates, the sequence number in which the groups of gates from the first to the (K-1)-th is determined by the ordinal number of the group of gates increased by 1, and in the K-th group of valves is the ordinal number of the group of valves, reduced by the number K-1, the control input 3 of Perestroikas signals connected to the control inputs of gates, the sequence number in which the groups of gates from the first to the (K-2)-th is determined by the ordinal number of the group of gates increased by the number 2, and the K-th and (K-1)-th groups of gates is the ordinal number of the group of valves is reduced by h the EP in which the first and second groups of gates is determined by the ordinal number of the group of valves, increased by the number of K-2, and in groups of gates from the third up To the seventh, the ordinal number of a group of valves, reduced by the number 2, the control input To Perestroikas signals is connected with the control input of the K-th gate of the first group of valves and control inputs of gates from the second to K-th group of valves, in which the sequence number of the valves is determined by the ordinal number of the group of valves, reduced by the number 1, the control inputs located between the third and the (K-1)-m control inputs of Perestroikas signals, connected with the control inputs of gates in accordance with the order of connection described above, the same outputs of gates from the first to K-th group of gates connected with each other and with relevant information outputs of Perestroikas signals, the clock input of Perestroikas signals is connected with a clock input from the first to the (K-1)-th flip-flops.

 

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The invention relates to a device and method for forming words frame synchronization in an asynchronous communication system with multiple access and code division multiplexing

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal

The invention relates to a method of transmitting digital data and can be used for frame synchronization in systems robust data protection with application of the adjustment, in particular, concatenated codes

The invention relates to the transmission of discrete information and can be used for frame synchronization in systems robust protection using corrective, in particular concatenated codes

The invention relates to systems for the transmission of discrete data and can be used for frame synchronization in systems robust data protection that apply corrective, in particular concatenated codes

Device sync cycles // 2192711
The invention relates to communication technology and can be used for receiving data from a downhole telemetry system using looped packets of digital data

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal

FIELD: digital communications.

SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.

EFFECT: higher reliability, higher effectiveness, higher interference resistance.

1 cl, 3 dwg

FIELD: communications.

SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.

EFFECT: higher trustworthiness.

1 dwg

FIELD: digital communications;

SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.

EFFECT: enlarged functional capabilities.

1 cl, 2 dwg

FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.

SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.

EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.

1 dwg

FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.

EFFECT: increased interference resistance of device for cyclic synchronization.

4 dwg

FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.

SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.

EFFECT: expanded functional capabilities of device for cyclic synchronization.

2 cl, 3 dwg

FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.

SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.

EFFECT: increased interference resistance of cyclic synchronization.

2 cl

FIELD: data processing in broadband radio communications and radio navigation.

SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.

EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.

2 cl, 9 dwg

FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.

SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.

EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.

1 cl, 9 dwg

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